[PATCH] Make mkcompile_h use LANG=C and LC_ALL=C for $CC -v
[linux-2.6.git] / arch / powerpc / platforms / chrp / pci.c
1 /*
2  * CHRP pci routines.
3  */
4
5 #include <linux/kernel.h>
6 #include <linux/pci.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/ide.h>
11
12 #include <asm/io.h>
13 #include <asm/pgtable.h>
14 #include <asm/irq.h>
15 #include <asm/hydra.h>
16 #include <asm/prom.h>
17 #include <asm/gg2.h>
18 #include <asm/machdep.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/grackle.h>
22 #include <asm/rtas.h>
23
24 #include "chrp.h"
25
26 /* LongTrail */
27 void __iomem *gg2_pci_config_base;
28
29 /*
30  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
31  * limit the bus number to 3 bits
32  */
33
34 int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
35                            int len, u32 *val)
36 {
37         volatile void __iomem *cfg_data;
38         struct pci_controller *hose = bus->sysdata;
39
40         if (bus->number > 7)
41                 return PCIBIOS_DEVICE_NOT_FOUND;
42         /*
43          * Note: the caller has already checked that off is
44          * suitably aligned and that len is 1, 2 or 4.
45          */
46         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
47         switch (len) {
48         case 1:
49                 *val =  in_8(cfg_data);
50                 break;
51         case 2:
52                 *val = in_le16(cfg_data);
53                 break;
54         default:
55                 *val = in_le32(cfg_data);
56                 break;
57         }
58         return PCIBIOS_SUCCESSFUL;
59 }
60
61 int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
62                             int len, u32 val)
63 {
64         volatile void __iomem *cfg_data;
65         struct pci_controller *hose = bus->sysdata;
66
67         if (bus->number > 7)
68                 return PCIBIOS_DEVICE_NOT_FOUND;
69         /*
70          * Note: the caller has already checked that off is
71          * suitably aligned and that len is 1, 2 or 4.
72          */
73         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
74         switch (len) {
75         case 1:
76                 out_8(cfg_data, val);
77                 break;
78         case 2:
79                 out_le16(cfg_data, val);
80                 break;
81         default:
82                 out_le32(cfg_data, val);
83                 break;
84         }
85         return PCIBIOS_SUCCESSFUL;
86 }
87
88 static struct pci_ops gg2_pci_ops =
89 {
90         gg2_read_config,
91         gg2_write_config
92 };
93
94 /*
95  * Access functions for PCI config space using RTAS calls.
96  */
97 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
98                      int len, u32 *val)
99 {
100         struct pci_controller *hose = bus->sysdata;
101         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
102                 | (((bus->number - hose->first_busno) & 0xff) << 16)
103                 | (hose->index << 24);
104         int ret = -1;
105         int rval;
106
107         rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
108         *val = ret;
109         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
110 }
111
112 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
113                       int len, u32 val)
114 {
115         struct pci_controller *hose = bus->sysdata;
116         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
117                 | (((bus->number - hose->first_busno) & 0xff) << 16)
118                 | (hose->index << 24);
119         int rval;
120
121         rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
122                          addr, len, val);
123         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
124 }
125
126 static struct pci_ops rtas_pci_ops =
127 {
128         rtas_read_config,
129         rtas_write_config
130 };
131
132 volatile struct Hydra __iomem *Hydra = NULL;
133
134 int __init
135 hydra_init(void)
136 {
137         struct device_node *np;
138         struct resource r;
139
140         np = find_devices("mac-io");
141         if (np == NULL || of_address_to_resource(np, 0, &r))
142                 return 0;
143         Hydra = ioremap(r.start, r.end-r.start);
144         printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
145         printk("Hydra Feature_Control was %x",
146                in_le32(&Hydra->Feature_Control));
147         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
148                                            HYDRA_FC_SCSI_CELL_EN |
149                                            HYDRA_FC_SCCA_ENABLE |
150                                            HYDRA_FC_SCCB_ENABLE |
151                                            HYDRA_FC_ARB_BYPASS |
152                                            HYDRA_FC_MPIC_ENABLE |
153                                            HYDRA_FC_SLOW_SCC_PCLK |
154                                            HYDRA_FC_MPIC_IS_MASTER));
155         printk(", now %x\n", in_le32(&Hydra->Feature_Control));
156         return 1;
157 }
158
159 #define PRG_CL_RESET_VALID 0x00010000
160
161 static void __init
162 setup_python(struct pci_controller *hose, struct device_node *dev)
163 {
164         u32 __iomem *reg;
165         u32 val;
166         struct resource r;
167
168         if (of_address_to_resource(dev, 0, &r)) {
169                 printk(KERN_ERR "No address for Python PCI controller\n");
170                 return;
171         }
172
173         /* Clear the magic go-slow bit */
174         reg = ioremap(r.start + 0xf6000, 0x40);
175         BUG_ON(!reg); 
176         val = in_be32(&reg[12]);
177         if (val & PRG_CL_RESET_VALID) {
178                 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
179                 in_be32(&reg[12]);
180         }
181         iounmap(reg);
182
183         setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
184 }
185
186 /* Marvell Discovery II based Pegasos 2 */
187 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
188 {
189         struct device_node *root = find_path_device("/");
190         struct device_node *rtas;
191
192         of_node_get(root);
193         rtas = of_find_node_by_name (root, "rtas");
194         if (rtas) {
195                 hose->ops = &rtas_pci_ops;
196                 of_node_put(rtas);
197         } else {
198                 printk ("RTAS supporting Pegasos OF not found, please upgrade"
199                         " your firmware\n");
200         }
201         pci_assign_all_buses = 1;
202 }
203
204 void __init
205 chrp_find_bridges(void)
206 {
207         struct device_node *dev;
208         const int *bus_range;
209         int len, index = -1;
210         struct pci_controller *hose;
211         const unsigned int *dma;
212         const char *model, *machine;
213         int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
214         struct device_node *root = find_path_device("/");
215         struct resource r;
216         /*
217          * The PCI host bridge nodes on some machines don't have
218          * properties to adequately identify them, so we have to
219          * look at what sort of machine this is as well.
220          */
221         machine = get_property(root, "model", NULL);
222         if (machine != NULL) {
223                 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
224                 is_mot = strncmp(machine, "MOT", 3) == 0;
225                 if (strncmp(machine, "Pegasos2", 8) == 0)
226                         is_pegasos = 2;
227                 else if (strncmp(machine, "Pegasos", 7) == 0)
228                         is_pegasos = 1;
229         }
230         for (dev = root->child; dev != NULL; dev = dev->sibling) {
231                 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
232                         continue;
233                 ++index;
234                 /* The GG2 bridge on the LongTrail doesn't have an address */
235                 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
236                         printk(KERN_WARNING "Can't use %s: no address\n",
237                                dev->full_name);
238                         continue;
239                 }
240                 bus_range = get_property(dev, "bus-range", &len);
241                 if (bus_range == NULL || len < 2 * sizeof(int)) {
242                         printk(KERN_WARNING "Can't get bus-range for %s\n",
243                                 dev->full_name);
244                         continue;
245                 }
246                 if (bus_range[1] == bus_range[0])
247                         printk(KERN_INFO "PCI bus %d", bus_range[0]);
248                 else
249                         printk(KERN_INFO "PCI buses %d..%d",
250                                bus_range[0], bus_range[1]);
251                 printk(" controlled by %s", dev->full_name);
252                 if (!is_longtrail)
253                         printk(" at %llx", (unsigned long long)r.start);
254                 printk("\n");
255
256                 hose = pcibios_alloc_controller();
257                 if (!hose) {
258                         printk("Can't allocate PCI controller structure for %s\n",
259                                 dev->full_name);
260                         continue;
261                 }
262                 hose->arch_data = dev;
263                 hose->first_busno = bus_range[0];
264                 hose->last_busno = bus_range[1];
265
266                 model = get_property(dev, "model", NULL);
267                 if (model == NULL)
268                         model = "<none>";
269                 if (device_is_compatible(dev, "IBM,python")) {
270                         setup_python(hose, dev);
271                 } else if (is_mot
272                            || strncmp(model, "Motorola, Grackle", 17) == 0) {
273                         setup_grackle(hose);
274                 } else if (is_longtrail) {
275                         void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
276                         hose->ops = &gg2_pci_ops;
277                         hose->cfg_data = p;
278                         gg2_pci_config_base = p;
279                 } else if (is_pegasos == 1) {
280                         setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
281                 } else if (is_pegasos == 2) {
282                         setup_peg2(hose, dev);
283                 } else if (!strncmp(model, "IBM,CPC710", 10)) {
284                         setup_indirect_pci(hose,
285                                            r.start + 0x000f8000,
286                                            r.start + 0x000f8010);
287                         if (index == 0) {
288                                 dma = get_property(dev, "system-dma-base",&len);
289                                 if (dma && len >= sizeof(*dma)) {
290                                         dma = (unsigned int *)
291                                                 (((unsigned long)dma) +
292                                                 len - sizeof(*dma));
293                                                 pci_dram_offset = *dma;
294                                 }
295                         }
296                 } else {
297                         printk("No methods for %s (model %s), using RTAS\n",
298                                dev->full_name, model);
299                         hose->ops = &rtas_pci_ops;
300                 }
301
302                 pci_process_bridge_OF_ranges(hose, dev, index == 0);
303
304                 /* check the first bridge for a property that we can
305                    use to set pci_dram_offset */
306                 dma = get_property(dev, "ibm,dma-ranges", &len);
307                 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
308                         pci_dram_offset = dma[2] - dma[3];
309                         printk("pci_dram_offset = %lx\n", pci_dram_offset);
310                 }
311         }
312 }
313
314 /* SL82C105 IDE Control/Status Register */
315 #define SL82C105_IDECSR                0x40
316
317 /* Fixup for Winbond ATA quirk, required for briq */
318 void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
319 {
320         u8 progif;
321
322         /* If non-briq machines need that fixup too, please speak up */
323         if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
324                 return;
325
326         if ((sl82c105->class & 5) != 5) {
327                 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
328                 /* Enable SL82C105 PCI native IDE mode */
329                 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
330                 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
331                 sl82c105->class |= 0x05;
332                 /* Disable SL82C105 second port */
333                 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
334         }
335 }
336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
337                 chrp_pci_fixup_winbond_ata);