ae62f5d5c31b7e85db6987f4c3a97fd542048583
[linux-2.6.git] / arch / powerpc / platforms / cell / interrupt.c
1 /*
2  * Cell Internal Interrupt Controller
3  *
4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5  *
6  * Author: Arnd Bergmann <arndb@de.ibm.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #include <linux/config.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
27 #include <linux/percpu.h>
28 #include <linux/types.h>
29
30 #include <asm/io.h>
31 #include <asm/pgtable.h>
32 #include <asm/prom.h>
33 #include <asm/ptrace.h>
34
35 #include "interrupt.h"
36
37 struct iic_pending_bits {
38         u32 data;
39         u8 flags;
40         u8 class;
41         u8 source;
42         u8 prio;
43 };
44
45 enum iic_pending_flags {
46         IIC_VALID = 0x80,
47         IIC_IPI   = 0x40,
48 };
49
50 struct iic_regs {
51         struct iic_pending_bits pending;
52         struct iic_pending_bits pending_destr;
53         u64 generate;
54         u64 prio;
55 };
56
57 struct iic {
58         struct iic_regs __iomem *regs;
59         u8 target_id;
60 };
61
62 static DEFINE_PER_CPU(struct iic, iic);
63
64 void iic_local_enable(void)
65 {
66         struct iic *iic = &__get_cpu_var(iic);
67         u64 tmp;
68
69         /*
70          * There seems to be a bug that is present in DD2.x CPUs
71          * and still only partially fixed in DD3.1.
72          * This bug causes a value written to the priority register
73          * not to make it there, resulting in a system hang unless we
74          * write it again.
75          * Masking with 0xf0 is done because the Cell BE does not
76          * implement the lower four bits of the interrupt priority,
77          * they always read back as zeroes, although future CPUs
78          * might implement different bits.
79          */
80         do {
81                 out_be64(&iic->regs->prio, 0xff);
82                 tmp = in_be64(&iic->regs->prio);
83         } while ((tmp & 0xf0) != 0xf0);
84 }
85
86 void iic_local_disable(void)
87 {
88         out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
89 }
90
91 static unsigned int iic_startup(unsigned int irq)
92 {
93         return 0;
94 }
95
96 static void iic_enable(unsigned int irq)
97 {
98         iic_local_enable();
99 }
100
101 static void iic_disable(unsigned int irq)
102 {
103 }
104
105 static void iic_end(unsigned int irq)
106 {
107         iic_local_enable();
108 }
109
110 static struct hw_interrupt_type iic_pic = {
111         .typename = " CELL-IIC ",
112         .startup = iic_startup,
113         .enable = iic_enable,
114         .disable = iic_disable,
115         .end = iic_end,
116 };
117
118 static int iic_external_get_irq(struct iic_pending_bits pending)
119 {
120         int irq;
121         unsigned char node, unit;
122
123         node = pending.source >> 4;
124         unit = pending.source & 0xf;
125         irq = -1;
126
127         /*
128          * This mapping is specific to the Cell Broadband
129          * Engine. We might need to get the numbers
130          * from the device tree to support future CPUs.
131          */
132         switch (unit) {
133         case 0x00:
134         case 0x0b:
135                 /*
136                  * One of these units can be connected
137                  * to an external interrupt controller.
138                  */
139                 if (pending.prio > 0x3f ||
140                     pending.class != 2)
141                         break;
142                 irq = IIC_EXT_OFFSET
143                         + spider_get_irq(node)
144                         + node * IIC_NODE_STRIDE;
145                 break;
146         case 0x01 ... 0x04:
147         case 0x07 ... 0x0a:
148                 /*
149                  * These units are connected to the SPEs
150                  */
151                 if (pending.class > 2)
152                         break;
153                 irq = IIC_SPE_OFFSET
154                         + pending.class * IIC_CLASS_STRIDE
155                         + node * IIC_NODE_STRIDE
156                         + unit;
157                 break;
158         }
159         if (irq == -1)
160                 printk(KERN_WARNING "Unexpected interrupt class %02x, "
161                         "source %02x, prio %02x, cpu %02x\n", pending.class,
162                         pending.source, pending.prio, smp_processor_id());
163         return irq;
164 }
165
166 /* Get an IRQ number from the pending state register of the IIC */
167 int iic_get_irq(struct pt_regs *regs)
168 {
169         struct iic *iic;
170         int irq;
171         struct iic_pending_bits pending;
172
173         iic = &__get_cpu_var(iic);
174         *(unsigned long *) &pending = 
175                 in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
176
177         irq = -1;
178         if (pending.flags & IIC_VALID) {
179                 if (pending.flags & IIC_IPI) {
180                         irq = IIC_IPI_OFFSET + (pending.prio >> 4);
181 /*
182                         if (irq > 0x80)
183                                 printk(KERN_WARNING "Unexpected IPI prio %02x"
184                                         "on CPU %02x\n", pending.prio,
185                                                         smp_processor_id());
186 */
187                 } else {
188                         irq = iic_external_get_irq(pending);
189                 }
190         }
191         return irq;
192 }
193
194 /* hardcoded part to be compatible with older firmware */
195
196 static int setup_iic_hardcoded(void)
197 {
198         struct device_node *np;
199         int nodeid, cpu;
200         unsigned long regs;
201         struct iic *iic;
202
203         for_each_cpu(cpu) {
204                 iic = &per_cpu(iic, cpu);
205                 nodeid = cpu/2;
206
207                 for (np = of_find_node_by_type(NULL, "cpu");
208                      np;
209                      np = of_find_node_by_type(np, "cpu")) {
210                         if (nodeid == *(int *)get_property(np, "node-id", NULL))
211                                 break;
212                         }
213
214                 if (!np) {
215                         printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
216                         iic->regs = NULL;
217                         iic->target_id = 0xff;
218                         return -ENODEV;
219                         }
220
221                 regs = *(long *)get_property(np, "iic", NULL);
222
223                 /* hack until we have decided on the devtree info */
224                 regs += 0x400;
225                 if (cpu & 1)
226                         regs += 0x20;
227
228                 printk(KERN_INFO "IIC for CPU %d at %lx\n", cpu, regs);
229                 iic->regs = ioremap(regs, sizeof(struct iic_regs));
230                 iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
231         }
232
233         return 0;
234 }
235
236 static int setup_iic(void)
237 {
238         struct device_node *dn;
239         unsigned long *regs;
240         char *compatible;
241         unsigned *np, found = 0;
242         struct iic *iic = NULL;
243
244         for (dn = NULL; (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
245                 compatible = (char *)get_property(dn, "compatible", NULL);
246
247                 if (!compatible) {
248                         printk(KERN_WARNING "no compatible property found !\n");
249                         continue;
250                 }
251
252                 if (strstr(compatible, "IBM,CBEA-Internal-Interrupt-Controller"))
253                         regs = (unsigned long *)get_property(dn,"reg", NULL);
254                 else
255                         continue;
256
257                 if (!regs)
258                         printk(KERN_WARNING "IIC: no reg property\n");
259
260                 np = (unsigned int *)get_property(dn, "ibm,interrupt-server-ranges", NULL);
261
262                 if (!np) {
263                         printk(KERN_WARNING "IIC: CPU association not found\n");
264                         iic->regs = NULL;
265                         iic->target_id = 0xff;
266                         return -ENODEV;
267                 }
268
269                 iic = &per_cpu(iic, np[0]);
270                 iic->regs = ioremap(regs[0], sizeof(struct iic_regs));
271                 iic->target_id = ((np[0] & 2) << 3) + ((np[0] & 1) ? 0xf : 0xe);
272                 printk("IIC for CPU %d at %lx mapped to %p\n", np[0], regs[0], iic->regs);
273
274                 iic = &per_cpu(iic, np[1]);
275                 iic->regs = ioremap(regs[2], sizeof(struct iic_regs));
276                 iic->target_id = ((np[1] & 2) << 3) + ((np[1] & 1) ? 0xf : 0xe);
277                 printk("IIC for CPU %d at %lx mapped to %p\n", np[1], regs[2], iic->regs);
278
279                 found++;
280         }
281
282         if (found)
283                 return 0;
284         else
285                 return -ENODEV;
286 }
287
288 #ifdef CONFIG_SMP
289
290 /* Use the highest interrupt priorities for IPI */
291 static inline int iic_ipi_to_irq(int ipi)
292 {
293         return IIC_IPI_OFFSET + IIC_NUM_IPIS - 1 - ipi;
294 }
295
296 static inline int iic_irq_to_ipi(int irq)
297 {
298         return IIC_NUM_IPIS - 1 - (irq - IIC_IPI_OFFSET);
299 }
300
301 void iic_setup_cpu(void)
302 {
303         out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
304 }
305
306 void iic_cause_IPI(int cpu, int mesg)
307 {
308         out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
309 }
310
311 u8 iic_get_target_id(int cpu)
312 {
313         return per_cpu(iic, cpu).target_id;
314 }
315 EXPORT_SYMBOL_GPL(iic_get_target_id);
316
317 static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
318 {
319         smp_message_recv(iic_irq_to_ipi(irq), regs);
320         return IRQ_HANDLED;
321 }
322
323 static void iic_request_ipi(int ipi, const char *name)
324 {
325         int irq;
326
327         irq = iic_ipi_to_irq(ipi);
328         /* IPIs are marked SA_INTERRUPT as they must run with irqs
329          * disabled */
330         get_irq_desc(irq)->handler = &iic_pic;
331         get_irq_desc(irq)->status |= IRQ_PER_CPU;
332         request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL);
333 }
334
335 void iic_request_IPIs(void)
336 {
337         iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
338         iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
339 #ifdef CONFIG_DEBUGGER
340         iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
341 #endif /* CONFIG_DEBUGGER */
342 }
343 #endif /* CONFIG_SMP */
344
345 static void iic_setup_spe_handlers(void)
346 {
347         int be, isrc;
348
349         /* Assume two threads per BE are present */
350         for (be=0; be < num_present_cpus() / 2; be++) {
351                 for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
352                         int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
353                         get_irq_desc(irq)->handler = &iic_pic;
354                 }
355         }
356 }
357
358 void iic_init_IRQ(void)
359 {
360         int cpu, irq_offset;
361         struct iic *iic;
362
363         if (setup_iic() < 0)
364                 setup_iic_hardcoded();
365
366         irq_offset = 0;
367         for_each_cpu(cpu) {
368                 iic = &per_cpu(iic, cpu);
369                 if (iic->regs)
370                         out_be64(&iic->regs->prio, 0xff);
371         }
372         iic_setup_spe_handlers();
373 }