[PATCH] Add mm->task_size and fix powerpc vdso
[linux-2.6.git] / arch / powerpc / oprofile / op_model_fsl_booke.c
1 /*
2  * oprofile/op_model_e500.c
3  *
4  * Freescale Book-E oprofile support, based on ppc64 oprofile support
5  * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
6  *
7  * Copyright (c) 2004 Freescale Semiconductor, Inc
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License
14  * as published by the Free Software Foundation; either version
15  * 2 of the License, or (at your option) any later version.
16  */
17
18 #include <linux/oprofile.h>
19 #include <linux/init.h>
20 #include <linux/smp.h>
21 #include <asm/ptrace.h>
22 #include <asm/system.h>
23 #include <asm/processor.h>
24 #include <asm/cputable.h>
25 #include <asm/reg_booke.h>
26 #include <asm/page.h>
27 #include <asm/pmc.h>
28 #include <asm/oprofile_impl.h>
29
30 static unsigned long reset_value[OP_MAX_COUNTER];
31
32 static int num_counters;
33 static int oprofile_running;
34
35 static inline unsigned int ctr_read(unsigned int i)
36 {
37         switch(i) {
38                 case 0:
39                         return mfpmr(PMRN_PMC0);
40                 case 1:
41                         return mfpmr(PMRN_PMC1);
42                 case 2:
43                         return mfpmr(PMRN_PMC2);
44                 case 3:
45                         return mfpmr(PMRN_PMC3);
46                 default:
47                         return 0;
48         }
49 }
50
51 static inline void ctr_write(unsigned int i, unsigned int val)
52 {
53         switch(i) {
54                 case 0:
55                         mtpmr(PMRN_PMC0, val);
56                         break;
57                 case 1:
58                         mtpmr(PMRN_PMC1, val);
59                         break;
60                 case 2:
61                         mtpmr(PMRN_PMC2, val);
62                         break;
63                 case 3:
64                         mtpmr(PMRN_PMC3, val);
65                         break;
66                 default:
67                         break;
68         }
69 }
70
71
72 static void fsl_booke_reg_setup(struct op_counter_config *ctr,
73                              struct op_system_config *sys,
74                              int num_ctrs)
75 {
76         int i;
77
78         num_counters = num_ctrs;
79
80         /* freeze all counters */
81         pmc_stop_ctrs();
82
83         /* Our counters count up, and "count" refers to
84          * how much before the next interrupt, and we interrupt
85          * on overflow.  So we calculate the starting value
86          * which will give us "count" until overflow.
87          * Then we set the events on the enabled counters */
88         for (i = 0; i < num_counters; ++i) {
89                 reset_value[i] = 0x80000000UL - ctr[i].count;
90
91                 init_pmc_stop(i);
92
93                 set_pmc_event(i, ctr[i].event);
94
95                 set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
96         }
97 }
98
99 static void fsl_booke_start(struct op_counter_config *ctr)
100 {
101         int i;
102
103         mtmsr(mfmsr() | MSR_PMM);
104
105         for (i = 0; i < num_counters; ++i) {
106                 if (ctr[i].enabled) {
107                         ctr_write(i, reset_value[i]);
108                         /* Set Each enabled counterd to only
109                          * count when the Mark bit is not set */
110                         set_pmc_marked(i, 1, 0);
111                         pmc_start_ctr(i, 1);
112                 } else {
113                         ctr_write(i, 0);
114
115                         /* Set the ctr to be stopped */
116                         pmc_start_ctr(i, 0);
117                 }
118         }
119
120         /* Clear the freeze bit, and enable the interrupt.
121          * The counters won't actually start until the rfi clears
122          * the PMM bit */
123         pmc_start_ctrs(1);
124
125         oprofile_running = 1;
126
127         pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
128                         mfpmr(PMRN_PMGC0));
129 }
130
131 static void fsl_booke_stop(void)
132 {
133         /* freeze counters */
134         pmc_stop_ctrs();
135
136         oprofile_running = 0;
137
138         pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
139                         mfpmr(PMRN_PMGC0));
140
141         mb();
142 }
143
144
145 static void fsl_booke_handle_interrupt(struct pt_regs *regs,
146                                     struct op_counter_config *ctr)
147 {
148         unsigned long pc;
149         int is_kernel;
150         int val;
151         int i;
152
153         /* set the PMM bit (see comment below) */
154         mtmsr(mfmsr() | MSR_PMM);
155
156         pc = regs->nip;
157         is_kernel = (pc >= KERNELBASE);
158
159         for (i = 0; i < num_counters; ++i) {
160                 val = ctr_read(i);
161                 if (val < 0) {
162                         if (oprofile_running && ctr[i].enabled) {
163                                 oprofile_add_pc(pc, is_kernel, i);
164                                 ctr_write(i, reset_value[i]);
165                         } else {
166                                 ctr_write(i, 0);
167                         }
168                 }
169         }
170
171         /* The freeze bit was set by the interrupt. */
172         /* Clear the freeze bit, and reenable the interrupt.
173          * The counters won't actually start until the rfi clears
174          * the PMM bit */
175         pmc_start_ctrs(1);
176 }
177
178 struct op_powerpc_model op_model_fsl_booke = {
179         .reg_setup              = fsl_booke_reg_setup,
180         .start                  = fsl_booke_start,
181         .stop                   = fsl_booke_stop,
182         .handle_interrupt       = fsl_booke_handle_interrupt,
183 };