Add support for BCM1480 family of chips.
[linux-2.6.git] / arch / mips / sibyte / bcm1480 / irq.c
1 /*
2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/linkage.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/kernel_stat.h>
27
28 #include <asm/errno.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/ptrace.h>
32 #include <asm/io.h>
33
34 #include <asm/sibyte/bcm1480_regs.h>
35 #include <asm/sibyte/bcm1480_int.h>
36 #include <asm/sibyte/bcm1480_scd.h>
37
38 #include <asm/sibyte/sb1250_uart.h>
39 #include <asm/sibyte/sb1250.h>
40
41 /*
42  * These are the routines that handle all the low level interrupt stuff.
43  * Actions handled here are: initialization of the interrupt map, requesting of
44  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
45  * for interrupt lines
46  */
47
48
49 #define shutdown_bcm1480_irq    disable_bcm1480_irq
50 static void end_bcm1480_irq(unsigned int irq);
51 static void enable_bcm1480_irq(unsigned int irq);
52 static void disable_bcm1480_irq(unsigned int irq);
53 static unsigned int startup_bcm1480_irq(unsigned int irq);
54 static void ack_bcm1480_irq(unsigned int irq);
55 #ifdef CONFIG_SMP
56 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
57 #endif
58
59 #ifdef CONFIG_PCI
60 extern unsigned long ht_eoi_space;
61 #endif
62
63 #ifdef CONFIG_KGDB
64 #include <asm/gdb-stub.h>
65 extern void breakpoint(void);
66 static int kgdb_irq;
67 #ifdef CONFIG_GDB_CONSOLE
68 extern void register_gdb_console(void);
69 #endif
70
71 /* kgdb is on when configured.  Pass "nokgdb" kernel arg to turn it off */
72 static int kgdb_flag = 1;
73 static int __init nokgdb(char *str)
74 {
75         kgdb_flag = 0;
76         return 1;
77 }
78 __setup("nokgdb", nokgdb);
79
80 /* Default to UART1 */
81 int kgdb_port = 1;
82 #ifdef CONFIG_SIBYTE_SB1250_DUART
83 extern char sb1250_duart_present[];
84 #endif
85 #endif
86
87 static struct hw_interrupt_type bcm1480_irq_type = {
88         .typename = "BCM1480-IMR",
89         .startup = startup_bcm1480_irq,
90         .shutdown = shutdown_bcm1480_irq,
91         .enable = enable_bcm1480_irq,
92         .disable = disable_bcm1480_irq,
93         .ack = ack_bcm1480_irq,
94         .end = end_bcm1480_irq,
95 #ifdef CONFIG_SMP
96         .set_affinity = bcm1480_set_affinity
97 #endif
98 };
99
100 /* Store the CPU id (not the logical number) */
101 int bcm1480_irq_owner[BCM1480_NR_IRQS];
102
103 DEFINE_SPINLOCK(bcm1480_imr_lock);
104
105 void bcm1480_mask_irq(int cpu, int irq)
106 {
107         unsigned long flags;
108         u64 cur_ints,hl_spacing;
109
110         spin_lock_irqsave(&bcm1480_imr_lock, flags);
111         hl_spacing = 0;
112         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
113                 hl_spacing = BCM1480_IMR_HL_SPACING;
114                 irq -= BCM1480_NR_IRQS_HALF;
115         }
116         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
117         cur_ints |= (((u64) 1) << irq);
118         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
119         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
120 }
121
122 void bcm1480_unmask_irq(int cpu, int irq)
123 {
124         unsigned long flags;
125         u64 cur_ints,hl_spacing;
126
127         spin_lock_irqsave(&bcm1480_imr_lock, flags);
128         hl_spacing = 0;
129         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
130                 hl_spacing = BCM1480_IMR_HL_SPACING;
131                 irq -= BCM1480_NR_IRQS_HALF;
132         }
133         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
134         cur_ints &= ~(((u64) 1) << irq);
135         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
136         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
137 }
138
139 #ifdef CONFIG_SMP
140 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
141 {
142         int i = 0, old_cpu, cpu, int_on;
143         u64 cur_ints;
144         irq_desc_t *desc = irq_desc + irq;
145         unsigned long flags;
146         unsigned int irq_dirty;
147
148         i = first_cpu(mask);
149         if (next_cpu(i, mask) <= NR_CPUS) {
150                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
151                 return;
152         }
153
154         /* Convert logical CPU to physical CPU */
155         cpu = cpu_logical_map(i);
156
157         /* Protect against other affinity changers and IMR manipulation */
158         spin_lock_irqsave(&desc->lock, flags);
159         spin_lock(&bcm1480_imr_lock);
160
161         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
162         old_cpu = bcm1480_irq_owner[irq];
163         irq_dirty = irq;
164         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
165                 irq_dirty -= BCM1480_NR_IRQS_HALF;
166         }
167
168         int k;
169         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
170                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
171                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
172                 if (int_on) {
173                         /* If it was on, mask it */
174                         cur_ints |= (((u64) 1) << irq_dirty);
175                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
176                 }
177                 bcm1480_irq_owner[irq] = cpu;
178                 if (int_on) {
179                         /* unmask for the new CPU */
180                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
181                         cur_ints &= ~(((u64) 1) << irq_dirty);
182                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
183                 }
184         }
185         spin_unlock(&bcm1480_imr_lock);
186         spin_unlock_irqrestore(&desc->lock, flags);
187 }
188 #endif
189
190
191 /* Defined in arch/mips/sibyte/bcm1480/irq_handler.S */
192 extern void bcm1480_irq_handler(void);
193
194 /*****************************************************************************/
195
196 static unsigned int startup_bcm1480_irq(unsigned int irq)
197 {
198         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
199
200         return 0;               /* never anything pending */
201 }
202
203
204 static void disable_bcm1480_irq(unsigned int irq)
205 {
206         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
207 }
208
209 static void enable_bcm1480_irq(unsigned int irq)
210 {
211         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
212 }
213
214
215 static void ack_bcm1480_irq(unsigned int irq)
216 {
217         u64 pending;
218         unsigned int irq_dirty;
219
220         /*
221          * If the interrupt was an HT interrupt, now is the time to
222          * clear it.  NOTE: we assume the HT bridge was set up to
223          * deliver the interrupts to all CPUs (which makes affinity
224          * changing easier for us)
225          */
226         irq_dirty = irq;
227         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
228                 irq_dirty -= BCM1480_NR_IRQS_HALF;
229         }
230         int k;
231         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
232                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
233                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
234                 pending &= ((u64)1 << (irq_dirty));
235                 if (pending) {
236 #ifdef CONFIG_SMP
237                         int i;
238                         for (i=0; i<NR_CPUS; i++) {
239                                 /*
240                                  * Clear for all CPUs so an affinity switch
241                                  * doesn't find an old status
242                                  */
243                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
244                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
245                         }
246 #else
247                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
248 #endif
249
250                         /*
251                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
252                          * Pass 2, the LDT world may be edge-triggered, but
253                          * this EOI shouldn't hurt.  If they are
254                          * level-sensitive, the EOI is required.
255                          */
256 #ifdef CONFIG_PCI
257                         if (ht_eoi_space)
258                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
259 #endif
260                 }
261         }
262         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
263 }
264
265
266 static void end_bcm1480_irq(unsigned int irq)
267 {
268         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
269                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
270         }
271 }
272
273
274 void __init init_bcm1480_irqs(void)
275 {
276         int i;
277
278         for (i = 0; i < NR_IRQS; i++) {
279                 irq_desc[i].status = IRQ_DISABLED;
280                 irq_desc[i].action = 0;
281                 irq_desc[i].depth = 1;
282                 if (i < BCM1480_NR_IRQS) {
283                         irq_desc[i].handler = &bcm1480_irq_type;
284                         bcm1480_irq_owner[i] = 0;
285                 } else {
286                         irq_desc[i].handler = &no_irq_type;
287                 }
288         }
289 }
290
291
292 static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id,
293         struct pt_regs *regs)
294 {
295         return IRQ_NONE;
296 }
297
298 static struct irqaction bcm1480_dummy_action = {
299         .handler = bcm1480_dummy_handler,
300         .flags   = 0,
301         .mask    = CPU_MASK_NONE,
302         .name    = "bcm1480-private",
303         .next    = NULL,
304         .dev_id  = 0
305 };
306
307 int bcm1480_steal_irq(int irq)
308 {
309         irq_desc_t *desc = irq_desc + irq;
310         unsigned long flags;
311         int retval = 0;
312
313         if (irq >= BCM1480_NR_IRQS)
314                 return -EINVAL;
315
316         spin_lock_irqsave(&desc->lock,flags);
317         /* Don't allow sharing at all for these */
318         if (desc->action != NULL)
319                 retval = -EBUSY;
320         else {
321                 desc->action = &bcm1480_dummy_action;
322                 desc->depth = 0;
323         }
324         spin_unlock_irqrestore(&desc->lock,flags);
325         return 0;
326 }
327
328 /*
329  *  init_IRQ is called early in the boot sequence from init/main.c.  It
330  *  is responsible for setting up the interrupt mapper and installing the
331  *  handler that will be responsible for dispatching interrupts to the
332  *  "right" place.
333  */
334 /*
335  * For now, map all interrupts to IP[2].  We could save
336  * some cycles by parceling out system interrupts to different
337  * IP lines, but keep it simple for bringup.  We'll also direct
338  * all interrupts to a single CPU; we should probably route
339  * PCI and LDT to one cpu and everything else to the other
340  * to balance the load a bit.
341  *
342  * On the second cpu, everything is set to IP5, which is
343  * ignored, EXCEPT the mailbox interrupt.  That one is
344  * set to IP[2] so it is handled.  This is needed so we
345  * can do cross-cpu function calls, as requred by SMP
346  */
347
348 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
349 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
350 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
351 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
352 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
353
354 void __init arch_init_irq(void)
355 {
356
357         unsigned int i, cpu;
358         u64 tmp;
359         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
360                 STATUSF_IP1 | STATUSF_IP0;
361
362         /* Default everything to IP2 */
363         /* Start with _high registers which has no bit 0 interrupt source */
364         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
365                 for (cpu = 0; cpu < 4; cpu++) {
366                         __raw_writeq(IMR_IP2_VAL,
367                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
368                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
369                 }
370         }
371
372         /* Now do _low registers */
373         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
374                 for (cpu = 0; cpu < 4; cpu++) {
375                         __raw_writeq(IMR_IP2_VAL,
376                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
377                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
378                 }
379         }
380
381         init_bcm1480_irqs();
382
383         /*
384          * Map the high 16 bits of mailbox_0 registers to IP[3], for
385          * inter-cpu messages
386          */
387         /* Was I1 */
388         for (cpu = 0; cpu < 4; cpu++) {
389                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
390                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
391         }
392
393
394         /* Clear the mailboxes.  The firmware may leave them dirty */
395         for (cpu = 0; cpu < 4; cpu++) {
396                 __raw_writeq(0xffffffffffffffffULL,
397                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
398                 __raw_writeq(0xffffffffffffffffULL,
399                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
400         }
401
402
403         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
404         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
405         for (cpu = 0; cpu < 4; cpu++) {
406                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
407         }
408         tmp = ~((u64) 0);
409         for (cpu = 0; cpu < 4; cpu++) {
410                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
411         }
412
413         bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
414
415         /*
416          * Note that the timer interrupts are also mapped, but this is
417          * done in bcm1480_time_init().  Also, the profiling driver
418          * does its own management of IP7.
419          */
420
421 #ifdef CONFIG_KGDB
422         imask |= STATUSF_IP6;
423 #endif
424         /* Enable necessary IPs, disable the rest */
425         change_c0_status(ST0_IM, imask);
426         set_except_vector(0, bcm1480_irq_handler);
427
428 #ifdef CONFIG_KGDB
429         if (kgdb_flag) {
430                 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
431
432 #ifdef CONFIG_SIBYTE_SB1250_DUART
433                 sb1250_duart_present[kgdb_port] = 0;
434 #endif
435                 /* Setup uart 1 settings, mapper */
436                 /* QQQ FIXME */
437                 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
438
439                 bcm1480_steal_irq(kgdb_irq);
440                 __raw_writeq(IMR_IP6_VAL,
441                              IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
442                              (kgdb_irq<<3));
443                 bcm1480_unmask_irq(0, kgdb_irq);
444
445 #ifdef CONFIG_GDB_CONSOLE
446                 register_gdb_console();
447 #endif
448                 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
449                 set_debug_traps();
450                 breakpoint();
451         }
452 #endif
453 }
454
455 #ifdef CONFIG_KGDB
456
457 #include <linux/delay.h>
458
459 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
460 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
461
462 void bcm1480_kgdb_interrupt(struct pt_regs *regs)
463 {
464         /*
465          * Clear break-change status (allow some time for the remote
466          * host to stop the break, since we would see another
467          * interrupt on the end-of-break too)
468          */
469         kstat.irqs[smp_processor_id()][kgdb_irq]++;
470         mdelay(500);
471         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
472                                 M_DUART_RX_EN | M_DUART_TX_EN);
473         set_async_breakpoint(&regs->cp0_epc);
474 }
475
476 #endif  /* CONFIG_KGDB */