[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
[linux-2.6.git] / arch / mips / sibyte / bcm1480 / irq.c
1 /*
2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/mm.h>
24 #include <linux/slab.h>
25 #include <linux/kernel_stat.h>
26
27 #include <asm/errno.h>
28 #include <asm/irq_regs.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/io.h>
32
33 #include <asm/sibyte/bcm1480_regs.h>
34 #include <asm/sibyte/bcm1480_int.h>
35 #include <asm/sibyte/bcm1480_scd.h>
36
37 #include <asm/sibyte/sb1250_uart.h>
38 #include <asm/sibyte/sb1250.h>
39
40 /*
41  * These are the routines that handle all the low level interrupt stuff.
42  * Actions handled here are: initialization of the interrupt map, requesting of
43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
44  * for interrupt lines
45  */
46
47
48 static void end_bcm1480_irq(unsigned int irq);
49 static void enable_bcm1480_irq(unsigned int irq);
50 static void disable_bcm1480_irq(unsigned int irq);
51 static void ack_bcm1480_irq(unsigned int irq);
52 #ifdef CONFIG_SMP
53 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
54 #endif
55
56 #ifdef CONFIG_PCI
57 extern unsigned long ht_eoi_space;
58 #endif
59
60 #ifdef CONFIG_KGDB
61 #include <asm/gdb-stub.h>
62 extern void breakpoint(void);
63 static int kgdb_irq;
64 #ifdef CONFIG_GDB_CONSOLE
65 extern void register_gdb_console(void);
66 #endif
67
68 /* kgdb is on when configured.  Pass "nokgdb" kernel arg to turn it off */
69 static int kgdb_flag = 1;
70 static int __init nokgdb(char *str)
71 {
72         kgdb_flag = 0;
73         return 1;
74 }
75 __setup("nokgdb", nokgdb);
76
77 /* Default to UART1 */
78 int kgdb_port = 1;
79 #ifdef CONFIG_SERIAL_SB1250_DUART
80 extern char sb1250_duart_present[];
81 #endif
82 #endif
83
84 static struct irq_chip bcm1480_irq_type = {
85         .name = "BCM1480-IMR",
86         .ack = ack_bcm1480_irq,
87         .mask = disable_bcm1480_irq,
88         .mask_ack = ack_bcm1480_irq,
89         .unmask = enable_bcm1480_irq,
90         .end = end_bcm1480_irq,
91 #ifdef CONFIG_SMP
92         .set_affinity = bcm1480_set_affinity
93 #endif
94 };
95
96 /* Store the CPU id (not the logical number) */
97 int bcm1480_irq_owner[BCM1480_NR_IRQS];
98
99 DEFINE_SPINLOCK(bcm1480_imr_lock);
100
101 void bcm1480_mask_irq(int cpu, int irq)
102 {
103         unsigned long flags, hl_spacing;
104         u64 cur_ints;
105
106         spin_lock_irqsave(&bcm1480_imr_lock, flags);
107         hl_spacing = 0;
108         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
109                 hl_spacing = BCM1480_IMR_HL_SPACING;
110                 irq -= BCM1480_NR_IRQS_HALF;
111         }
112         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
113         cur_ints |= (((u64) 1) << irq);
114         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
115         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
116 }
117
118 void bcm1480_unmask_irq(int cpu, int irq)
119 {
120         unsigned long flags, hl_spacing;
121         u64 cur_ints;
122
123         spin_lock_irqsave(&bcm1480_imr_lock, flags);
124         hl_spacing = 0;
125         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
126                 hl_spacing = BCM1480_IMR_HL_SPACING;
127                 irq -= BCM1480_NR_IRQS_HALF;
128         }
129         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
130         cur_ints &= ~(((u64) 1) << irq);
131         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
132         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
133 }
134
135 #ifdef CONFIG_SMP
136 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
137 {
138         int i = 0, old_cpu, cpu, int_on, k;
139         u64 cur_ints;
140         struct irq_desc *desc = irq_desc + irq;
141         unsigned long flags;
142         unsigned int irq_dirty;
143
144         if (cpus_weight(mask) != 1) {
145                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
146                 return;
147         }
148         i = first_cpu(mask);
149
150         /* Convert logical CPU to physical CPU */
151         cpu = cpu_logical_map(i);
152
153         /* Protect against other affinity changers and IMR manipulation */
154         spin_lock_irqsave(&desc->lock, flags);
155         spin_lock(&bcm1480_imr_lock);
156
157         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
158         old_cpu = bcm1480_irq_owner[irq];
159         irq_dirty = irq;
160         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
161                 irq_dirty -= BCM1480_NR_IRQS_HALF;
162         }
163
164         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
165                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
166                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
167                 if (int_on) {
168                         /* If it was on, mask it */
169                         cur_ints |= (((u64) 1) << irq_dirty);
170                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
171                 }
172                 bcm1480_irq_owner[irq] = cpu;
173                 if (int_on) {
174                         /* unmask for the new CPU */
175                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
176                         cur_ints &= ~(((u64) 1) << irq_dirty);
177                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
178                 }
179         }
180         spin_unlock(&bcm1480_imr_lock);
181         spin_unlock_irqrestore(&desc->lock, flags);
182 }
183 #endif
184
185
186 /*****************************************************************************/
187
188 static void disable_bcm1480_irq(unsigned int irq)
189 {
190         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
191 }
192
193 static void enable_bcm1480_irq(unsigned int irq)
194 {
195         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
196 }
197
198
199 static void ack_bcm1480_irq(unsigned int irq)
200 {
201         u64 pending;
202         unsigned int irq_dirty;
203         int k;
204
205         /*
206          * If the interrupt was an HT interrupt, now is the time to
207          * clear it.  NOTE: we assume the HT bridge was set up to
208          * deliver the interrupts to all CPUs (which makes affinity
209          * changing easier for us)
210          */
211         irq_dirty = irq;
212         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
213                 irq_dirty -= BCM1480_NR_IRQS_HALF;
214         }
215         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
216                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
217                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
218                 pending &= ((u64)1 << (irq_dirty));
219                 if (pending) {
220 #ifdef CONFIG_SMP
221                         int i;
222                         for (i=0; i<NR_CPUS; i++) {
223                                 /*
224                                  * Clear for all CPUs so an affinity switch
225                                  * doesn't find an old status
226                                  */
227                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
228                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
229                         }
230 #else
231                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
232 #endif
233
234                         /*
235                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
236                          * Pass 2, the LDT world may be edge-triggered, but
237                          * this EOI shouldn't hurt.  If they are
238                          * level-sensitive, the EOI is required.
239                          */
240 #ifdef CONFIG_PCI
241                         if (ht_eoi_space)
242                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
243 #endif
244                 }
245         }
246         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
247 }
248
249
250 static void end_bcm1480_irq(unsigned int irq)
251 {
252         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
253                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
254         }
255 }
256
257
258 void __init init_bcm1480_irqs(void)
259 {
260         int i;
261
262         for (i = 0; i < BCM1480_NR_IRQS; i++) {
263                 set_irq_chip(i, &bcm1480_irq_type);
264                 bcm1480_irq_owner[i] = 0;
265         }
266 }
267
268
269 static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id)
270 {
271         return IRQ_NONE;
272 }
273
274 static struct irqaction bcm1480_dummy_action = {
275         .handler = bcm1480_dummy_handler,
276         .flags   = 0,
277         .mask    = CPU_MASK_NONE,
278         .name    = "bcm1480-private",
279         .next    = NULL,
280         .dev_id  = 0
281 };
282
283 int bcm1480_steal_irq(int irq)
284 {
285         struct irq_desc *desc = irq_desc + irq;
286         unsigned long flags;
287         int retval = 0;
288
289         if (irq >= BCM1480_NR_IRQS)
290                 return -EINVAL;
291
292         spin_lock_irqsave(&desc->lock, flags);
293         /* Don't allow sharing at all for these */
294         if (desc->action != NULL)
295                 retval = -EBUSY;
296         else {
297                 desc->action = &bcm1480_dummy_action;
298                 desc->depth = 0;
299         }
300         spin_unlock_irqrestore(&desc->lock, flags);
301         return 0;
302 }
303
304 /*
305  *  init_IRQ is called early in the boot sequence from init/main.c.  It
306  *  is responsible for setting up the interrupt mapper and installing the
307  *  handler that will be responsible for dispatching interrupts to the
308  *  "right" place.
309  */
310 /*
311  * For now, map all interrupts to IP[2].  We could save
312  * some cycles by parceling out system interrupts to different
313  * IP lines, but keep it simple for bringup.  We'll also direct
314  * all interrupts to a single CPU; we should probably route
315  * PCI and LDT to one cpu and everything else to the other
316  * to balance the load a bit.
317  *
318  * On the second cpu, everything is set to IP5, which is
319  * ignored, EXCEPT the mailbox interrupt.  That one is
320  * set to IP[2] so it is handled.  This is needed so we
321  * can do cross-cpu function calls, as requred by SMP
322  */
323
324 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
325 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
326 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
327 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
328 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
329
330 void __init arch_init_irq(void)
331 {
332
333         unsigned int i, cpu;
334         u64 tmp;
335         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
336                 STATUSF_IP1 | STATUSF_IP0;
337
338         /* Default everything to IP2 */
339         /* Start with _high registers which has no bit 0 interrupt source */
340         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
341                 for (cpu = 0; cpu < 4; cpu++) {
342                         __raw_writeq(IMR_IP2_VAL,
343                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
344                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
345                 }
346         }
347
348         /* Now do _low registers */
349         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
350                 for (cpu = 0; cpu < 4; cpu++) {
351                         __raw_writeq(IMR_IP2_VAL,
352                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
353                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
354                 }
355         }
356
357         init_bcm1480_irqs();
358
359         /*
360          * Map the high 16 bits of mailbox_0 registers to IP[3], for
361          * inter-cpu messages
362          */
363         /* Was I1 */
364         for (cpu = 0; cpu < 4; cpu++) {
365                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
366                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
367         }
368
369
370         /* Clear the mailboxes.  The firmware may leave them dirty */
371         for (cpu = 0; cpu < 4; cpu++) {
372                 __raw_writeq(0xffffffffffffffffULL,
373                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
374                 __raw_writeq(0xffffffffffffffffULL,
375                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
376         }
377
378
379         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
380         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
381         for (cpu = 0; cpu < 4; cpu++) {
382                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
383         }
384         tmp = ~((u64) 0);
385         for (cpu = 0; cpu < 4; cpu++) {
386                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
387         }
388
389         bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
390
391         /*
392          * Note that the timer interrupts are also mapped, but this is
393          * done in bcm1480_time_init().  Also, the profiling driver
394          * does its own management of IP7.
395          */
396
397 #ifdef CONFIG_KGDB
398         imask |= STATUSF_IP6;
399 #endif
400         /* Enable necessary IPs, disable the rest */
401         change_c0_status(ST0_IM, imask);
402
403 #ifdef CONFIG_KGDB
404         if (kgdb_flag) {
405                 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
406
407 #ifdef CONFIG_SERIAL_SB1250_DUART
408                 sb1250_duart_present[kgdb_port] = 0;
409 #endif
410                 /* Setup uart 1 settings, mapper */
411                 /* QQQ FIXME */
412                 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
413
414                 bcm1480_steal_irq(kgdb_irq);
415                 __raw_writeq(IMR_IP6_VAL,
416                              IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
417                              (kgdb_irq<<3));
418                 bcm1480_unmask_irq(0, kgdb_irq);
419
420 #ifdef CONFIG_GDB_CONSOLE
421                 register_gdb_console();
422 #endif
423                 printk("Waiting for GDB on UART port %d\n", kgdb_port);
424                 set_debug_traps();
425                 breakpoint();
426         }
427 #endif
428 }
429
430 #ifdef CONFIG_KGDB
431
432 #include <linux/delay.h>
433
434 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
435 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
436
437 static void bcm1480_kgdb_interrupt(void)
438 {
439         /*
440          * Clear break-change status (allow some time for the remote
441          * host to stop the break, since we would see another
442          * interrupt on the end-of-break too)
443          */
444         kstat.irqs[smp_processor_id()][kgdb_irq]++;
445         mdelay(500);
446         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
447                                 M_DUART_RX_EN | M_DUART_TX_EN);
448         set_async_breakpoint(&get_irq_regs()->cp0_epc);
449 }
450
451 #endif  /* CONFIG_KGDB */
452
453 extern void bcm1480_mailbox_interrupt(void);
454
455 static inline void dispatch_ip4(void)
456 {
457         int cpu = smp_processor_id();
458         int irq = K_BCM1480_INT_TIMER_0 + cpu;
459
460         /* Reset the timer */
461         __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
462                     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
463
464         do_IRQ(irq);
465 }
466
467 static inline void dispatch_ip2(void)
468 {
469         unsigned long long mask_h, mask_l;
470         unsigned int cpu = smp_processor_id();
471         unsigned long base;
472
473         /*
474          * Default...we've hit an IP[2] interrupt, which means we've got to
475          * check the 1480 interrupt registers to figure out what to do.  Need
476          * to detect which CPU we're on, now that smp_affinity is supported.
477          */
478         base = A_BCM1480_IMR_MAPPER(cpu);
479         mask_h = __raw_readq(
480                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
481         mask_l = __raw_readq(
482                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
483
484         if (mask_h) {
485                 if (mask_h ^ 1)
486                         do_IRQ(fls64(mask_h) - 1);
487                 else if (mask_l)
488                         do_IRQ(63 + fls64(mask_l));
489         }
490 }
491
492 asmlinkage void plat_irq_dispatch(void)
493 {
494         unsigned int pending;
495
496 #ifdef CONFIG_SIBYTE_BCM1480_PROF
497         /* Set compare to count to silence count/compare timer interrupts */
498         write_c0_compare(read_c0_count());
499 #endif
500
501         pending = read_c0_cause() & read_c0_status();
502
503 #ifdef CONFIG_SIBYTE_BCM1480_PROF
504         if (pending & CAUSEF_IP7)       /* Cpu performance counter interrupt */
505                 sbprof_cpu_intr();
506         else
507 #endif
508
509         if (pending & CAUSEF_IP4)
510                 dispatch_ip4();
511 #ifdef CONFIG_SMP
512         else if (pending & CAUSEF_IP3)
513                 bcm1480_mailbox_interrupt();
514 #endif
515
516 #ifdef CONFIG_KGDB
517         else if (pending & CAUSEF_IP6)
518                 bcm1480_kgdb_interrupt();               /* KGDB (uart 1) */
519 #endif
520
521         else if (pending & CAUSEF_IP2)
522                 dispatch_ip2();
523 }