c54384779fb91edfa81111b8aea030e2056486eb
[linux-2.6.git] / arch / mips / alchemy / common / irq.c
1 /*
2  * Copyright 2001, 2007-2008 MontaVista Software Inc.
3  * Author: MontaVista Software, Inc. <source@mvista.com>
4  *
5  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
6  *
7  *  This program is free software; you can redistribute  it and/or modify it
8  *  under  the terms of  the GNU General  Public License as published by the
9  *  Free Software Foundation;  either version 2 of the  License, or (at your
10  *  option) any later version.
11  *
12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22  *
23  *  You should have received a copy of the  GNU General Public License along
24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
25  *  675 Mass Ave, Cambridge, MA 02139, USA.
26  */
27
28 #include <linux/bitops.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32
33 #include <asm/irq_cpu.h>
34 #include <asm/mipsregs.h>
35 #include <asm/mach-au1x00/au1000.h>
36 #ifdef CONFIG_MIPS_PB1000
37 #include <asm/mach-pb1x00/pb1000.h>
38 #endif
39
40 static DEFINE_SPINLOCK(irq_lock);
41
42 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
43
44 /* per-processor fixed function irqs */
45 struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = {
46
47 #if defined(CONFIG_SOC_AU1000)
48         { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
49         { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
50         { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
51         { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
52         { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
53         { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
54         { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
55         { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
56         { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
57         { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
58         { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
59         { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
60         { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
61         { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
62         { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
63         { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
64         { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
65         { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
66         { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
67         { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
68         { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
69         { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
70         { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
71         { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
72         { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
73         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
74         { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
75         { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
76         { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
77         { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
78         { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
79
80 #elif defined(CONFIG_SOC_AU1500)
81
82         { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
83         { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
84         { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
85         { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
86         { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
87         { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
88         { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
89         { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
90         { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
91         { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
92         { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
93         { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
94         { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
95         { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
96         { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
97         { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
98         { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
99         { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
100         { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
101         { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
102         { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
103         { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
104         { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
105         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
106         { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
107         { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
108         { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
109         { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
110         { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
111
112 #elif defined(CONFIG_SOC_AU1100)
113
114         { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
115         { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
116         { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117         { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118         { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
119         { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
120         { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
121         { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
122         { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
123         { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
124         { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
125         { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
126         { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
127         { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
128         { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
129         { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
130         { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
131         { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
132         { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
133         { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
134         { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
135         { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
136         { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
137         { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
138         { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
139         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
140         { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
141         { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
142         { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
143         { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
144         { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
145
146 #elif defined(CONFIG_SOC_AU1550)
147
148         { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
149         { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
150         { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
151         { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
152         { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
153         { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
154         { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
155         { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
156         { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157         { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
158         { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
159         { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160         { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
161         { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
162         { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
163         { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
164         { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
165         { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
166         { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
167         { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
168         { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
169         { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
170         { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
171         { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
172         { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
173         { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
174         { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
175         { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
176
177 #elif defined(CONFIG_SOC_AU1200)
178
179         { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
180         { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
181         { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
182         { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183         { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184         { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
185         { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186         { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187         { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188         { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
189         { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
190         { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
191         { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
192         { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
193         { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
194         { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
195         { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
196         { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
197         { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
198         { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
199         { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
200         { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
201         { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
202
203 #else
204 #error "Error: Unknown Alchemy SOC"
205 #endif
206 };
207
208
209 #ifdef CONFIG_PM
210
211 /*
212  * Save/restore the interrupt controller state.
213  * Called from the save/restore core registers as part of the
214  * au_sleep function in power.c.....maybe I should just pm_register()
215  * them instead?
216  */
217 static unsigned int     sleep_intctl_config0[2];
218 static unsigned int     sleep_intctl_config1[2];
219 static unsigned int     sleep_intctl_config2[2];
220 static unsigned int     sleep_intctl_src[2];
221 static unsigned int     sleep_intctl_assign[2];
222 static unsigned int     sleep_intctl_wake[2];
223 static unsigned int     sleep_intctl_mask[2];
224
225 void save_au1xxx_intctl(void)
226 {
227         sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
228         sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
229         sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
230         sleep_intctl_src[0] = au_readl(IC0_SRCRD);
231         sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
232         sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
233         sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
234
235         sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
236         sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
237         sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
238         sleep_intctl_src[1] = au_readl(IC1_SRCRD);
239         sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
240         sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
241         sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
242 }
243
244 /*
245  * For most restore operations, we clear the entire register and
246  * then set the bits we found during the save.
247  */
248 void restore_au1xxx_intctl(void)
249 {
250         au_writel(0xffffffff, IC0_MASKCLR); au_sync();
251
252         au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
253         au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
254         au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
255         au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
256         au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
257         au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
258         au_writel(0xffffffff, IC0_SRCCLR); au_sync();
259         au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
260         au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
261         au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
262         au_writel(0xffffffff, IC0_WAKECLR); au_sync();
263         au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
264         au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
265         au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
266         au_writel(0x00000000, IC0_TESTBIT); au_sync();
267
268         au_writel(0xffffffff, IC1_MASKCLR); au_sync();
269
270         au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
271         au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
272         au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
273         au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
274         au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
275         au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
276         au_writel(0xffffffff, IC1_SRCCLR); au_sync();
277         au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
278         au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
279         au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
280         au_writel(0xffffffff, IC1_WAKECLR); au_sync();
281         au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
282         au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
283         au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
284         au_writel(0x00000000, IC1_TESTBIT); au_sync();
285
286         au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
287
288         au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
289 }
290 #endif /* CONFIG_PM */
291
292
293 static void au1x_ic0_unmask(unsigned int irq_nr)
294 {
295         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
296         au_writel(1 << bit, IC0_MASKSET);
297         au_writel(1 << bit, IC0_WAKESET);
298         au_sync();
299 }
300
301 static void au1x_ic1_unmask(unsigned int irq_nr)
302 {
303         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
304         au_writel(1 << bit, IC1_MASKSET);
305         au_writel(1 << bit, IC1_WAKESET);
306
307 /* very hacky. does the pb1000 cpld auto-disable this int?
308  * nowhere in the current kernel sources is it disabled.        --mlau
309  */
310 #if defined(CONFIG_MIPS_PB1000)
311         if (irq_nr == AU1000_GPIO_15)
312                 au_writel(0x4000, PB1000_MDR); /* enable int */
313 #endif
314         au_sync();
315 }
316
317 static void au1x_ic0_mask(unsigned int irq_nr)
318 {
319         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
320         au_writel(1 << bit, IC0_MASKCLR);
321         au_writel(1 << bit, IC0_WAKECLR);
322         au_sync();
323 }
324
325 static void au1x_ic1_mask(unsigned int irq_nr)
326 {
327         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
328         au_writel(1 << bit, IC1_MASKCLR);
329         au_writel(1 << bit, IC1_WAKECLR);
330         au_sync();
331 }
332
333 static void au1x_ic0_ack(unsigned int irq_nr)
334 {
335         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
336
337         /*
338          * This may assume that we don't get interrupts from
339          * both edges at once, or if we do, that we don't care.
340          */
341         au_writel(1 << bit, IC0_FALLINGCLR);
342         au_writel(1 << bit, IC0_RISINGCLR);
343         au_sync();
344 }
345
346 static void au1x_ic1_ack(unsigned int irq_nr)
347 {
348         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
349
350         /*
351          * This may assume that we don't get interrupts from
352          * both edges at once, or if we do, that we don't care.
353          */
354         au_writel(1 << bit, IC1_FALLINGCLR);
355         au_writel(1 << bit, IC1_RISINGCLR);
356         au_sync();
357 }
358
359 static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
360 {
361         unsigned int bit = irq - AU1000_INTC1_INT_BASE;
362         unsigned long wakemsk, flags;
363
364         /* only GPIO 0-7 can act as wakeup source: */
365         if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))
366                 return -EINVAL;
367
368         local_irq_save(flags);
369         wakemsk = au_readl(SYS_WAKEMSK);
370         if (on)
371                 wakemsk |= 1 << bit;
372         else
373                 wakemsk &= ~(1 << bit);
374         au_writel(wakemsk, SYS_WAKEMSK);
375         au_sync();
376         local_irq_restore(flags);
377
378         return 0;
379 }
380
381 /*
382  * irq_chips for both ICs; this way the mask handlers can be
383  * as short as possible.
384  *
385  * NOTE: the ->ack() callback is used by the handle_edge_irq
386  *       flowhandler only, the ->mask_ack() one by handle_level_irq,
387  *       so no need for an irq_chip for each type of irq (level/edge).
388  */
389 static struct irq_chip au1x_ic0_chip = {
390         .name           = "Alchemy-IC0",
391         .ack            = au1x_ic0_ack,         /* edge */
392         .mask           = au1x_ic0_mask,
393         .mask_ack       = au1x_ic0_mask,        /* level */
394         .unmask         = au1x_ic0_unmask,
395         .set_type       = au1x_ic_settype,
396 };
397
398 static struct irq_chip au1x_ic1_chip = {
399         .name           = "Alchemy-IC1",
400         .ack            = au1x_ic1_ack,         /* edge */
401         .mask           = au1x_ic1_mask,
402         .mask_ack       = au1x_ic1_mask,        /* level */
403         .unmask         = au1x_ic1_unmask,
404         .set_type       = au1x_ic_settype,
405         .set_wake       = au1x_ic1_setwake,
406 };
407
408 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
409 {
410         struct irq_chip *chip;
411         unsigned long icr[6];
412         unsigned int bit, ic;
413         int ret;
414
415         if (irq >= AU1000_INTC1_INT_BASE) {
416                 bit = irq - AU1000_INTC1_INT_BASE;
417                 chip = &au1x_ic1_chip;
418                 ic = 1;
419         } else {
420                 bit = irq - AU1000_INTC0_INT_BASE;
421                 chip = &au1x_ic0_chip;
422                 ic = 0;
423         }
424
425         if (bit > 31)
426                 return -EINVAL;
427
428         icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
429         icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
430         icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
431         icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
432         icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
433         icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
434
435         ret = 0;
436
437         switch (flow_type) {    /* cfgregs 2:1:0 */
438         case IRQ_TYPE_EDGE_RISING:      /* 0:0:1 */
439                 au_writel(1 << bit, icr[5]);
440                 au_writel(1 << bit, icr[4]);
441                 au_writel(1 << bit, icr[0]);
442                 set_irq_chip_and_handler_name(irq, chip,
443                                 handle_edge_irq, "riseedge");
444                 break;
445         case IRQ_TYPE_EDGE_FALLING:     /* 0:1:0 */
446                 au_writel(1 << bit, icr[5]);
447                 au_writel(1 << bit, icr[1]);
448                 au_writel(1 << bit, icr[3]);
449                 set_irq_chip_and_handler_name(irq, chip,
450                                 handle_edge_irq, "falledge");
451                 break;
452         case IRQ_TYPE_EDGE_BOTH:        /* 0:1:1 */
453                 au_writel(1 << bit, icr[5]);
454                 au_writel(1 << bit, icr[1]);
455                 au_writel(1 << bit, icr[0]);
456                 set_irq_chip_and_handler_name(irq, chip,
457                                 handle_edge_irq, "bothedge");
458                 break;
459         case IRQ_TYPE_LEVEL_HIGH:       /* 1:0:1 */
460                 au_writel(1 << bit, icr[2]);
461                 au_writel(1 << bit, icr[4]);
462                 au_writel(1 << bit, icr[0]);
463                 set_irq_chip_and_handler_name(irq, chip,
464                                 handle_level_irq, "hilevel");
465                 break;
466         case IRQ_TYPE_LEVEL_LOW:        /* 1:1:0 */
467                 au_writel(1 << bit, icr[2]);
468                 au_writel(1 << bit, icr[1]);
469                 au_writel(1 << bit, icr[3]);
470                 set_irq_chip_and_handler_name(irq, chip,
471                                 handle_level_irq, "lowlevel");
472                 break;
473         case IRQ_TYPE_NONE:             /* 0:0:0 */
474                 au_writel(1 << bit, icr[5]);
475                 au_writel(1 << bit, icr[4]);
476                 au_writel(1 << bit, icr[3]);
477                 /* set at least chip so we can call set_irq_type() on it */
478                 set_irq_chip(irq, chip);
479                 break;
480         default:
481                 ret = -EINVAL;
482         }
483         au_sync();
484
485         return ret;
486 }
487
488 asmlinkage void plat_irq_dispatch(void)
489 {
490         unsigned int pending = read_c0_status() & read_c0_cause();
491         unsigned long s, off, bit;
492
493         if (pending & CAUSEF_IP7) {
494                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
495                 return;
496         } else if (pending & CAUSEF_IP2) {
497                 s = IC0_REQ0INT;
498                 off = AU1000_INTC0_INT_BASE;
499         } else if (pending & CAUSEF_IP3) {
500                 s = IC0_REQ1INT;
501                 off = AU1000_INTC0_INT_BASE;
502         } else if (pending & CAUSEF_IP4) {
503                 s = IC1_REQ0INT;
504                 off = AU1000_INTC1_INT_BASE;
505         } else if (pending & CAUSEF_IP5) {
506                 s = IC1_REQ1INT;
507                 off = AU1000_INTC1_INT_BASE;
508         } else
509                 goto spurious;
510
511         bit = 0;
512         s = au_readl(s);
513         if (unlikely(!s)) {
514 spurious:
515                 spurious_interrupt();
516                 return;
517         }
518 #ifdef AU1000_USB_DEV_REQ_INT
519         /*
520          * Because of the tight timing of SETUP token to reply
521          * transactions, the USB devices-side packet complete
522          * interrupt needs the highest priority.
523          */
524         bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
525         if ((pending & CAUSEF_IP2) && (s & bit)) {
526                 do_IRQ(AU1000_USB_DEV_REQ_INT);
527                 return;
528         }
529 #endif
530         do_IRQ(__ffs(s) + off);
531 }
532
533 /* setup edge/level and assign request 0/1 */
534 void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
535 {
536         unsigned int bit, irq_nr;
537
538         while (count--) {
539                 irq_nr = map[count].im_irq;
540
541                 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
542                      (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
543                     ((irq_nr < AU1000_INTC1_INT_BASE) ||
544                      (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
545                         continue;
546
547                 if (irq_nr >= AU1000_INTC1_INT_BASE) {
548                         bit = irq_nr - AU1000_INTC1_INT_BASE;
549                         if (map[count].im_request)
550                                 au_writel(1 << bit, IC1_ASSIGNCLR);
551                 } else {
552                         bit = irq_nr - AU1000_INTC0_INT_BASE;
553                         if (map[count].im_request)
554                                 au_writel(1 << bit, IC0_ASSIGNCLR);
555                 }
556
557                 au1x_ic_settype(irq_nr, map[count].im_type);
558         }
559 }
560
561 void __init arch_init_irq(void)
562 {
563         int i;
564
565         /*
566          * Initialize interrupt controllers to a safe state.
567          */
568         au_writel(0xffffffff, IC0_CFG0CLR);
569         au_writel(0xffffffff, IC0_CFG1CLR);
570         au_writel(0xffffffff, IC0_CFG2CLR);
571         au_writel(0xffffffff, IC0_MASKCLR);
572         au_writel(0xffffffff, IC0_ASSIGNSET);
573         au_writel(0xffffffff, IC0_WAKECLR);
574         au_writel(0xffffffff, IC0_SRCSET);
575         au_writel(0xffffffff, IC0_FALLINGCLR);
576         au_writel(0xffffffff, IC0_RISINGCLR);
577         au_writel(0x00000000, IC0_TESTBIT);
578
579         au_writel(0xffffffff, IC1_CFG0CLR);
580         au_writel(0xffffffff, IC1_CFG1CLR);
581         au_writel(0xffffffff, IC1_CFG2CLR);
582         au_writel(0xffffffff, IC1_MASKCLR);
583         au_writel(0xffffffff, IC1_ASSIGNSET);
584         au_writel(0xffffffff, IC1_WAKECLR);
585         au_writel(0xffffffff, IC1_SRCSET);
586         au_writel(0xffffffff, IC1_FALLINGCLR);
587         au_writel(0xffffffff, IC1_RISINGCLR);
588         au_writel(0x00000000, IC1_TESTBIT);
589
590         mips_cpu_irq_init();
591
592         /* register all 64 possible IC0+IC1 irq sources as type "none".
593          * Use set_irq_type() to set edge/level behaviour at runtime.
594          */
595         for (i = AU1000_INTC0_INT_BASE;
596              (i < AU1000_INTC0_INT_BASE + 32); i++)
597                 au1x_ic_settype(i, IRQ_TYPE_NONE);
598
599         for (i = AU1000_INTC1_INT_BASE;
600              (i < AU1000_INTC1_INT_BASE + 32); i++)
601                 au1x_ic_settype(i, IRQ_TYPE_NONE);
602
603         /*
604          * Initialize IC0, which is fixed per processor.
605          */
606         au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
607
608         /* Boards can register additional (GPIO-based) IRQs.
609         */
610         board_init_irq();
611
612         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
613 }
614
615 unsigned long save_local_and_disable(int controller)
616 {
617         int i;
618         unsigned long flags, mask;
619
620         spin_lock_irqsave(&irq_lock, flags);
621         if (controller) {
622                 mask = au_readl(IC1_MASKSET);
623                 for (i = 0; i < 32; i++)
624                         au1x_ic1_mask(i + AU1000_INTC1_INT_BASE);
625         } else {
626                 mask = au_readl(IC0_MASKSET);
627                 for (i = 0; i < 32; i++)
628                         au1x_ic0_mask(i + AU1000_INTC0_INT_BASE);
629         }
630         spin_unlock_irqrestore(&irq_lock, flags);
631
632         return mask;
633 }
634
635 void restore_local_and_enable(int controller, unsigned long mask)
636 {
637         int i;
638         unsigned long flags, new_mask;
639
640         spin_lock_irqsave(&irq_lock, flags);
641         for (i = 0; i < 32; i++)
642                 if (mask & (1 << i)) {
643                         if (controller)
644                                 au1x_ic1_unmask(i + AU1000_INTC1_INT_BASE);
645                         else
646                                 au1x_ic0_unmask(i + AU1000_INTC0_INT_BASE);
647                 }
648
649         if (controller)
650                 new_mask = au_readl(IC1_MASKSET);
651         else
652                 new_mask = au_readl(IC0_MASKSET);
653
654         spin_unlock_irqrestore(&irq_lock, flags);
655 }