[PATCH] m32r icu_data gcc4 fixes
[linux-2.6.git] / arch / m32r / kernel / setup_m32700ut.c
1 /*
2  *  linux/arch/m32r/kernel/setup_m32700ut.c
3  *
4  *  Setup routines for Renesas M32700UT Board
5  *
6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
7  *                           Hitoshi Yamamoto, Takeo Takahashi
8  *
9  *  This file is subject to the terms and conditions of the GNU General
10  *  Public License.  See the file "COPYING" in the main directory of this
11  *  archive for more details.
12  */
13
14 #include <linux/config.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19
20 #include <asm/system.h>
21 #include <asm/m32r.h>
22 #include <asm/io.h>
23
24 /*
25  * M32700 Interrupt Control Unit (Level 1)
26  */
27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
28
29 #ifndef CONFIG_SMP
30 typedef struct {
31         unsigned long icucr;  /* ICU Control Register */
32 } icu_data_t;
33 static icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
34 #else
35 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
36 #endif /* CONFIG_SMP */
37
38
39 static void disable_m32700ut_irq(unsigned int irq)
40 {
41         unsigned long port, data;
42
43         port = irq2port(irq);
44         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
45         outl(data, port);
46 }
47
48 static void enable_m32700ut_irq(unsigned int irq)
49 {
50         unsigned long port, data;
51
52         port = irq2port(irq);
53         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
54         outl(data, port);
55 }
56
57 static void mask_and_ack_m32700ut(unsigned int irq)
58 {
59         disable_m32700ut_irq(irq);
60 }
61
62 static void end_m32700ut_irq(unsigned int irq)
63 {
64         enable_m32700ut_irq(irq);
65 }
66
67 static unsigned int startup_m32700ut_irq(unsigned int irq)
68 {
69         enable_m32700ut_irq(irq);
70         return (0);
71 }
72
73 static void shutdown_m32700ut_irq(unsigned int irq)
74 {
75         unsigned long port;
76
77         port = irq2port(irq);
78         outl(M32R_ICUCR_ILEVEL7, port);
79 }
80
81 static struct hw_interrupt_type m32700ut_irq_type =
82 {
83         .typename = "M32700UT-IRQ",
84         .startup = startup_m32700ut_irq,
85         .shutdown = shutdown_m32700ut_irq,
86         .enable = enable_m32700ut_irq,
87         .disable = disable_m32700ut_irq,
88         .ack = mask_and_ack_m32700ut,
89         .end = end_m32700ut_irq
90 };
91
92 /*
93  * Interrupt Control Unit of PLD on M32700UT (Level 2)
94  */
95 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
96 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
97                                  (((x) - 1) * sizeof(unsigned short)))
98
99 typedef struct {
100         unsigned short icucr;  /* ICU Control Register */
101 } pld_icu_data_t;
102
103 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
104
105 static void disable_m32700ut_pld_irq(unsigned int irq)
106 {
107         unsigned long port, data;
108         unsigned int pldirq;
109
110         pldirq = irq2pldirq(irq);
111 //      disable_m32700ut_irq(M32R_IRQ_INT1);
112         port = pldirq2port(pldirq);
113         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
114         outw(data, port);
115 }
116
117 static void enable_m32700ut_pld_irq(unsigned int irq)
118 {
119         unsigned long port, data;
120         unsigned int pldirq;
121
122         pldirq = irq2pldirq(irq);
123 //      enable_m32700ut_irq(M32R_IRQ_INT1);
124         port = pldirq2port(pldirq);
125         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
126         outw(data, port);
127 }
128
129 static void mask_and_ack_m32700ut_pld(unsigned int irq)
130 {
131         disable_m32700ut_pld_irq(irq);
132 //      mask_and_ack_m32700ut(M32R_IRQ_INT1);
133 }
134
135 static void end_m32700ut_pld_irq(unsigned int irq)
136 {
137         enable_m32700ut_pld_irq(irq);
138         end_m32700ut_irq(M32R_IRQ_INT1);
139 }
140
141 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
142 {
143         enable_m32700ut_pld_irq(irq);
144         return (0);
145 }
146
147 static void shutdown_m32700ut_pld_irq(unsigned int irq)
148 {
149         unsigned long port;
150         unsigned int pldirq;
151
152         pldirq = irq2pldirq(irq);
153 //      shutdown_m32700ut_irq(M32R_IRQ_INT1);
154         port = pldirq2port(pldirq);
155         outw(PLD_ICUCR_ILEVEL7, port);
156 }
157
158 static struct hw_interrupt_type m32700ut_pld_irq_type =
159 {
160         .typename = "M32700UT-PLD-IRQ",
161         .startup = startup_m32700ut_pld_irq,
162         .shutdown = shutdown_m32700ut_pld_irq,
163         .enable = enable_m32700ut_pld_irq,
164         .disable = disable_m32700ut_pld_irq,
165         .ack = mask_and_ack_m32700ut_pld,
166         .end = end_m32700ut_pld_irq
167 };
168
169 /*
170  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
171  */
172 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
173 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
174                                  (((x) - 1) * sizeof(unsigned short)))
175
176 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
177
178 static void disable_m32700ut_lanpld_irq(unsigned int irq)
179 {
180         unsigned long port, data;
181         unsigned int pldirq;
182
183         pldirq = irq2lanpldirq(irq);
184         port = lanpldirq2port(pldirq);
185         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
186         outw(data, port);
187 }
188
189 static void enable_m32700ut_lanpld_irq(unsigned int irq)
190 {
191         unsigned long port, data;
192         unsigned int pldirq;
193
194         pldirq = irq2lanpldirq(irq);
195         port = lanpldirq2port(pldirq);
196         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
197         outw(data, port);
198 }
199
200 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
201 {
202         disable_m32700ut_lanpld_irq(irq);
203 }
204
205 static void end_m32700ut_lanpld_irq(unsigned int irq)
206 {
207         enable_m32700ut_lanpld_irq(irq);
208         end_m32700ut_irq(M32R_IRQ_INT0);
209 }
210
211 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
212 {
213         enable_m32700ut_lanpld_irq(irq);
214         return (0);
215 }
216
217 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
218 {
219         unsigned long port;
220         unsigned int pldirq;
221
222         pldirq = irq2lanpldirq(irq);
223         port = lanpldirq2port(pldirq);
224         outw(PLD_ICUCR_ILEVEL7, port);
225 }
226
227 static struct hw_interrupt_type m32700ut_lanpld_irq_type =
228 {
229         .typename = "M32700UT-PLD-LAN-IRQ",
230         .startup = startup_m32700ut_lanpld_irq,
231         .shutdown = shutdown_m32700ut_lanpld_irq,
232         .enable = enable_m32700ut_lanpld_irq,
233         .disable = disable_m32700ut_lanpld_irq,
234         .ack = mask_and_ack_m32700ut_lanpld,
235         .end = end_m32700ut_lanpld_irq
236 };
237
238 /*
239  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
240  */
241 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
242 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
243                                  (((x) - 1) * sizeof(unsigned short)))
244
245 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
246
247 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
248 {
249         unsigned long port, data;
250         unsigned int pldirq;
251
252         pldirq = irq2lcdpldirq(irq);
253         port = lcdpldirq2port(pldirq);
254         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
255         outw(data, port);
256 }
257
258 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
259 {
260         unsigned long port, data;
261         unsigned int pldirq;
262
263         pldirq = irq2lcdpldirq(irq);
264         port = lcdpldirq2port(pldirq);
265         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
266         outw(data, port);
267 }
268
269 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
270 {
271         disable_m32700ut_lcdpld_irq(irq);
272 }
273
274 static void end_m32700ut_lcdpld_irq(unsigned int irq)
275 {
276         enable_m32700ut_lcdpld_irq(irq);
277         end_m32700ut_irq(M32R_IRQ_INT2);
278 }
279
280 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
281 {
282         enable_m32700ut_lcdpld_irq(irq);
283         return (0);
284 }
285
286 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
287 {
288         unsigned long port;
289         unsigned int pldirq;
290
291         pldirq = irq2lcdpldirq(irq);
292         port = lcdpldirq2port(pldirq);
293         outw(PLD_ICUCR_ILEVEL7, port);
294 }
295
296 static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
297 {
298         .typename = "M32700UT-PLD-LCD-IRQ",
299         .startup = startup_m32700ut_lcdpld_irq,
300         .shutdown = shutdown_m32700ut_lcdpld_irq,
301         .enable = enable_m32700ut_lcdpld_irq,
302         .disable = disable_m32700ut_lcdpld_irq,
303         .ack = mask_and_ack_m32700ut_lcdpld,
304         .end = end_m32700ut_lcdpld_irq
305 };
306
307 void __init init_IRQ(void)
308 {
309 #if defined(CONFIG_SMC91X)
310         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
311         irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
312         irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
313         irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
314         irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1;       /* disable nested irq */
315         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
316         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
317 #endif  /* CONFIG_SMC91X */
318
319         /* MFT2 : system timer */
320         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
321         irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
322         irq_desc[M32R_IRQ_MFT2].action = 0;
323         irq_desc[M32R_IRQ_MFT2].depth = 1;
324         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
325         disable_m32700ut_irq(M32R_IRQ_MFT2);
326
327         /* SIO0 : receive */
328         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
329         irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
330         irq_desc[M32R_IRQ_SIO0_R].action = 0;
331         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
332         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
333         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
334
335         /* SIO0 : send */
336         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
337         irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
338         irq_desc[M32R_IRQ_SIO0_S].action = 0;
339         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
340         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
341         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
342
343         /* SIO1 : receive */
344         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
345         irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
346         irq_desc[M32R_IRQ_SIO1_R].action = 0;
347         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
348         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
349         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
350
351         /* SIO1 : send */
352         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
353         irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
354         irq_desc[M32R_IRQ_SIO1_S].action = 0;
355         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
356         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
357         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
358
359         /* DMA1 : */
360         irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
361         irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
362         irq_desc[M32R_IRQ_DMA1].action = 0;
363         irq_desc[M32R_IRQ_DMA1].depth = 1;
364         icu_data[M32R_IRQ_DMA1].icucr = 0;
365         disable_m32700ut_irq(M32R_IRQ_DMA1);
366
367 #ifdef CONFIG_SERIAL_M32R_PLDSIO
368         /* INT#1: SIO0 Receive on PLD */
369         irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
370         irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
371         irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
372         irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;   /* disable nested irq */
373         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
374         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
375
376         /* INT#1: SIO0 Send on PLD */
377         irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
378         irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
379         irq_desc[PLD_IRQ_SIO0_SND].action = 0;
380         irq_desc[PLD_IRQ_SIO0_SND].depth = 1;   /* disable nested irq */
381         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
382         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
383 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
384
385         /* INT#1: CFC IREQ on PLD */
386         irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
387         irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
388         irq_desc[PLD_IRQ_CFIREQ].action = 0;
389         irq_desc[PLD_IRQ_CFIREQ].depth = 1;     /* disable nested irq */
390         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
391         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
392
393         /* INT#1: CFC Insert on PLD */
394         irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
395         irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
396         irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
397         irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
398         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
399         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
400
401         /* INT#1: CFC Eject on PLD */
402         irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
403         irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
404         irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
405         irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;  /* disable nested irq */
406         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
407         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
408
409         /*
410          * INT0# is used for LAN, DIO
411          * We enable it here.
412          */
413         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
414         enable_m32700ut_irq(M32R_IRQ_INT0);
415
416         /*
417          * INT1# is used for UART, MMC, CF Controller in FPGA.
418          * We enable it here.
419          */
420         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
421         enable_m32700ut_irq(M32R_IRQ_INT1);
422
423 #if defined(CONFIG_USB)
424         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
425
426     irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
427     irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
428     irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
429     irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
430     lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;  /* "L" level sense */
431     disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
432 #endif
433         /*
434          * INT2# is used for BAT, USB, AUDIO
435          * We enable it here.
436          */
437         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
438         enable_m32700ut_irq(M32R_IRQ_INT2);
439
440 #if defined(CONFIG_VIDEO_M32R_AR)
441         /*
442          * INT3# is used for AR
443          */
444         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
445         irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
446         irq_desc[M32R_IRQ_INT3].action = 0;
447         irq_desc[M32R_IRQ_INT3].depth = 1;
448         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
449         disable_m32700ut_irq(M32R_IRQ_INT3);
450 #endif  /* CONFIG_VIDEO_M32R_AR */
451 }
452
453 #if defined(CONFIG_SMC91X)
454
455 #define LAN_IOSTART     0x300
456 #define LAN_IOEND       0x320
457 static struct resource smc91x_resources[] = {
458         [0] = {
459                 .start  = (LAN_IOSTART),
460                 .end    = (LAN_IOEND),
461                 .flags  = IORESOURCE_MEM,
462         },
463         [1] = {
464                 .start  = M32700UT_LAN_IRQ_LAN,
465                 .end    = M32700UT_LAN_IRQ_LAN,
466                 .flags  = IORESOURCE_IRQ,
467         }
468 };
469
470 static struct platform_device smc91x_device = {
471         .name           = "smc91x",
472         .id             = 0,
473         .num_resources  = ARRAY_SIZE(smc91x_resources),
474         .resource       = smc91x_resources,
475 };
476 #endif
477
478 #if defined(CONFIG_FB_S1D13XXX)
479
480 #include <video/s1d13xxxfb.h>
481 #include <asm/s1d13806.h>
482
483 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
484         .initregs               = s1d13xxxfb_initregs,
485         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
486         .platform_init_video    = NULL,
487 #ifdef CONFIG_PM
488         .platform_suspend_video = NULL,
489         .platform_resume_video  = NULL,
490 #endif
491 };
492
493 static struct resource s1d13xxxfb_resources[] = {
494         [0] = {
495                 .start  = 0x10600000UL,
496                 .end    = 0x1073FFFFUL,
497                 .flags  = IORESOURCE_MEM,
498         },
499         [1] = {
500                 .start  = 0x10400000UL,
501                 .end    = 0x104001FFUL,
502                 .flags  = IORESOURCE_MEM,
503         }
504 };
505
506 static struct platform_device s1d13xxxfb_device = {
507         .name           = S1D_DEVICENAME,
508         .id             = 0,
509         .dev            = {
510                 .platform_data  = &s1d13xxxfb_data,
511         },
512         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
513         .resource       = s1d13xxxfb_resources,
514 };
515 #endif
516
517 static int __init platform_init(void)
518 {
519 #if defined(CONFIG_SMC91X)
520         platform_device_register(&smc91x_device);
521 #endif
522 #if defined(CONFIG_FB_S1D13XXX)
523         platform_device_register(&s1d13xxxfb_device);
524 #endif
525         return 0;
526 }
527 arch_initcall(platform_init);