2 * SN2 Platform specific SMP Support
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/threads.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/mmzone.h>
20 #include <linux/module.h>
21 #include <linux/bitops.h>
22 #include <linux/nodemask.h>
23 #include <linux/proc_fs.h>
24 #include <linux/seq_file.h>
26 #include <asm/processor.h>
29 #include <asm/system.h>
30 #include <asm/delay.h>
35 #include <asm/hw_irq.h>
36 #include <asm/current.h>
37 #include <asm/sn/sn_cpuid.h>
38 #include <asm/sn/sn_sal.h>
39 #include <asm/sn/addrs.h>
40 #include <asm/sn/shub_mmr.h>
41 #include <asm/sn/nodepda.h>
42 #include <asm/sn/rw_mmr.h>
44 DEFINE_PER_CPU(struct ptc_stats, ptcstats);
45 DECLARE_PER_CPU(struct ptc_stats, ptcstats);
47 static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
49 void sn2_ptc_deadlock_recovery(short *, short, int, volatile unsigned long *, unsigned long data0,
50 volatile unsigned long *, unsigned long data1);
56 * xyz - 3 digit hex number:
57 * x - Force PTC purges to use shub:
61 * 0 - disable interrupts
62 * 1 - leave interuupts enabled
68 * Note: on shub1, only ptctest == 0 is supported. Don't try other values!
71 static unsigned int sn2_ptctest = 0;
73 static int __init ptc_test(char *str)
75 get_option(&str, &sn2_ptctest);
78 __setup("ptctest=", ptc_test);
80 static inline int ptc_lock(unsigned long *flagp)
82 unsigned long opt = sn2_ptctest & 255;
86 spin_lock_irqsave(&sn2_global_ptc_lock, *flagp);
89 spin_lock_irqsave(&sn_nodepda->ptc_lock, *flagp);
92 local_irq_save(*flagp);
95 spin_lock(&sn2_global_ptc_lock);
98 spin_lock(&sn_nodepda->ptc_lock);
108 static inline void ptc_unlock(unsigned long flags, int opt)
112 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
115 spin_unlock_irqrestore(&sn_nodepda->ptc_lock, flags);
118 local_irq_restore(flags);
121 spin_unlock(&sn2_global_ptc_lock);
124 spin_unlock(&sn_nodepda->ptc_lock);
134 #define sn2_ptctest 0
136 static inline int ptc_lock(unsigned long *flagp)
138 spin_lock_irqsave(&sn2_global_ptc_lock, *flagp);
142 static inline void ptc_unlock(unsigned long flags, int opt)
144 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
150 unsigned long change_rid;
151 unsigned long shub_ptc_flushes;
152 unsigned long nodes_flushed;
153 unsigned long deadlocks;
154 unsigned long lock_itc_clocks;
155 unsigned long shub_itc_clocks;
156 unsigned long shub_itc_clocks_max;
159 static inline unsigned long wait_piowc(void)
161 volatile unsigned long *piows, zeroval;
164 piows = pda->pio_write_status_addr;
165 zeroval = pda->pio_write_status_val;
168 } while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
173 * sn_migrate - SN-specific task migration actions
174 * @task: Task being migrated to new CPU
176 * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
177 * Context switching user threads which have memory-mapped MMIO may cause
178 * PIOs to issue from seperate CPUs, thus the PIO writes must be drained
179 * from the previous CPU's Shub before execution resumes on the new CPU.
181 void sn_migrate(struct task_struct *task)
183 pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
184 volatile unsigned long *adr = last_pda->pio_write_status_addr;
185 unsigned long val = last_pda->pio_write_status_val;
187 /* Drain PIO writes from old CPU's Shub */
188 while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
193 void sn_tlb_migrate_finish(struct mm_struct *mm)
195 if (mm == current->mm)
200 * sn2_global_tlb_purge - globally purge translation cache of virtual address range
201 * @mm: mm_struct containing virtual address range
202 * @start: start of virtual address range
203 * @end: end of virtual address range
204 * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
206 * Purges the translation caches of all processors of the given virtual address
210 * - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
211 * - cpu_vm_mask is converted into a nodemask of the nodes containing the
212 * cpus in cpu_vm_mask.
213 * - if only one bit is set in cpu_vm_mask & it is the current cpu & the
214 * process is purging its own virtual address range, then only the
215 * local TLB needs to be flushed. This flushing can be done using
216 * ptc.l. This is the common case & avoids the global spinlock.
217 * - if multiple cpus have loaded the context, then flushing has to be
218 * done with ptc.g/MMRs under protection of the global ptc_lock.
222 sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
223 unsigned long end, unsigned long nbits)
225 int i, opt, shub1, cnode, mynasid, cpu, lcpu = 0, nasid, flushed = 0;
226 int mymm = (mm == current->active_mm && current->mm);
227 volatile unsigned long *ptc0, *ptc1;
228 unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value;
229 short nasids[MAX_NUMNODES], nix;
230 nodemask_t nodes_flushed;
232 nodes_clear(nodes_flushed);
235 for_each_cpu_mask(cpu, mm->cpu_vm_mask) {
236 cnode = cpu_to_node(cpu);
237 node_set(cnode, nodes_flushed);
247 if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
249 ia64_ptcl(start, nbits << 2);
250 start += (1UL << nbits);
251 } while (start < end);
253 __get_cpu_var(ptcstats).ptc_l++;
258 if (atomic_read(&mm->mm_users) == 1 && mymm) {
260 __get_cpu_var(ptcstats).change_rid++;
265 itc = ia64_get_itc();
267 for_each_node_mask(cnode, nodes_flushed)
268 nasids[nix++] = cnodeid_to_nasid(cnode);
270 rr_value = (mm->context << 3) | REGION_NUMBER(start);
274 data0 = (1UL << SH1_PTC_0_A_SHFT) |
275 (nbits << SH1_PTC_0_PS_SHFT) |
276 (rr_value << SH1_PTC_0_RID_SHFT) |
277 (1UL << SH1_PTC_0_START_SHFT);
278 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
279 ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
281 data0 = (1UL << SH2_PTC_A_SHFT) |
282 (nbits << SH2_PTC_PS_SHFT) |
283 (1UL << SH2_PTC_START_SHFT);
284 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
285 (rr_value << SH2_PTC_RID_SHFT));
290 mynasid = get_nasid();
292 itc = ia64_get_itc();
293 opt = ptc_lock(&flags);
294 itc2 = ia64_get_itc();
295 __get_cpu_var(ptcstats).lock_itc_clocks += itc2 - itc;
296 __get_cpu_var(ptcstats).shub_ptc_flushes++;
297 __get_cpu_var(ptcstats).nodes_flushed += nix;
301 data1 = start | (1UL << SH1_PTC_1_START_SHFT);
303 data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
304 for (i = 0; i < nix; i++) {
306 if ((!(sn2_ptctest & 3)) && unlikely(nasid == mynasid && mymm)) {
307 ia64_ptcga(start, nbits << 2);
310 ptc0 = CHANGE_NASID(nasid, ptc0);
312 ptc1 = CHANGE_NASID(nasid, ptc1);
313 pio_atomic_phys_write_mmrs(ptc0, data0, ptc1,
320 (SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK))) {
321 sn2_ptc_deadlock_recovery(nasids, nix, mynasid, ptc0, data0, ptc1, data1);
324 start += (1UL << nbits);
326 } while (start < end);
328 itc2 = ia64_get_itc() - itc2;
329 __get_cpu_var(ptcstats).shub_itc_clocks += itc2;
330 if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
331 __get_cpu_var(ptcstats).shub_itc_clocks_max = itc2;
333 ptc_unlock(flags, opt);
339 * sn2_ptc_deadlock_recovery
341 * Recover from PTC deadlocks conditions. Recovery requires stepping thru each
342 * TLB flush transaction. The recovery sequence is somewhat tricky & is
343 * coded in assembly language.
345 void sn2_ptc_deadlock_recovery(short *nasids, short nix, int mynasid, volatile unsigned long *ptc0, unsigned long data0,
346 volatile unsigned long *ptc1, unsigned long data1)
348 extern void sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
349 volatile unsigned long *, unsigned long, volatile unsigned long *, unsigned long);
351 unsigned long *piows, zeroval;
353 __get_cpu_var(ptcstats).deadlocks++;
355 piows = (unsigned long *) pda->pio_write_status_addr;
356 zeroval = pda->pio_write_status_val;
358 for (i=0; i < nix; i++) {
360 if (!(sn2_ptctest & 3) && nasid == mynasid)
362 ptc0 = CHANGE_NASID(nasid, ptc0);
364 ptc1 = CHANGE_NASID(nasid, ptc1);
365 sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
371 * sn_send_IPI_phys - send an IPI to a Nasid and slice
372 * @nasid: nasid to receive the interrupt (may be outside partition)
373 * @physid: physical cpuid to receive the interrupt.
374 * @vector: command to send
375 * @delivery_mode: delivery mechanism
377 * Sends an IPI (interprocessor interrupt) to the processor specified by
380 * @delivery_mode can be one of the following
382 * %IA64_IPI_DM_INT - pend an interrupt
383 * %IA64_IPI_DM_PMI - pend a PMI
384 * %IA64_IPI_DM_NMI - pend an NMI
385 * %IA64_IPI_DM_INIT - pend an INIT interrupt
387 void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
390 unsigned long flags = 0;
393 p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
394 val = (1UL << SH_IPI_INT_SEND_SHFT) |
395 (physid << SH_IPI_INT_PID_SHFT) |
396 ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
397 ((long)vector << SH_IPI_INT_IDX_SHFT) |
398 (0x000feeUL << SH_IPI_INT_BASE_SHFT);
401 if (enable_shub_wars_1_1()) {
402 spin_lock_irqsave(&sn2_global_ptc_lock, flags);
404 pio_phys_write_mmr(p, val);
405 if (enable_shub_wars_1_1()) {
407 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
412 EXPORT_SYMBOL(sn_send_IPI_phys);
415 * sn2_send_IPI - send an IPI to a processor
416 * @cpuid: target of the IPI
417 * @vector: command to send
418 * @delivery_mode: delivery mechanism
419 * @redirect: redirect the IPI?
421 * Sends an IPI (InterProcessor Interrupt) to the processor specified by
422 * @cpuid. @vector specifies the command to send, while @delivery_mode can
423 * be one of the following
425 * %IA64_IPI_DM_INT - pend an interrupt
426 * %IA64_IPI_DM_PMI - pend a PMI
427 * %IA64_IPI_DM_NMI - pend an NMI
428 * %IA64_IPI_DM_INIT - pend an INIT interrupt
430 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
435 physid = cpu_physical_id(cpuid);
436 nasid = cpuid_to_nasid(cpuid);
438 /* the following is used only when starting cpus at boot time */
439 if (unlikely(nasid == -1))
440 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
442 sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
445 #ifdef CONFIG_PROC_FS
447 #define PTC_BASENAME "sgi_sn/ptc_statistics"
449 static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
451 if (*offset < NR_CPUS)
456 static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
459 if (*offset < NR_CPUS)
464 static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
468 static int sn2_ptc_seq_show(struct seq_file *file, void *data)
470 struct ptc_stats *stat;
473 cpu = *(loff_t *) data;
476 seq_printf(file, "# ptc_l change_rid shub_ptc_flushes shub_nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max\n");
477 seq_printf(file, "# ptctest %d\n", sn2_ptctest);
480 if (cpu < NR_CPUS && cpu_online(cpu)) {
481 stat = &per_cpu(ptcstats, cpu);
482 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
483 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
485 1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
486 1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
487 1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec);
493 static struct seq_operations sn2_ptc_seq_ops = {
494 .start = sn2_ptc_seq_start,
495 .next = sn2_ptc_seq_next,
496 .stop = sn2_ptc_seq_stop,
497 .show = sn2_ptc_seq_show
500 int sn2_ptc_proc_open(struct inode *inode, struct file *file)
502 return seq_open(file, &sn2_ptc_seq_ops);
505 static struct file_operations proc_sn2_ptc_operations = {
506 .open = sn2_ptc_proc_open,
509 .release = seq_release,
512 static struct proc_dir_entry *proc_sn2_ptc;
514 static int __init sn2_ptc_init(void)
516 if (!ia64_platform_is("sn2"))
519 if (!(proc_sn2_ptc = create_proc_entry(PTC_BASENAME, 0444, NULL))) {
520 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
523 proc_sn2_ptc->proc_fops = &proc_sn2_ptc_operations;
524 spin_lock_init(&sn2_global_ptc_lock);
528 static void __exit sn2_ptc_exit(void)
530 remove_proc_entry(PTC_BASENAME, NULL);
533 module_init(sn2_ptc_init);
534 module_exit(sn2_ptc_exit);
535 #endif /* CONFIG_PROC_FS */