[PATCH] genirq: cleanup: remove irq_descp()
[linux-2.6.git] / arch / ia64 / kernel / mca.c
1 /*
2  * File:        mca.c
3  * Purpose:     Generic MCA handling layer
4  *
5  * Updated for latest kernel
6  * Copyright (C) 2003 Hewlett-Packard Co
7  *      David Mosberger-Tang <davidm@hpl.hp.com>
8  *
9  * Copyright (C) 2002 Dell Inc.
10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
11  *
12  * Copyright (C) 2002 Intel
13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
14  *
15  * Copyright (C) 2001 Intel
16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
17  *
18  * Copyright (C) 2000 Intel
19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
20  *
21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
23  *
24  * 03/04/15 D. Mosberger Added INIT backtrace support.
25  * 02/03/25 M. Domsch   GUID cleanups
26  *
27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
28  *                      error flag, set SAL default return values, changed
29  *                      error record structure to linked list, added init call
30  *                      to sal_get_state_info_size().
31  *
32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
33  *                      platform errors, completed code for logging of
34  *                      corrected & uncorrected machine check errors, and
35  *                      updated for conformance with Nov. 2000 revision of the
36  *                      SAL 3.0 spec.
37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38  *                           added min save state dump, added INIT handler.
39  *
40  * 2003-12-08 Keith Owens <kaos@sgi.com>
41  *            smp_call_function() must not be called from interrupt context (can
42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
43  *
44  * 2004-02-01 Keith Owens <kaos@sgi.com>
45  *            Avoid deadlock when using printk() for MCA and INIT records.
46  *            Delete all record printing code, moved to salinfo_decode in user space.
47  *            Mark variables and functions static where possible.
48  *            Delete dead variables and functions.
49  *            Reorder to remove the need for forward declarations and to consolidate
50  *            related code.
51  *
52  * 2005-08-12 Keith Owens <kaos@sgi.com>
53  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
54  *
55  * 2005-10-07 Keith Owens <kaos@sgi.com>
56  *            Add notify_die() hooks.
57  */
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/init.h>
61 #include <linux/sched.h>
62 #include <linux/interrupt.h>
63 #include <linux/irq.h>
64 #include <linux/smp_lock.h>
65 #include <linux/bootmem.h>
66 #include <linux/acpi.h>
67 #include <linux/timer.h>
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/smp.h>
71 #include <linux/workqueue.h>
72 #include <linux/cpumask.h>
73
74 #include <asm/delay.h>
75 #include <asm/kdebug.h>
76 #include <asm/machvec.h>
77 #include <asm/meminit.h>
78 #include <asm/page.h>
79 #include <asm/ptrace.h>
80 #include <asm/system.h>
81 #include <asm/sal.h>
82 #include <asm/mca.h>
83
84 #include <asm/irq.h>
85 #include <asm/hw_irq.h>
86
87 #include "mca_drv.h"
88 #include "entry.h"
89
90 #if defined(IA64_MCA_DEBUG_INFO)
91 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
92 #else
93 # define IA64_MCA_DEBUG(fmt...)
94 #endif
95
96 /* Used by mca_asm.S */
97 u32                             ia64_mca_serialize;
98 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
99 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
100 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
101 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
102
103 unsigned long __per_cpu_mca[NR_CPUS];
104
105 /* In mca_asm.S */
106 extern void                     ia64_os_init_dispatch_monarch (void);
107 extern void                     ia64_os_init_dispatch_slave (void);
108
109 static int monarch_cpu = -1;
110
111 static ia64_mc_info_t           ia64_mc_info;
112
113 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
114 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
115 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
116 #define CPE_HISTORY_LENGTH    5
117 #define CMC_HISTORY_LENGTH    5
118
119 static struct timer_list cpe_poll_timer;
120 static struct timer_list cmc_poll_timer;
121 /*
122  * This variable tells whether we are currently in polling mode.
123  * Start with this in the wrong state so we won't play w/ timers
124  * before the system is ready.
125  */
126 static int cmc_polling_enabled = 1;
127
128 /*
129  * Clearing this variable prevents CPE polling from getting activated
130  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
131  * but encounters problems retrieving CPE logs.  This should only be
132  * necessary for debugging.
133  */
134 static int cpe_poll_enabled = 1;
135
136 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
137
138 static int mca_init __initdata;
139
140
141 static void inline
142 ia64_mca_spin(const char *func)
143 {
144         printk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
145         while (1)
146                 cpu_relax();
147 }
148 /*
149  * IA64_MCA log support
150  */
151 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
152 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
153
154 typedef struct ia64_state_log_s
155 {
156         spinlock_t      isl_lock;
157         int             isl_index;
158         unsigned long   isl_count;
159         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
160 } ia64_state_log_t;
161
162 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
163
164 #define IA64_LOG_ALLOCATE(it, size) \
165         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
166                 (ia64_err_rec_t *)alloc_bootmem(size); \
167         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
168                 (ia64_err_rec_t *)alloc_bootmem(size);}
169 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
170 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
171 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
172 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
173 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
174 #define IA64_LOG_INDEX_INC(it) \
175     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
176     ia64_state_log[it].isl_count++;}
177 #define IA64_LOG_INDEX_DEC(it) \
178     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
179 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
180 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
181 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
182
183 /*
184  * ia64_log_init
185  *      Reset the OS ia64 log buffer
186  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
187  * Outputs      :       None
188  */
189 static void __init
190 ia64_log_init(int sal_info_type)
191 {
192         u64     max_size = 0;
193
194         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
195         IA64_LOG_LOCK_INIT(sal_info_type);
196
197         // SAL will tell us the maximum size of any error record of this type
198         max_size = ia64_sal_get_state_info_size(sal_info_type);
199         if (!max_size)
200                 /* alloc_bootmem() doesn't like zero-sized allocations! */
201                 return;
202
203         // set up OS data structures to hold error info
204         IA64_LOG_ALLOCATE(sal_info_type, max_size);
205         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
206         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
207 }
208
209 /*
210  * ia64_log_get
211  *
212  *      Get the current MCA log from SAL and copy it into the OS log buffer.
213  *
214  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
215  *              irq_safe    whether you can use printk at this point
216  *  Outputs :   size        (total record length)
217  *              *buffer     (ptr to error record)
218  *
219  */
220 static u64
221 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
222 {
223         sal_log_record_header_t     *log_buffer;
224         u64                         total_len = 0;
225         int                         s;
226
227         IA64_LOG_LOCK(sal_info_type);
228
229         /* Get the process state information */
230         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
231
232         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
233
234         if (total_len) {
235                 IA64_LOG_INDEX_INC(sal_info_type);
236                 IA64_LOG_UNLOCK(sal_info_type);
237                 if (irq_safe) {
238                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
239                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
240                 }
241                 *buffer = (u8 *) log_buffer;
242                 return total_len;
243         } else {
244                 IA64_LOG_UNLOCK(sal_info_type);
245                 return 0;
246         }
247 }
248
249 /*
250  *  ia64_mca_log_sal_error_record
251  *
252  *  This function retrieves a specified error record type from SAL
253  *  and wakes up any processes waiting for error records.
254  *
255  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
256  *              FIXME: remove MCA and irq_safe.
257  */
258 static void
259 ia64_mca_log_sal_error_record(int sal_info_type)
260 {
261         u8 *buffer;
262         sal_log_record_header_t *rh;
263         u64 size;
264         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
265 #ifdef IA64_MCA_DEBUG_INFO
266         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
267 #endif
268
269         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
270         if (!size)
271                 return;
272
273         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
274
275         if (irq_safe)
276                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
277                         smp_processor_id(),
278                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
279
280         /* Clear logs from corrected errors in case there's no user-level logger */
281         rh = (sal_log_record_header_t *)buffer;
282         if (rh->severity == sal_log_severity_corrected)
283                 ia64_sal_clear_state_info(sal_info_type);
284 }
285
286 /*
287  * search_mca_table
288  *  See if the MCA surfaced in an instruction range
289  *  that has been tagged as recoverable.
290  *
291  *  Inputs
292  *      first   First address range to check
293  *      last    Last address range to check
294  *      ip      Instruction pointer, address we are looking for
295  *
296  * Return value:
297  *      1 on Success (in the table)/ 0 on Failure (not in the  table)
298  */
299 int
300 search_mca_table (const struct mca_table_entry *first,
301                 const struct mca_table_entry *last,
302                 unsigned long ip)
303 {
304         const struct mca_table_entry *curr;
305         u64 curr_start, curr_end;
306
307         curr = first;
308         while (curr <= last) {
309                 curr_start = (u64) &curr->start_addr + curr->start_addr;
310                 curr_end = (u64) &curr->end_addr + curr->end_addr;
311
312                 if ((ip >= curr_start) && (ip <= curr_end)) {
313                         return 1;
314                 }
315                 curr++;
316         }
317         return 0;
318 }
319
320 /* Given an address, look for it in the mca tables. */
321 int mca_recover_range(unsigned long addr)
322 {
323         extern struct mca_table_entry __start___mca_table[];
324         extern struct mca_table_entry __stop___mca_table[];
325
326         return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
327 }
328 EXPORT_SYMBOL_GPL(mca_recover_range);
329
330 #ifdef CONFIG_ACPI
331
332 int cpe_vector = -1;
333 int ia64_cpe_irq = -1;
334
335 static irqreturn_t
336 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
337 {
338         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
339         static int              index;
340         static DEFINE_SPINLOCK(cpe_history_lock);
341
342         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
343                        __FUNCTION__, cpe_irq, smp_processor_id());
344
345         /* SAL spec states this should run w/ interrupts enabled */
346         local_irq_enable();
347
348         /* Get the CPE error record and log it */
349         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
350
351         spin_lock(&cpe_history_lock);
352         if (!cpe_poll_enabled && cpe_vector >= 0) {
353
354                 int i, count = 1; /* we know 1 happened now */
355                 unsigned long now = jiffies;
356
357                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
358                         if (now - cpe_history[i] <= HZ)
359                                 count++;
360                 }
361
362                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
363                 if (count >= CPE_HISTORY_LENGTH) {
364
365                         cpe_poll_enabled = 1;
366                         spin_unlock(&cpe_history_lock);
367                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
368
369                         /*
370                          * Corrected errors will still be corrected, but
371                          * make sure there's a log somewhere that indicates
372                          * something is generating more than we can handle.
373                          */
374                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
375
376                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
377
378                         /* lock already released, get out now */
379                         return IRQ_HANDLED;
380                 } else {
381                         cpe_history[index++] = now;
382                         if (index == CPE_HISTORY_LENGTH)
383                                 index = 0;
384                 }
385         }
386         spin_unlock(&cpe_history_lock);
387         return IRQ_HANDLED;
388 }
389
390 #endif /* CONFIG_ACPI */
391
392 #ifdef CONFIG_ACPI
393 /*
394  * ia64_mca_register_cpev
395  *
396  *  Register the corrected platform error vector with SAL.
397  *
398  *  Inputs
399  *      cpev        Corrected Platform Error Vector number
400  *
401  *  Outputs
402  *      None
403  */
404 static void __init
405 ia64_mca_register_cpev (int cpev)
406 {
407         /* Register the CPE interrupt vector with SAL */
408         struct ia64_sal_retval isrv;
409
410         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
411         if (isrv.status) {
412                 printk(KERN_ERR "Failed to register Corrected Platform "
413                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
414                 return;
415         }
416
417         IA64_MCA_DEBUG("%s: corrected platform error "
418                        "vector %#x registered\n", __FUNCTION__, cpev);
419 }
420 #endif /* CONFIG_ACPI */
421
422 /*
423  * ia64_mca_cmc_vector_setup
424  *
425  *  Setup the corrected machine check vector register in the processor.
426  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
427  *  This function is invoked on a per-processor basis.
428  *
429  * Inputs
430  *      None
431  *
432  * Outputs
433  *      None
434  */
435 void __cpuinit
436 ia64_mca_cmc_vector_setup (void)
437 {
438         cmcv_reg_t      cmcv;
439
440         cmcv.cmcv_regval        = 0;
441         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
442         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
443         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
444
445         IA64_MCA_DEBUG("%s: CPU %d corrected "
446                        "machine check vector %#x registered.\n",
447                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
448
449         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
450                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
451 }
452
453 /*
454  * ia64_mca_cmc_vector_disable
455  *
456  *  Mask the corrected machine check vector register in the processor.
457  *  This function is invoked on a per-processor basis.
458  *
459  * Inputs
460  *      dummy(unused)
461  *
462  * Outputs
463  *      None
464  */
465 static void
466 ia64_mca_cmc_vector_disable (void *dummy)
467 {
468         cmcv_reg_t      cmcv;
469
470         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
471
472         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
473         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
474
475         IA64_MCA_DEBUG("%s: CPU %d corrected "
476                        "machine check vector %#x disabled.\n",
477                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
478 }
479
480 /*
481  * ia64_mca_cmc_vector_enable
482  *
483  *  Unmask the corrected machine check vector register in the processor.
484  *  This function is invoked on a per-processor basis.
485  *
486  * Inputs
487  *      dummy(unused)
488  *
489  * Outputs
490  *      None
491  */
492 static void
493 ia64_mca_cmc_vector_enable (void *dummy)
494 {
495         cmcv_reg_t      cmcv;
496
497         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
498
499         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
500         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
501
502         IA64_MCA_DEBUG("%s: CPU %d corrected "
503                        "machine check vector %#x enabled.\n",
504                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
505 }
506
507 /*
508  * ia64_mca_cmc_vector_disable_keventd
509  *
510  * Called via keventd (smp_call_function() is not safe in interrupt context) to
511  * disable the cmc interrupt vector.
512  */
513 static void
514 ia64_mca_cmc_vector_disable_keventd(void *unused)
515 {
516         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
517 }
518
519 /*
520  * ia64_mca_cmc_vector_enable_keventd
521  *
522  * Called via keventd (smp_call_function() is not safe in interrupt context) to
523  * enable the cmc interrupt vector.
524  */
525 static void
526 ia64_mca_cmc_vector_enable_keventd(void *unused)
527 {
528         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
529 }
530
531 /*
532  * ia64_mca_wakeup
533  *
534  *      Send an inter-cpu interrupt to wake-up a particular cpu
535  *      and mark that cpu to be out of rendez.
536  *
537  *  Inputs  :   cpuid
538  *  Outputs :   None
539  */
540 static void
541 ia64_mca_wakeup(int cpu)
542 {
543         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
544         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
545
546 }
547
548 /*
549  * ia64_mca_wakeup_all
550  *
551  *      Wakeup all the cpus which have rendez'ed previously.
552  *
553  *  Inputs  :   None
554  *  Outputs :   None
555  */
556 static void
557 ia64_mca_wakeup_all(void)
558 {
559         int cpu;
560
561         /* Clear the Rendez checkin flag for all cpus */
562         for_each_online_cpu(cpu) {
563                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
564                         ia64_mca_wakeup(cpu);
565         }
566
567 }
568
569 /*
570  * ia64_mca_rendez_interrupt_handler
571  *
572  *      This is handler used to put slave processors into spinloop
573  *      while the monarch processor does the mca handling and later
574  *      wake each slave up once the monarch is done.
575  *
576  *  Inputs  :   None
577  *  Outputs :   None
578  */
579 static irqreturn_t
580 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *regs)
581 {
582         unsigned long flags;
583         int cpu = smp_processor_id();
584         struct ia64_mca_notify_die nd =
585                 { .sos = NULL, .monarch_cpu = &monarch_cpu };
586
587         /* Mask all interrupts */
588         local_irq_save(flags);
589         if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", regs, (long)&nd, 0, 0)
590                         == NOTIFY_STOP)
591                 ia64_mca_spin(__FUNCTION__);
592
593         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
594         /* Register with the SAL monarch that the slave has
595          * reached SAL
596          */
597         ia64_sal_mc_rendez();
598
599         if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", regs, (long)&nd, 0, 0)
600                         == NOTIFY_STOP)
601                 ia64_mca_spin(__FUNCTION__);
602
603         /* Wait for the monarch cpu to exit. */
604         while (monarch_cpu != -1)
605                cpu_relax();     /* spin until monarch leaves */
606
607         if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", regs, (long)&nd, 0, 0)
608                         == NOTIFY_STOP)
609                 ia64_mca_spin(__FUNCTION__);
610
611         /* Enable all interrupts */
612         local_irq_restore(flags);
613         return IRQ_HANDLED;
614 }
615
616 /*
617  * ia64_mca_wakeup_int_handler
618  *
619  *      The interrupt handler for processing the inter-cpu interrupt to the
620  *      slave cpu which was spinning in the rendez loop.
621  *      Since this spinning is done by turning off the interrupts and
622  *      polling on the wakeup-interrupt bit in the IRR, there is
623  *      nothing useful to be done in the handler.
624  *
625  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
626  *      arg             (Interrupt handler specific argument)
627  *      ptregs          (Exception frame at the time of the interrupt)
628  *  Outputs :   None
629  *
630  */
631 static irqreturn_t
632 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
633 {
634         return IRQ_HANDLED;
635 }
636
637 /* Function pointer for extra MCA recovery */
638 int (*ia64_mca_ucmc_extension)
639         (void*,struct ia64_sal_os_state*)
640         = NULL;
641
642 int
643 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
644 {
645         if (ia64_mca_ucmc_extension)
646                 return 1;
647
648         ia64_mca_ucmc_extension = fn;
649         return 0;
650 }
651
652 void
653 ia64_unreg_MCA_extension(void)
654 {
655         if (ia64_mca_ucmc_extension)
656                 ia64_mca_ucmc_extension = NULL;
657 }
658
659 EXPORT_SYMBOL(ia64_reg_MCA_extension);
660 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
661
662
663 static inline void
664 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
665 {
666         u64 fslot, tslot, nat;
667         *tr = *fr;
668         fslot = ((unsigned long)fr >> 3) & 63;
669         tslot = ((unsigned long)tr >> 3) & 63;
670         *tnat &= ~(1UL << tslot);
671         nat = (fnat >> fslot) & 1;
672         *tnat |= (nat << tslot);
673 }
674
675 /* Change the comm field on the MCA/INT task to include the pid that
676  * was interrupted, it makes for easier debugging.  If that pid was 0
677  * (swapper or nested MCA/INIT) then use the start of the previous comm
678  * field suffixed with its cpu.
679  */
680
681 static void
682 ia64_mca_modify_comm(const task_t *previous_current)
683 {
684         char *p, comm[sizeof(current->comm)];
685         if (previous_current->pid)
686                 snprintf(comm, sizeof(comm), "%s %d",
687                         current->comm, previous_current->pid);
688         else {
689                 int l;
690                 if ((p = strchr(previous_current->comm, ' ')))
691                         l = p - previous_current->comm;
692                 else
693                         l = strlen(previous_current->comm);
694                 snprintf(comm, sizeof(comm), "%s %*s %d",
695                         current->comm, l, previous_current->comm,
696                         task_thread_info(previous_current)->cpu);
697         }
698         memcpy(current->comm, comm, sizeof(current->comm));
699 }
700
701 /* On entry to this routine, we are running on the per cpu stack, see
702  * mca_asm.h.  The original stack has not been touched by this event.  Some of
703  * the original stack's registers will be in the RBS on this stack.  This stack
704  * also contains a partial pt_regs and switch_stack, the rest of the data is in
705  * PAL minstate.
706  *
707  * The first thing to do is modify the original stack to look like a blocked
708  * task so we can run backtrace on the original task.  Also mark the per cpu
709  * stack as current to ensure that we use the correct task state, it also means
710  * that we can do backtrace on the MCA/INIT handler code itself.
711  */
712
713 static task_t *
714 ia64_mca_modify_original_stack(struct pt_regs *regs,
715                 const struct switch_stack *sw,
716                 struct ia64_sal_os_state *sos,
717                 const char *type)
718 {
719         char *p;
720         ia64_va va;
721         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
722         const pal_min_state_area_t *ms = sos->pal_min_state;
723         task_t *previous_current;
724         struct pt_regs *old_regs;
725         struct switch_stack *old_sw;
726         unsigned size = sizeof(struct pt_regs) +
727                         sizeof(struct switch_stack) + 16;
728         u64 *old_bspstore, *old_bsp;
729         u64 *new_bspstore, *new_bsp;
730         u64 old_unat, old_rnat, new_rnat, nat;
731         u64 slots, loadrs = regs->loadrs;
732         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
733         u64 ar_bspstore = regs->ar_bspstore;
734         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
735         const u64 *bank;
736         const char *msg;
737         int cpu = smp_processor_id();
738
739         previous_current = curr_task(cpu);
740         set_curr_task(cpu, current);
741         if ((p = strchr(current->comm, ' ')))
742                 *p = '\0';
743
744         /* Best effort attempt to cope with MCA/INIT delivered while in
745          * physical mode.
746          */
747         regs->cr_ipsr = ms->pmsa_ipsr;
748         if (ia64_psr(regs)->dt == 0) {
749                 va.l = r12;
750                 if (va.f.reg == 0) {
751                         va.f.reg = 7;
752                         r12 = va.l;
753                 }
754                 va.l = r13;
755                 if (va.f.reg == 0) {
756                         va.f.reg = 7;
757                         r13 = va.l;
758                 }
759         }
760         if (ia64_psr(regs)->rt == 0) {
761                 va.l = ar_bspstore;
762                 if (va.f.reg == 0) {
763                         va.f.reg = 7;
764                         ar_bspstore = va.l;
765                 }
766                 va.l = ar_bsp;
767                 if (va.f.reg == 0) {
768                         va.f.reg = 7;
769                         ar_bsp = va.l;
770                 }
771         }
772
773         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
774          * have been copied to the old stack, the old stack may fail the
775          * validation tests below.  So ia64_old_stack() must restore the dirty
776          * registers from the new stack.  The old and new bspstore probably
777          * have different alignments, so loadrs calculated on the old bsp
778          * cannot be used to restore from the new bsp.  Calculate a suitable
779          * loadrs for the new stack and save it in the new pt_regs, where
780          * ia64_old_stack() can get it.
781          */
782         old_bspstore = (u64 *)ar_bspstore;
783         old_bsp = (u64 *)ar_bsp;
784         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
785         new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
786         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
787         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
788
789         /* Verify the previous stack state before we change it */
790         if (user_mode(regs)) {
791                 msg = "occurred in user space";
792                 /* previous_current is guaranteed to be valid when the task was
793                  * in user space, so ...
794                  */
795                 ia64_mca_modify_comm(previous_current);
796                 goto no_mod;
797         }
798
799         if (!mca_recover_range(ms->pmsa_iip)) {
800                 if (r13 != sos->prev_IA64_KR_CURRENT) {
801                         msg = "inconsistent previous current and r13";
802                         goto no_mod;
803                 }
804                 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
805                         msg = "inconsistent r12 and r13";
806                         goto no_mod;
807                 }
808                 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
809                         msg = "inconsistent ar.bspstore and r13";
810                         goto no_mod;
811                 }
812                 va.p = old_bspstore;
813                 if (va.f.reg < 5) {
814                         msg = "old_bspstore is in the wrong region";
815                         goto no_mod;
816                 }
817                 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
818                         msg = "inconsistent ar.bsp and r13";
819                         goto no_mod;
820                 }
821                 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
822                 if (ar_bspstore + size > r12) {
823                         msg = "no room for blocked state";
824                         goto no_mod;
825                 }
826         }
827
828         ia64_mca_modify_comm(previous_current);
829
830         /* Make the original task look blocked.  First stack a struct pt_regs,
831          * describing the state at the time of interrupt.  mca_asm.S built a
832          * partial pt_regs, copy it and fill in the blanks using minstate.
833          */
834         p = (char *)r12 - sizeof(*regs);
835         old_regs = (struct pt_regs *)p;
836         memcpy(old_regs, regs, sizeof(*regs));
837         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
838          * pmsa_{xip,xpsr,xfs}
839          */
840         if (ia64_psr(regs)->ic) {
841                 old_regs->cr_iip = ms->pmsa_iip;
842                 old_regs->cr_ipsr = ms->pmsa_ipsr;
843                 old_regs->cr_ifs = ms->pmsa_ifs;
844         } else {
845                 old_regs->cr_iip = ms->pmsa_xip;
846                 old_regs->cr_ipsr = ms->pmsa_xpsr;
847                 old_regs->cr_ifs = ms->pmsa_xfs;
848         }
849         old_regs->pr = ms->pmsa_pr;
850         old_regs->b0 = ms->pmsa_br0;
851         old_regs->loadrs = loadrs;
852         old_regs->ar_rsc = ms->pmsa_rsc;
853         old_unat = old_regs->ar_unat;
854         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
855         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
856         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
857         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
858         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
859         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
860         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
861         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
862         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
863         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
864         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
865         if (ia64_psr(old_regs)->bn)
866                 bank = ms->pmsa_bank1_gr;
867         else
868                 bank = ms->pmsa_bank0_gr;
869         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
870         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
871         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
872         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
873         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
874         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
875         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
876         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
877         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
878         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
879         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
880         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
881         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
882         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
883         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
884         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
885
886         /* Next stack a struct switch_stack.  mca_asm.S built a partial
887          * switch_stack, copy it and fill in the blanks using pt_regs and
888          * minstate.
889          *
890          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
891          * ar.pfs is set to 0.
892          *
893          * unwind.c::unw_unwind() does special processing for interrupt frames.
894          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
895          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
896          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
897          * switch_stack on the original stack so it will unwind correctly when
898          * unwind.c reads pt_regs.
899          *
900          * thread.ksp is updated to point to the synthesized switch_stack.
901          */
902         p -= sizeof(struct switch_stack);
903         old_sw = (struct switch_stack *)p;
904         memcpy(old_sw, sw, sizeof(*sw));
905         old_sw->caller_unat = old_unat;
906         old_sw->ar_fpsr = old_regs->ar_fpsr;
907         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
908         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
909         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
910         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
911         old_sw->b0 = (u64)ia64_leave_kernel;
912         old_sw->b1 = ms->pmsa_br1;
913         old_sw->ar_pfs = 0;
914         old_sw->ar_unat = old_unat;
915         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
916         previous_current->thread.ksp = (u64)p - 16;
917
918         /* Finally copy the original stack's registers back to its RBS.
919          * Registers from ar.bspstore through ar.bsp at the time of the event
920          * are in the current RBS, copy them back to the original stack.  The
921          * copy must be done register by register because the original bspstore
922          * and the current one have different alignments, so the saved RNAT
923          * data occurs at different places.
924          *
925          * mca_asm does cover, so the old_bsp already includes all registers at
926          * the time of MCA/INIT.  It also does flushrs, so all registers before
927          * this function have been written to backing store on the MCA/INIT
928          * stack.
929          */
930         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
931         old_rnat = regs->ar_rnat;
932         while (slots--) {
933                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
934                         new_rnat = ia64_get_rnat(new_bspstore++);
935                 }
936                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
937                         *old_bspstore++ = old_rnat;
938                         old_rnat = 0;
939                 }
940                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
941                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
942                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
943                 *old_bspstore++ = *new_bspstore++;
944         }
945         old_sw->ar_bspstore = (unsigned long)old_bspstore;
946         old_sw->ar_rnat = old_rnat;
947
948         sos->prev_task = previous_current;
949         return previous_current;
950
951 no_mod:
952         printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
953                         smp_processor_id(), type, msg);
954         return previous_current;
955 }
956
957 /* The monarch/slave interaction is based on monarch_cpu and requires that all
958  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
959  * not entered rendezvous yet then wait a bit.  The assumption is that any
960  * slave that has not rendezvoused after a reasonable time is never going to do
961  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
962  * interrupt, as well as cpus that receive the INIT slave event.
963  */
964
965 static void
966 ia64_wait_for_slaves(int monarch, const char *type)
967 {
968         int c, wait = 0, missing = 0;
969         for_each_online_cpu(c) {
970                 if (c == monarch)
971                         continue;
972                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
973                         udelay(1000);           /* short wait first */
974                         wait = 1;
975                         break;
976                 }
977         }
978         if (!wait)
979                 goto all_in;
980         for_each_online_cpu(c) {
981                 if (c == monarch)
982                         continue;
983                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
984                         udelay(5*1000000);      /* wait 5 seconds for slaves (arbitrary) */
985                         if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
986                                 missing = 1;
987                         break;
988                 }
989         }
990         if (!missing)
991                 goto all_in;
992         printk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
993         for_each_online_cpu(c) {
994                 if (c == monarch)
995                         continue;
996                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
997                         printk(" %d", c);
998         }
999         printk("\n");
1000         return;
1001
1002 all_in:
1003         printk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1004         return;
1005 }
1006
1007 /*
1008  * ia64_mca_handler
1009  *
1010  *      This is uncorrectable machine check handler called from OS_MCA
1011  *      dispatch code which is in turn called from SAL_CHECK().
1012  *      This is the place where the core of OS MCA handling is done.
1013  *      Right now the logs are extracted and displayed in a well-defined
1014  *      format. This handler code is supposed to be run only on the
1015  *      monarch processor. Once the monarch is done with MCA handling
1016  *      further MCA logging is enabled by clearing logs.
1017  *      Monarch also has the duty of sending wakeup-IPIs to pull the
1018  *      slave processors out of rendezvous spinloop.
1019  */
1020 void
1021 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1022                  struct ia64_sal_os_state *sos)
1023 {
1024         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
1025                 &sos->proc_state_param;
1026         int recover, cpu = smp_processor_id();
1027         task_t *previous_current;
1028         struct ia64_mca_notify_die nd =
1029                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1030
1031         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1032         console_loglevel = 15;  /* make sure printks make it to console */
1033         printk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d monarch=%ld\n",
1034                 sos->proc_state_param, cpu, sos->monarch);
1035
1036         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1037         monarch_cpu = cpu;
1038         if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0)
1039                         == NOTIFY_STOP)
1040                 ia64_mca_spin(__FUNCTION__);
1041         ia64_wait_for_slaves(cpu, "MCA");
1042
1043         /* Wakeup all the processors which are spinning in the rendezvous loop.
1044          * They will leave SAL, then spin in the OS with interrupts disabled
1045          * until this monarch cpu leaves the MCA handler.  That gets control
1046          * back to the OS so we can backtrace the other cpus, backtrace when
1047          * spinning in SAL does not work.
1048          */
1049         ia64_mca_wakeup_all();
1050         if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0)
1051                         == NOTIFY_STOP)
1052                 ia64_mca_spin(__FUNCTION__);
1053
1054         /* Get the MCA error record and log it */
1055         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1056
1057         /* TLB error is only exist in this SAL error record */
1058         recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
1059         /* other error recovery */
1060            || (ia64_mca_ucmc_extension
1061                 && ia64_mca_ucmc_extension(
1062                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1063                         sos));
1064
1065         if (recover) {
1066                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1067                 rh->severity = sal_log_severity_corrected;
1068                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1069                 sos->os_status = IA64_MCA_CORRECTED;
1070         }
1071         if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover)
1072                         == NOTIFY_STOP)
1073                 ia64_mca_spin(__FUNCTION__);
1074
1075         set_curr_task(cpu, previous_current);
1076         monarch_cpu = -1;
1077 }
1078
1079 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
1080 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
1081
1082 /*
1083  * ia64_mca_cmc_int_handler
1084  *
1085  *  This is corrected machine check interrupt handler.
1086  *      Right now the logs are extracted and displayed in a well-defined
1087  *      format.
1088  *
1089  * Inputs
1090  *      interrupt number
1091  *      client data arg ptr
1092  *      saved registers ptr
1093  *
1094  * Outputs
1095  *      None
1096  */
1097 static irqreturn_t
1098 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
1099 {
1100         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1101         static int              index;
1102         static DEFINE_SPINLOCK(cmc_history_lock);
1103
1104         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1105                        __FUNCTION__, cmc_irq, smp_processor_id());
1106
1107         /* SAL spec states this should run w/ interrupts enabled */
1108         local_irq_enable();
1109
1110         /* Get the CMC error record and log it */
1111         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1112
1113         spin_lock(&cmc_history_lock);
1114         if (!cmc_polling_enabled) {
1115                 int i, count = 1; /* we know 1 happened now */
1116                 unsigned long now = jiffies;
1117
1118                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1119                         if (now - cmc_history[i] <= HZ)
1120                                 count++;
1121                 }
1122
1123                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1124                 if (count >= CMC_HISTORY_LENGTH) {
1125
1126                         cmc_polling_enabled = 1;
1127                         spin_unlock(&cmc_history_lock);
1128                         /* If we're being hit with CMC interrupts, we won't
1129                          * ever execute the schedule_work() below.  Need to
1130                          * disable CMC interrupts on this processor now.
1131                          */
1132                         ia64_mca_cmc_vector_disable(NULL);
1133                         schedule_work(&cmc_disable_work);
1134
1135                         /*
1136                          * Corrected errors will still be corrected, but
1137                          * make sure there's a log somewhere that indicates
1138                          * something is generating more than we can handle.
1139                          */
1140                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1141
1142                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1143
1144                         /* lock already released, get out now */
1145                         return IRQ_HANDLED;
1146                 } else {
1147                         cmc_history[index++] = now;
1148                         if (index == CMC_HISTORY_LENGTH)
1149                                 index = 0;
1150                 }
1151         }
1152         spin_unlock(&cmc_history_lock);
1153         return IRQ_HANDLED;
1154 }
1155
1156 /*
1157  *  ia64_mca_cmc_int_caller
1158  *
1159  *      Triggered by sw interrupt from CMC polling routine.  Calls
1160  *      real interrupt handler and either triggers a sw interrupt
1161  *      on the next cpu or does cleanup at the end.
1162  *
1163  * Inputs
1164  *      interrupt number
1165  *      client data arg ptr
1166  *      saved registers ptr
1167  * Outputs
1168  *      handled
1169  */
1170 static irqreturn_t
1171 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1172 {
1173         static int start_count = -1;
1174         unsigned int cpuid;
1175
1176         cpuid = smp_processor_id();
1177
1178         /* If first cpu, update count */
1179         if (start_count == -1)
1180                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1181
1182         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1183
1184         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1185
1186         if (cpuid < NR_CPUS) {
1187                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1188         } else {
1189                 /* If no log record, switch out of polling mode */
1190                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1191
1192                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1193                         schedule_work(&cmc_enable_work);
1194                         cmc_polling_enabled = 0;
1195
1196                 } else {
1197
1198                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1199                 }
1200
1201                 start_count = -1;
1202         }
1203
1204         return IRQ_HANDLED;
1205 }
1206
1207 /*
1208  *  ia64_mca_cmc_poll
1209  *
1210  *      Poll for Corrected Machine Checks (CMCs)
1211  *
1212  * Inputs   :   dummy(unused)
1213  * Outputs  :   None
1214  *
1215  */
1216 static void
1217 ia64_mca_cmc_poll (unsigned long dummy)
1218 {
1219         /* Trigger a CMC interrupt cascade  */
1220         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1221 }
1222
1223 /*
1224  *  ia64_mca_cpe_int_caller
1225  *
1226  *      Triggered by sw interrupt from CPE polling routine.  Calls
1227  *      real interrupt handler and either triggers a sw interrupt
1228  *      on the next cpu or does cleanup at the end.
1229  *
1230  * Inputs
1231  *      interrupt number
1232  *      client data arg ptr
1233  *      saved registers ptr
1234  * Outputs
1235  *      handled
1236  */
1237 #ifdef CONFIG_ACPI
1238
1239 static irqreturn_t
1240 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1241 {
1242         static int start_count = -1;
1243         static int poll_time = MIN_CPE_POLL_INTERVAL;
1244         unsigned int cpuid;
1245
1246         cpuid = smp_processor_id();
1247
1248         /* If first cpu, update count */
1249         if (start_count == -1)
1250                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1251
1252         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1253
1254         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1255
1256         if (cpuid < NR_CPUS) {
1257                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1258         } else {
1259                 /*
1260                  * If a log was recorded, increase our polling frequency,
1261                  * otherwise, backoff or return to interrupt mode.
1262                  */
1263                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1264                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1265                 } else if (cpe_vector < 0) {
1266                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1267                 } else {
1268                         poll_time = MIN_CPE_POLL_INTERVAL;
1269
1270                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1271                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1272                         cpe_poll_enabled = 0;
1273                 }
1274
1275                 if (cpe_poll_enabled)
1276                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1277                 start_count = -1;
1278         }
1279
1280         return IRQ_HANDLED;
1281 }
1282
1283 /*
1284  *  ia64_mca_cpe_poll
1285  *
1286  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1287  *      on first cpu, from there it will trickle through all the cpus.
1288  *
1289  * Inputs   :   dummy(unused)
1290  * Outputs  :   None
1291  *
1292  */
1293 static void
1294 ia64_mca_cpe_poll (unsigned long dummy)
1295 {
1296         /* Trigger a CPE interrupt cascade  */
1297         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1298 }
1299
1300 #endif /* CONFIG_ACPI */
1301
1302 static int
1303 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1304 {
1305         int c;
1306         struct task_struct *g, *t;
1307         if (val != DIE_INIT_MONARCH_PROCESS)
1308                 return NOTIFY_DONE;
1309         printk(KERN_ERR "Processes interrupted by INIT -");
1310         for_each_online_cpu(c) {
1311                 struct ia64_sal_os_state *s;
1312                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1313                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1314                 g = s->prev_task;
1315                 if (g) {
1316                         if (g->pid)
1317                                 printk(" %d", g->pid);
1318                         else
1319                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1320                 }
1321         }
1322         printk("\n\n");
1323         if (read_trylock(&tasklist_lock)) {
1324                 do_each_thread (g, t) {
1325                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1326                         show_stack(t, NULL);
1327                 } while_each_thread (g, t);
1328                 read_unlock(&tasklist_lock);
1329         }
1330         return NOTIFY_DONE;
1331 }
1332
1333 /*
1334  * C portion of the OS INIT handler
1335  *
1336  * Called from ia64_os_init_dispatch
1337  *
1338  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1339  * this event.  This code is used for both monarch and slave INIT events, see
1340  * sos->monarch.
1341  *
1342  * All INIT events switch to the INIT stack and change the previous process to
1343  * blocked status.  If one of the INIT events is the monarch then we are
1344  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1345  * the processes.  The slave INIT events all spin until the monarch cpu
1346  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1347  * process is the monarch.
1348  */
1349
1350 void
1351 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1352                   struct ia64_sal_os_state *sos)
1353 {
1354         static atomic_t slaves;
1355         static atomic_t monarchs;
1356         task_t *previous_current;
1357         int cpu = smp_processor_id();
1358         struct ia64_mca_notify_die nd =
1359                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1360
1361         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1362         console_loglevel = 15;  /* make sure printks make it to console */
1363
1364         (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0);
1365
1366         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1367                 sos->proc_state_param, cpu, sos->monarch);
1368         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1369
1370         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1371         sos->os_status = IA64_INIT_RESUME;
1372
1373         /* FIXME: Workaround for broken proms that drive all INIT events as
1374          * slaves.  The last slave that enters is promoted to be a monarch.
1375          * Remove this code in September 2006, that gives platforms a year to
1376          * fix their proms and get their customers updated.
1377          */
1378         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1379                 printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1380                        __FUNCTION__, cpu);
1381                 atomic_dec(&slaves);
1382                 sos->monarch = 1;
1383         }
1384
1385         /* FIXME: Workaround for broken proms that drive all INIT events as
1386          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1387          * Remove this code in September 2006, that gives platforms a year to
1388          * fix their proms and get their customers updated.
1389          */
1390         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1391                 printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1392                                __FUNCTION__, cpu);
1393                 atomic_dec(&monarchs);
1394                 sos->monarch = 0;
1395         }
1396
1397         if (!sos->monarch) {
1398                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1399                 while (monarch_cpu == -1)
1400                        cpu_relax();     /* spin until monarch enters */
1401                 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0)
1402                                 == NOTIFY_STOP)
1403                         ia64_mca_spin(__FUNCTION__);
1404                 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1405                                 == NOTIFY_STOP)
1406                         ia64_mca_spin(__FUNCTION__);
1407                 while (monarch_cpu != -1)
1408                        cpu_relax();     /* spin until monarch leaves */
1409                 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1410                                 == NOTIFY_STOP)
1411                         ia64_mca_spin(__FUNCTION__);
1412                 printk("Slave on cpu %d returning to normal service.\n", cpu);
1413                 set_curr_task(cpu, previous_current);
1414                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1415                 atomic_dec(&slaves);
1416                 return;
1417         }
1418
1419         monarch_cpu = cpu;
1420         if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0)
1421                         == NOTIFY_STOP)
1422                 ia64_mca_spin(__FUNCTION__);
1423
1424         /*
1425          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1426          * generated via the BMC's command-line interface, but since the console is on the
1427          * same serial line, the user will need some time to switch out of the BMC before
1428          * the dump begins.
1429          */
1430         printk("Delaying for 5 seconds...\n");
1431         udelay(5*1000000);
1432         ia64_wait_for_slaves(cpu, "INIT");
1433         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1434          * to default_monarch_init_process() above and just print all the
1435          * tasks.
1436          */
1437         if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1438                         == NOTIFY_STOP)
1439                 ia64_mca_spin(__FUNCTION__);
1440         if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1441                         == NOTIFY_STOP)
1442                 ia64_mca_spin(__FUNCTION__);
1443         printk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1444         atomic_dec(&monarchs);
1445         set_curr_task(cpu, previous_current);
1446         monarch_cpu = -1;
1447         return;
1448 }
1449
1450 static int __init
1451 ia64_mca_disable_cpe_polling(char *str)
1452 {
1453         cpe_poll_enabled = 0;
1454         return 1;
1455 }
1456
1457 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1458
1459 static struct irqaction cmci_irqaction = {
1460         .handler =      ia64_mca_cmc_int_handler,
1461         .flags =        SA_INTERRUPT,
1462         .name =         "cmc_hndlr"
1463 };
1464
1465 static struct irqaction cmcp_irqaction = {
1466         .handler =      ia64_mca_cmc_int_caller,
1467         .flags =        SA_INTERRUPT,
1468         .name =         "cmc_poll"
1469 };
1470
1471 static struct irqaction mca_rdzv_irqaction = {
1472         .handler =      ia64_mca_rendez_int_handler,
1473         .flags =        SA_INTERRUPT,
1474         .name =         "mca_rdzv"
1475 };
1476
1477 static struct irqaction mca_wkup_irqaction = {
1478         .handler =      ia64_mca_wakeup_int_handler,
1479         .flags =        SA_INTERRUPT,
1480         .name =         "mca_wkup"
1481 };
1482
1483 #ifdef CONFIG_ACPI
1484 static struct irqaction mca_cpe_irqaction = {
1485         .handler =      ia64_mca_cpe_int_handler,
1486         .flags =        SA_INTERRUPT,
1487         .name =         "cpe_hndlr"
1488 };
1489
1490 static struct irqaction mca_cpep_irqaction = {
1491         .handler =      ia64_mca_cpe_int_caller,
1492         .flags =        SA_INTERRUPT,
1493         .name =         "cpe_poll"
1494 };
1495 #endif /* CONFIG_ACPI */
1496
1497 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1498  * these stacks can never sleep, they cannot return from the kernel to user
1499  * space, they do not appear in a normal ps listing.  So there is no need to
1500  * format most of the fields.
1501  */
1502
1503 static void __cpuinit
1504 format_mca_init_stack(void *mca_data, unsigned long offset,
1505                 const char *type, int cpu)
1506 {
1507         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1508         struct thread_info *ti;
1509         memset(p, 0, KERNEL_STACK_SIZE);
1510         ti = task_thread_info(p);
1511         ti->flags = _TIF_MCA_INIT;
1512         ti->preempt_count = 1;
1513         ti->task = p;
1514         ti->cpu = cpu;
1515         p->thread_info = ti;
1516         p->state = TASK_UNINTERRUPTIBLE;
1517         cpu_set(cpu, p->cpus_allowed);
1518         INIT_LIST_HEAD(&p->tasks);
1519         p->parent = p->real_parent = p->group_leader = p;
1520         INIT_LIST_HEAD(&p->children);
1521         INIT_LIST_HEAD(&p->sibling);
1522         strncpy(p->comm, type, sizeof(p->comm)-1);
1523 }
1524
1525 /* Do per-CPU MCA-related initialization.  */
1526
1527 void __cpuinit
1528 ia64_mca_cpu_init(void *cpu_data)
1529 {
1530         void *pal_vaddr;
1531         static int first_time = 1;
1532
1533         if (first_time) {
1534                 void *mca_data;
1535                 int cpu;
1536
1537                 first_time = 0;
1538                 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1539                                          * NR_CPUS + KERNEL_STACK_SIZE);
1540                 mca_data = (void *)(((unsigned long)mca_data +
1541                                         KERNEL_STACK_SIZE - 1) &
1542                                 (-KERNEL_STACK_SIZE));
1543                 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1544                         format_mca_init_stack(mca_data,
1545                                         offsetof(struct ia64_mca_cpu, mca_stack),
1546                                         "MCA", cpu);
1547                         format_mca_init_stack(mca_data,
1548                                         offsetof(struct ia64_mca_cpu, init_stack),
1549                                         "INIT", cpu);
1550                         __per_cpu_mca[cpu] = __pa(mca_data);
1551                         mca_data += sizeof(struct ia64_mca_cpu);
1552                 }
1553         }
1554
1555         /*
1556          * The MCA info structure was allocated earlier and its
1557          * physical address saved in __per_cpu_mca[cpu].  Copy that
1558          * address * to ia64_mca_data so we can access it as a per-CPU
1559          * variable.
1560          */
1561         __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1562
1563         /*
1564          * Stash away a copy of the PTE needed to map the per-CPU page.
1565          * We may need it during MCA recovery.
1566          */
1567         __get_cpu_var(ia64_mca_per_cpu_pte) =
1568                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1569
1570         /*
1571          * Also, stash away a copy of the PAL address and the PTE
1572          * needed to map it.
1573          */
1574         pal_vaddr = efi_get_pal_addr();
1575         if (!pal_vaddr)
1576                 return;
1577         __get_cpu_var(ia64_mca_pal_base) =
1578                 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1579         __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1580                                                               PAGE_KERNEL));
1581 }
1582
1583 /*
1584  * ia64_mca_init
1585  *
1586  *  Do all the system level mca specific initialization.
1587  *
1588  *      1. Register spinloop and wakeup request interrupt vectors
1589  *
1590  *      2. Register OS_MCA handler entry point
1591  *
1592  *      3. Register OS_INIT handler entry point
1593  *
1594  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1595  *
1596  *  Note that this initialization is done very early before some kernel
1597  *  services are available.
1598  *
1599  *  Inputs  :   None
1600  *
1601  *  Outputs :   None
1602  */
1603 void __init
1604 ia64_mca_init(void)
1605 {
1606         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1607         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1608         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1609         int i;
1610         s64 rc;
1611         struct ia64_sal_retval isrv;
1612         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1613         static struct notifier_block default_init_monarch_nb = {
1614                 .notifier_call = default_monarch_init_process,
1615                 .priority = 0/* we need to notified last */
1616         };
1617
1618         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1619
1620         /* Clear the Rendez checkin flag for all cpus */
1621         for(i = 0 ; i < NR_CPUS; i++)
1622                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1623
1624         /*
1625          * Register the rendezvous spinloop and wakeup mechanism with SAL
1626          */
1627
1628         /* Register the rendezvous interrupt vector with SAL */
1629         while (1) {
1630                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1631                                               SAL_MC_PARAM_MECHANISM_INT,
1632                                               IA64_MCA_RENDEZ_VECTOR,
1633                                               timeout,
1634                                               SAL_MC_PARAM_RZ_ALWAYS);
1635                 rc = isrv.status;
1636                 if (rc == 0)
1637                         break;
1638                 if (rc == -2) {
1639                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1640                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1641                         timeout = isrv.v0;
1642                         (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0);
1643                         continue;
1644                 }
1645                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1646                        "with SAL (status %ld)\n", rc);
1647                 return;
1648         }
1649
1650         /* Register the wakeup interrupt vector with SAL */
1651         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1652                                       SAL_MC_PARAM_MECHANISM_INT,
1653                                       IA64_MCA_WAKEUP_VECTOR,
1654                                       0, 0);
1655         rc = isrv.status;
1656         if (rc) {
1657                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1658                        "(status %ld)\n", rc);
1659                 return;
1660         }
1661
1662         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1663
1664         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1665         /*
1666          * XXX - disable SAL checksum by setting size to 0; should be
1667          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1668          */
1669         ia64_mc_info.imi_mca_handler_size       = 0;
1670
1671         /* Register the os mca handler with SAL */
1672         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1673                                        ia64_mc_info.imi_mca_handler,
1674                                        ia64_tpa(mca_hldlr_ptr->gp),
1675                                        ia64_mc_info.imi_mca_handler_size,
1676                                        0, 0, 0)))
1677         {
1678                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1679                        "(status %ld)\n", rc);
1680                 return;
1681         }
1682
1683         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1684                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1685
1686         /*
1687          * XXX - disable SAL checksum by setting size to 0, should be
1688          * size of the actual init handler in mca_asm.S.
1689          */
1690         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
1691         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1692         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
1693         ia64_mc_info.imi_slave_init_handler_size        = 0;
1694
1695         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1696                        ia64_mc_info.imi_monarch_init_handler);
1697
1698         /* Register the os init handler with SAL */
1699         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1700                                        ia64_mc_info.imi_monarch_init_handler,
1701                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1702                                        ia64_mc_info.imi_monarch_init_handler_size,
1703                                        ia64_mc_info.imi_slave_init_handler,
1704                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1705                                        ia64_mc_info.imi_slave_init_handler_size)))
1706         {
1707                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1708                        "(status %ld)\n", rc);
1709                 return;
1710         }
1711         if (register_die_notifier(&default_init_monarch_nb)) {
1712                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
1713                 return;
1714         }
1715
1716         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1717
1718         /*
1719          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1720          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1721          */
1722         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1723         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1724         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1725
1726         /* Setup the MCA rendezvous interrupt vector */
1727         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1728
1729         /* Setup the MCA wakeup interrupt vector */
1730         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1731
1732 #ifdef CONFIG_ACPI
1733         /* Setup the CPEI/P handler */
1734         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1735 #endif
1736
1737         /* Initialize the areas set aside by the OS to buffer the
1738          * platform/processor error states for MCA/INIT/CMC
1739          * handling.
1740          */
1741         ia64_log_init(SAL_INFO_TYPE_MCA);
1742         ia64_log_init(SAL_INFO_TYPE_INIT);
1743         ia64_log_init(SAL_INFO_TYPE_CMC);
1744         ia64_log_init(SAL_INFO_TYPE_CPE);
1745
1746         mca_init = 1;
1747         printk(KERN_INFO "MCA related initialization done\n");
1748 }
1749
1750 /*
1751  * ia64_mca_late_init
1752  *
1753  *      Opportunity to setup things that require initialization later
1754  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1755  *      platform doesn't support an interrupt driven mechanism.
1756  *
1757  *  Inputs  :   None
1758  *  Outputs :   Status
1759  */
1760 static int __init
1761 ia64_mca_late_init(void)
1762 {
1763         if (!mca_init)
1764                 return 0;
1765
1766         /* Setup the CMCI/P vector and handler */
1767         init_timer(&cmc_poll_timer);
1768         cmc_poll_timer.function = ia64_mca_cmc_poll;
1769
1770         /* Unmask/enable the vector */
1771         cmc_polling_enabled = 0;
1772         schedule_work(&cmc_enable_work);
1773
1774         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1775
1776 #ifdef CONFIG_ACPI
1777         /* Setup the CPEI/P vector and handler */
1778         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1779         init_timer(&cpe_poll_timer);
1780         cpe_poll_timer.function = ia64_mca_cpe_poll;
1781
1782         {
1783                 irq_desc_t *desc;
1784                 unsigned int irq;
1785
1786                 if (cpe_vector >= 0) {
1787                         /* If platform supports CPEI, enable the irq. */
1788                         cpe_poll_enabled = 0;
1789                         for (irq = 0; irq < NR_IRQS; ++irq)
1790                                 if (irq_to_vector(irq) == cpe_vector) {
1791                                         desc = irq_desc + irq;
1792                                         desc->status |= IRQ_PER_CPU;
1793                                         setup_irq(irq, &mca_cpe_irqaction);
1794                                         ia64_cpe_irq = irq;
1795                                 }
1796                         ia64_mca_register_cpev(cpe_vector);
1797                         IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1798                 } else {
1799                         /* If platform doesn't support CPEI, get the timer going. */
1800                         if (cpe_poll_enabled) {
1801                                 ia64_mca_cpe_poll(0UL);
1802                                 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1803                         }
1804                 }
1805         }
1806 #endif
1807
1808         return 0;
1809 }
1810
1811 device_initcall(ia64_mca_late_init);