[PATCH] i386 CPU hotplug
[linux-2.6.git] / arch / i386 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/sysdev.h>
36 #include <asm/io.h>
37 #include <asm/smp.h>
38 #include <asm/desc.h>
39 #include <asm/timer.h>
40
41 #include <mach_apic.h>
42
43 #include "io_ports.h"
44
45 int (*ioapic_renumber_irq)(int ioapic, int irq);
46 atomic_t irq_mis_count;
47
48 static DEFINE_SPINLOCK(ioapic_lock);
49
50 /*
51  *      Is the SiS APIC rmw bug present ?
52  *      -1 = don't know, 0 = no, 1 = yes
53  */
54 int sis_apic_bug = -1;
55
56 /*
57  * # of IRQ routing registers
58  */
59 int nr_ioapic_registers[MAX_IO_APICS];
60
61 /*
62  * Rough estimation of how many shared IRQs there are, can
63  * be changed anytime.
64  */
65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
67
68 /*
69  * This is performance-critical, we want to do it O(1)
70  *
71  * the indexing order of this array favors 1:1 mappings
72  * between pins and IRQs.
73  */
74
75 static struct irq_pin_list {
76         int apic, pin, next;
77 } irq_2_pin[PIN_MAP_SIZE];
78
79 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
80 #ifdef CONFIG_PCI_MSI
81 #define vector_to_irq(vector)   \
82         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
83 #else
84 #define vector_to_irq(vector)   (vector)
85 #endif
86
87 /*
88  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
89  * shared ISA-space IRQs, so we have to support them. We are super
90  * fast in the common case, and fast for shared ISA-space IRQs.
91  */
92 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
93 {
94         static int first_free_entry = NR_IRQS;
95         struct irq_pin_list *entry = irq_2_pin + irq;
96
97         while (entry->next)
98                 entry = irq_2_pin + entry->next;
99
100         if (entry->pin != -1) {
101                 entry->next = first_free_entry;
102                 entry = irq_2_pin + entry->next;
103                 if (++first_free_entry >= PIN_MAP_SIZE)
104                         panic("io_apic.c: whoops");
105         }
106         entry->apic = apic;
107         entry->pin = pin;
108 }
109
110 /*
111  * Reroute an IRQ to a different pin.
112  */
113 static void __init replace_pin_at_irq(unsigned int irq,
114                                       int oldapic, int oldpin,
115                                       int newapic, int newpin)
116 {
117         struct irq_pin_list *entry = irq_2_pin + irq;
118
119         while (1) {
120                 if (entry->apic == oldapic && entry->pin == oldpin) {
121                         entry->apic = newapic;
122                         entry->pin = newpin;
123                 }
124                 if (!entry->next)
125                         break;
126                 entry = irq_2_pin + entry->next;
127         }
128 }
129
130 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
131 {
132         struct irq_pin_list *entry = irq_2_pin + irq;
133         unsigned int pin, reg;
134
135         for (;;) {
136                 pin = entry->pin;
137                 if (pin == -1)
138                         break;
139                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
140                 reg &= ~disable;
141                 reg |= enable;
142                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
143                 if (!entry->next)
144                         break;
145                 entry = irq_2_pin + entry->next;
146         }
147 }
148
149 /* mask = 1 */
150 static void __mask_IO_APIC_irq (unsigned int irq)
151 {
152         __modify_IO_APIC_irq(irq, 0x00010000, 0);
153 }
154
155 /* mask = 0 */
156 static void __unmask_IO_APIC_irq (unsigned int irq)
157 {
158         __modify_IO_APIC_irq(irq, 0, 0x00010000);
159 }
160
161 /* mask = 1, trigger = 0 */
162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
163 {
164         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
165 }
166
167 /* mask = 0, trigger = 1 */
168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
169 {
170         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
171 }
172
173 static void mask_IO_APIC_irq (unsigned int irq)
174 {
175         unsigned long flags;
176
177         spin_lock_irqsave(&ioapic_lock, flags);
178         __mask_IO_APIC_irq(irq);
179         spin_unlock_irqrestore(&ioapic_lock, flags);
180 }
181
182 static void unmask_IO_APIC_irq (unsigned int irq)
183 {
184         unsigned long flags;
185
186         spin_lock_irqsave(&ioapic_lock, flags);
187         __unmask_IO_APIC_irq(irq);
188         spin_unlock_irqrestore(&ioapic_lock, flags);
189 }
190
191 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
192 {
193         struct IO_APIC_route_entry entry;
194         unsigned long flags;
195         
196         /* Check delivery_mode to be sure we're not clearing an SMI pin */
197         spin_lock_irqsave(&ioapic_lock, flags);
198         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
199         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
200         spin_unlock_irqrestore(&ioapic_lock, flags);
201         if (entry.delivery_mode == dest_SMI)
202                 return;
203
204         /*
205          * Disable it in the IO-APIC irq-routing table:
206          */
207         memset(&entry, 0, sizeof(entry));
208         entry.mask = 1;
209         spin_lock_irqsave(&ioapic_lock, flags);
210         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
211         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
212         spin_unlock_irqrestore(&ioapic_lock, flags);
213 }
214
215 static void clear_IO_APIC (void)
216 {
217         int apic, pin;
218
219         for (apic = 0; apic < nr_ioapics; apic++)
220                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
221                         clear_IO_APIC_pin(apic, pin);
222 }
223
224 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
225 {
226         unsigned long flags;
227         int pin;
228         struct irq_pin_list *entry = irq_2_pin + irq;
229         unsigned int apicid_value;
230         
231         apicid_value = cpu_mask_to_apicid(cpumask);
232         /* Prepare to do the io_apic_write */
233         apicid_value = apicid_value << 24;
234         spin_lock_irqsave(&ioapic_lock, flags);
235         for (;;) {
236                 pin = entry->pin;
237                 if (pin == -1)
238                         break;
239                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
240                 if (!entry->next)
241                         break;
242                 entry = irq_2_pin + entry->next;
243         }
244         spin_unlock_irqrestore(&ioapic_lock, flags);
245 }
246
247 #if defined(CONFIG_IRQBALANCE)
248 # include <asm/processor.h>     /* kernel_thread() */
249 # include <linux/kernel_stat.h> /* kstat */
250 # include <linux/slab.h>                /* kmalloc() */
251 # include <linux/timer.h>       /* time_after() */
252  
253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
254 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
255 #  define Dprintk(x...) do { TDprintk(x); } while (0)
256 # else
257 #  define TDprintk(x...) 
258 #  define Dprintk(x...) 
259 # endif
260
261 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
262
263 #define IRQBALANCE_CHECK_ARCH -999
264 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
265 static int physical_balance = 0;
266
267 static struct irq_cpu_info {
268         unsigned long * last_irq;
269         unsigned long * irq_delta;
270         unsigned long irq;
271 } irq_cpu_data[NR_CPUS];
272
273 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
274 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
275 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
276
277 #define IDLE_ENOUGH(cpu,now) \
278         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
279
280 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
281
282 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
283
284 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
285 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
286 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
287 #define BALANCED_IRQ_LESS_DELTA         (HZ)
288
289 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
290
291 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
292                         unsigned long now, int direction)
293 {
294         int search_idle = 1;
295         int cpu = curr_cpu;
296
297         goto inside;
298
299         do {
300                 if (unlikely(cpu == curr_cpu))
301                         search_idle = 0;
302 inside:
303                 if (direction == 1) {
304                         cpu++;
305                         if (cpu >= NR_CPUS)
306                                 cpu = 0;
307                 } else {
308                         cpu--;
309                         if (cpu == -1)
310                                 cpu = NR_CPUS-1;
311                 }
312         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
313                         (search_idle && !IDLE_ENOUGH(cpu,now)));
314
315         return cpu;
316 }
317
318 static inline void balance_irq(int cpu, int irq)
319 {
320         unsigned long now = jiffies;
321         cpumask_t allowed_mask;
322         unsigned int new_cpu;
323                 
324         if (irqbalance_disabled)
325                 return; 
326
327         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
328         new_cpu = move(cpu, allowed_mask, now, 1);
329         if (cpu != new_cpu) {
330                 irq_desc_t *desc = irq_desc + irq;
331                 unsigned long flags;
332
333                 spin_lock_irqsave(&desc->lock, flags);
334                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
335                 spin_unlock_irqrestore(&desc->lock, flags);
336         }
337 }
338
339 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
340 {
341         int i, j;
342         Dprintk("Rotating IRQs among CPUs.\n");
343         for (i = 0; i < NR_CPUS; i++) {
344                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
345                         if (!irq_desc[j].action)
346                                 continue;
347                         /* Is it a significant load ?  */
348                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
349                                                 useful_load_threshold)
350                                 continue;
351                         balance_irq(i, j);
352                 }
353         }
354         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
355                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
356         return;
357 }
358
359 static void do_irq_balance(void)
360 {
361         int i, j;
362         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
363         unsigned long move_this_load = 0;
364         int max_loaded = 0, min_loaded = 0;
365         int load;
366         unsigned long useful_load_threshold = balanced_irq_interval + 10;
367         int selected_irq;
368         int tmp_loaded, first_attempt = 1;
369         unsigned long tmp_cpu_irq;
370         unsigned long imbalance = 0;
371         cpumask_t allowed_mask, target_cpu_mask, tmp;
372
373         for (i = 0; i < NR_CPUS; i++) {
374                 int package_index;
375                 CPU_IRQ(i) = 0;
376                 if (!cpu_online(i))
377                         continue;
378                 package_index = CPU_TO_PACKAGEINDEX(i);
379                 for (j = 0; j < NR_IRQS; j++) {
380                         unsigned long value_now, delta;
381                         /* Is this an active IRQ? */
382                         if (!irq_desc[j].action)
383                                 continue;
384                         if ( package_index == i )
385                                 IRQ_DELTA(package_index,j) = 0;
386                         /* Determine the total count per processor per IRQ */
387                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
388
389                         /* Determine the activity per processor per IRQ */
390                         delta = value_now - LAST_CPU_IRQ(i,j);
391
392                         /* Update last_cpu_irq[][] for the next time */
393                         LAST_CPU_IRQ(i,j) = value_now;
394
395                         /* Ignore IRQs whose rate is less than the clock */
396                         if (delta < useful_load_threshold)
397                                 continue;
398                         /* update the load for the processor or package total */
399                         IRQ_DELTA(package_index,j) += delta;
400
401                         /* Keep track of the higher numbered sibling as well */
402                         if (i != package_index)
403                                 CPU_IRQ(i) += delta;
404                         /*
405                          * We have sibling A and sibling B in the package
406                          *
407                          * cpu_irq[A] = load for cpu A + load for cpu B
408                          * cpu_irq[B] = load for cpu B
409                          */
410                         CPU_IRQ(package_index) += delta;
411                 }
412         }
413         /* Find the least loaded processor package */
414         for (i = 0; i < NR_CPUS; i++) {
415                 if (!cpu_online(i))
416                         continue;
417                 if (i != CPU_TO_PACKAGEINDEX(i))
418                         continue;
419                 if (min_cpu_irq > CPU_IRQ(i)) {
420                         min_cpu_irq = CPU_IRQ(i);
421                         min_loaded = i;
422                 }
423         }
424         max_cpu_irq = ULONG_MAX;
425
426 tryanothercpu:
427         /* Look for heaviest loaded processor.
428          * We may come back to get the next heaviest loaded processor.
429          * Skip processors with trivial loads.
430          */
431         tmp_cpu_irq = 0;
432         tmp_loaded = -1;
433         for (i = 0; i < NR_CPUS; i++) {
434                 if (!cpu_online(i))
435                         continue;
436                 if (i != CPU_TO_PACKAGEINDEX(i))
437                         continue;
438                 if (max_cpu_irq <= CPU_IRQ(i)) 
439                         continue;
440                 if (tmp_cpu_irq < CPU_IRQ(i)) {
441                         tmp_cpu_irq = CPU_IRQ(i);
442                         tmp_loaded = i;
443                 }
444         }
445
446         if (tmp_loaded == -1) {
447          /* In the case of small number of heavy interrupt sources, 
448           * loading some of the cpus too much. We use Ingo's original 
449           * approach to rotate them around.
450           */
451                 if (!first_attempt && imbalance >= useful_load_threshold) {
452                         rotate_irqs_among_cpus(useful_load_threshold);
453                         return;
454                 }
455                 goto not_worth_the_effort;
456         }
457         
458         first_attempt = 0;              /* heaviest search */
459         max_cpu_irq = tmp_cpu_irq;      /* load */
460         max_loaded = tmp_loaded;        /* processor */
461         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
462         
463         Dprintk("max_loaded cpu = %d\n", max_loaded);
464         Dprintk("min_loaded cpu = %d\n", min_loaded);
465         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
466         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
467         Dprintk("load imbalance = %lu\n", imbalance);
468
469         /* if imbalance is less than approx 10% of max load, then
470          * observe diminishing returns action. - quit
471          */
472         if (imbalance < (max_cpu_irq >> 3)) {
473                 Dprintk("Imbalance too trivial\n");
474                 goto not_worth_the_effort;
475         }
476
477 tryanotherirq:
478         /* if we select an IRQ to move that can't go where we want, then
479          * see if there is another one to try.
480          */
481         move_this_load = 0;
482         selected_irq = -1;
483         for (j = 0; j < NR_IRQS; j++) {
484                 /* Is this an active IRQ? */
485                 if (!irq_desc[j].action)
486                         continue;
487                 if (imbalance <= IRQ_DELTA(max_loaded,j))
488                         continue;
489                 /* Try to find the IRQ that is closest to the imbalance
490                  * without going over.
491                  */
492                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
493                         move_this_load = IRQ_DELTA(max_loaded,j);
494                         selected_irq = j;
495                 }
496         }
497         if (selected_irq == -1) {
498                 goto tryanothercpu;
499         }
500
501         imbalance = move_this_load;
502         
503         /* For physical_balance case, we accumlated both load
504          * values in the one of the siblings cpu_irq[],
505          * to use the same code for physical and logical processors
506          * as much as possible. 
507          *
508          * NOTE: the cpu_irq[] array holds the sum of the load for
509          * sibling A and sibling B in the slot for the lowest numbered
510          * sibling (A), _AND_ the load for sibling B in the slot for
511          * the higher numbered sibling.
512          *
513          * We seek the least loaded sibling by making the comparison
514          * (A+B)/2 vs B
515          */
516         load = CPU_IRQ(min_loaded) >> 1;
517         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
518                 if (load > CPU_IRQ(j)) {
519                         /* This won't change cpu_sibling_map[min_loaded] */
520                         load = CPU_IRQ(j);
521                         min_loaded = j;
522                 }
523         }
524
525         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
526         target_cpu_mask = cpumask_of_cpu(min_loaded);
527         cpus_and(tmp, target_cpu_mask, allowed_mask);
528
529         if (!cpus_empty(tmp)) {
530                 irq_desc_t *desc = irq_desc + selected_irq;
531                 unsigned long flags;
532
533                 Dprintk("irq = %d moved to cpu = %d\n",
534                                 selected_irq, min_loaded);
535                 /* mark for change destination */
536                 spin_lock_irqsave(&desc->lock, flags);
537                 pending_irq_balance_cpumask[selected_irq] =
538                                         cpumask_of_cpu(min_loaded);
539                 spin_unlock_irqrestore(&desc->lock, flags);
540                 /* Since we made a change, come back sooner to 
541                  * check for more variation.
542                  */
543                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
544                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
545                 return;
546         }
547         goto tryanotherirq;
548
549 not_worth_the_effort:
550         /*
551          * if we did not find an IRQ to move, then adjust the time interval
552          * upward
553          */
554         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
555                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
556         Dprintk("IRQ worth rotating not found\n");
557         return;
558 }
559
560 static int balanced_irq(void *unused)
561 {
562         int i;
563         unsigned long prev_balance_time = jiffies;
564         long time_remaining = balanced_irq_interval;
565
566         daemonize("kirqd");
567         
568         /* push everything to CPU 0 to give us a starting point.  */
569         for (i = 0 ; i < NR_IRQS ; i++) {
570                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
571         }
572
573         for ( ; ; ) {
574                 set_current_state(TASK_INTERRUPTIBLE);
575                 time_remaining = schedule_timeout(time_remaining);
576                 try_to_freeze(PF_FREEZE);
577                 if (time_after(jiffies,
578                                 prev_balance_time+balanced_irq_interval)) {
579                         preempt_disable();
580                         do_irq_balance();
581                         prev_balance_time = jiffies;
582                         time_remaining = balanced_irq_interval;
583                         preempt_enable();
584                 }
585         }
586         return 0;
587 }
588
589 static int __init balanced_irq_init(void)
590 {
591         int i;
592         struct cpuinfo_x86 *c;
593         cpumask_t tmp;
594
595         cpus_shift_right(tmp, cpu_online_map, 2);
596         c = &boot_cpu_data;
597         /* When not overwritten by the command line ask subarchitecture. */
598         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
599                 irqbalance_disabled = NO_BALANCE_IRQ;
600         if (irqbalance_disabled)
601                 return 0;
602         
603          /* disable irqbalance completely if there is only one processor online */
604         if (num_online_cpus() < 2) {
605                 irqbalance_disabled = 1;
606                 return 0;
607         }
608         /*
609          * Enable physical balance only if more than 1 physical processor
610          * is present
611          */
612         if (smp_num_siblings > 1 && !cpus_empty(tmp))
613                 physical_balance = 1;
614
615         for (i = 0; i < NR_CPUS; i++) {
616                 if (!cpu_online(i))
617                         continue;
618                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
619                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
620                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
621                         printk(KERN_ERR "balanced_irq_init: out of memory");
622                         goto failed;
623                 }
624                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
625                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
626         }
627         
628         printk(KERN_INFO "Starting balanced_irq\n");
629         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) 
630                 return 0;
631         else 
632                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
633 failed:
634         for (i = 0; i < NR_CPUS; i++) {
635                 if(irq_cpu_data[i].irq_delta)
636                         kfree(irq_cpu_data[i].irq_delta);
637                 if(irq_cpu_data[i].last_irq)
638                         kfree(irq_cpu_data[i].last_irq);
639         }
640         return 0;
641 }
642
643 int __init irqbalance_disable(char *str)
644 {
645         irqbalance_disabled = 1;
646         return 0;
647 }
648
649 __setup("noirqbalance", irqbalance_disable);
650
651 static inline void move_irq(int irq)
652 {
653         /* note - we hold the desc->lock */
654         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
655                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
656                 cpus_clear(pending_irq_balance_cpumask[irq]);
657         }
658 }
659
660 late_initcall(balanced_irq_init);
661
662 #else /* !CONFIG_IRQBALANCE */
663 static inline void move_irq(int irq) { }
664 #endif /* CONFIG_IRQBALANCE */
665
666 #ifndef CONFIG_SMP
667 void fastcall send_IPI_self(int vector)
668 {
669         unsigned int cfg;
670
671         /*
672          * Wait for idle.
673          */
674         apic_wait_icr_idle();
675         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
676         /*
677          * Send the IPI. The write to APIC_ICR fires this off.
678          */
679         apic_write_around(APIC_ICR, cfg);
680 }
681 #endif /* !CONFIG_SMP */
682
683
684 /*
685  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
686  * specific CPU-side IRQs.
687  */
688
689 #define MAX_PIRQS 8
690 static int pirq_entries [MAX_PIRQS];
691 static int pirqs_enabled;
692 int skip_ioapic_setup;
693
694 static int __init ioapic_setup(char *str)
695 {
696         skip_ioapic_setup = 1;
697         return 1;
698 }
699
700 __setup("noapic", ioapic_setup);
701
702 static int __init ioapic_pirq_setup(char *str)
703 {
704         int i, max;
705         int ints[MAX_PIRQS+1];
706
707         get_options(str, ARRAY_SIZE(ints), ints);
708
709         for (i = 0; i < MAX_PIRQS; i++)
710                 pirq_entries[i] = -1;
711
712         pirqs_enabled = 1;
713         apic_printk(APIC_VERBOSE, KERN_INFO
714                         "PIRQ redirection, working around broken MP-BIOS.\n");
715         max = MAX_PIRQS;
716         if (ints[0] < MAX_PIRQS)
717                 max = ints[0];
718
719         for (i = 0; i < max; i++) {
720                 apic_printk(APIC_VERBOSE, KERN_DEBUG
721                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
722                 /*
723                  * PIRQs are mapped upside down, usually.
724                  */
725                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
726         }
727         return 1;
728 }
729
730 __setup("pirq=", ioapic_pirq_setup);
731
732 /*
733  * Find the IRQ entry number of a certain pin.
734  */
735 static int find_irq_entry(int apic, int pin, int type)
736 {
737         int i;
738
739         for (i = 0; i < mp_irq_entries; i++)
740                 if (mp_irqs[i].mpc_irqtype == type &&
741                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
742                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
743                     mp_irqs[i].mpc_dstirq == pin)
744                         return i;
745
746         return -1;
747 }
748
749 /*
750  * Find the pin to which IRQ[irq] (ISA) is connected
751  */
752 static int find_isa_irq_pin(int irq, int type)
753 {
754         int i;
755
756         for (i = 0; i < mp_irq_entries; i++) {
757                 int lbus = mp_irqs[i].mpc_srcbus;
758
759                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
760                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
761                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
762                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
763                     ) &&
764                     (mp_irqs[i].mpc_irqtype == type) &&
765                     (mp_irqs[i].mpc_srcbusirq == irq))
766
767                         return mp_irqs[i].mpc_dstirq;
768         }
769         return -1;
770 }
771
772 /*
773  * Find a specific PCI IRQ entry.
774  * Not an __init, possibly needed by modules
775  */
776 static int pin_2_irq(int idx, int apic, int pin);
777
778 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
779 {
780         int apic, i, best_guess = -1;
781
782         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
783                 "slot:%d, pin:%d.\n", bus, slot, pin);
784         if (mp_bus_id_to_pci_bus[bus] == -1) {
785                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
786                 return -1;
787         }
788         for (i = 0; i < mp_irq_entries; i++) {
789                 int lbus = mp_irqs[i].mpc_srcbus;
790
791                 for (apic = 0; apic < nr_ioapics; apic++)
792                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
793                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
794                                 break;
795
796                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
797                     !mp_irqs[i].mpc_irqtype &&
798                     (bus == lbus) &&
799                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
800                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
801
802                         if (!(apic || IO_APIC_IRQ(irq)))
803                                 continue;
804
805                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
806                                 return irq;
807                         /*
808                          * Use the first all-but-pin matching entry as a
809                          * best-guess fuzzy result for broken mptables.
810                          */
811                         if (best_guess < 0)
812                                 best_guess = irq;
813                 }
814         }
815         return best_guess;
816 }
817 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
818
819 /*
820  * This function currently is only a helper for the i386 smp boot process where 
821  * we need to reprogram the ioredtbls to cater for the cpus which have come online
822  * so mask in all cases should simply be TARGET_CPUS
823  */
824 void __init setup_ioapic_dest(void)
825 {
826         int pin, ioapic, irq, irq_entry;
827
828         if (skip_ioapic_setup == 1)
829                 return;
830
831         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
832                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
833                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
834                         if (irq_entry == -1)
835                                 continue;
836                         irq = pin_2_irq(irq_entry, ioapic, pin);
837                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
838                 }
839
840         }
841 }
842
843 /*
844  * EISA Edge/Level control register, ELCR
845  */
846 static int EISA_ELCR(unsigned int irq)
847 {
848         if (irq < 16) {
849                 unsigned int port = 0x4d0 + (irq >> 3);
850                 return (inb(port) >> (irq & 7)) & 1;
851         }
852         apic_printk(APIC_VERBOSE, KERN_INFO
853                         "Broken MPtable reports ISA irq %d\n", irq);
854         return 0;
855 }
856
857 /* EISA interrupts are always polarity zero and can be edge or level
858  * trigger depending on the ELCR value.  If an interrupt is listed as
859  * EISA conforming in the MP table, that means its trigger type must
860  * be read in from the ELCR */
861
862 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
863 #define default_EISA_polarity(idx)      (0)
864
865 /* ISA interrupts are always polarity zero edge triggered,
866  * when listed as conforming in the MP table. */
867
868 #define default_ISA_trigger(idx)        (0)
869 #define default_ISA_polarity(idx)       (0)
870
871 /* PCI interrupts are always polarity one level triggered,
872  * when listed as conforming in the MP table. */
873
874 #define default_PCI_trigger(idx)        (1)
875 #define default_PCI_polarity(idx)       (1)
876
877 /* MCA interrupts are always polarity zero level triggered,
878  * when listed as conforming in the MP table. */
879
880 #define default_MCA_trigger(idx)        (1)
881 #define default_MCA_polarity(idx)       (0)
882
883 /* NEC98 interrupts are always polarity zero edge triggered,
884  * when listed as conforming in the MP table. */
885
886 #define default_NEC98_trigger(idx)     (0)
887 #define default_NEC98_polarity(idx)    (0)
888
889 static int __init MPBIOS_polarity(int idx)
890 {
891         int bus = mp_irqs[idx].mpc_srcbus;
892         int polarity;
893
894         /*
895          * Determine IRQ line polarity (high active or low active):
896          */
897         switch (mp_irqs[idx].mpc_irqflag & 3)
898         {
899                 case 0: /* conforms, ie. bus-type dependent polarity */
900                 {
901                         switch (mp_bus_id_to_type[bus])
902                         {
903                                 case MP_BUS_ISA: /* ISA pin */
904                                 {
905                                         polarity = default_ISA_polarity(idx);
906                                         break;
907                                 }
908                                 case MP_BUS_EISA: /* EISA pin */
909                                 {
910                                         polarity = default_EISA_polarity(idx);
911                                         break;
912                                 }
913                                 case MP_BUS_PCI: /* PCI pin */
914                                 {
915                                         polarity = default_PCI_polarity(idx);
916                                         break;
917                                 }
918                                 case MP_BUS_MCA: /* MCA pin */
919                                 {
920                                         polarity = default_MCA_polarity(idx);
921                                         break;
922                                 }
923                                 case MP_BUS_NEC98: /* NEC 98 pin */
924                                 {
925                                         polarity = default_NEC98_polarity(idx);
926                                         break;
927                                 }
928                                 default:
929                                 {
930                                         printk(KERN_WARNING "broken BIOS!!\n");
931                                         polarity = 1;
932                                         break;
933                                 }
934                         }
935                         break;
936                 }
937                 case 1: /* high active */
938                 {
939                         polarity = 0;
940                         break;
941                 }
942                 case 2: /* reserved */
943                 {
944                         printk(KERN_WARNING "broken BIOS!!\n");
945                         polarity = 1;
946                         break;
947                 }
948                 case 3: /* low active */
949                 {
950                         polarity = 1;
951                         break;
952                 }
953                 default: /* invalid */
954                 {
955                         printk(KERN_WARNING "broken BIOS!!\n");
956                         polarity = 1;
957                         break;
958                 }
959         }
960         return polarity;
961 }
962
963 static int MPBIOS_trigger(int idx)
964 {
965         int bus = mp_irqs[idx].mpc_srcbus;
966         int trigger;
967
968         /*
969          * Determine IRQ trigger mode (edge or level sensitive):
970          */
971         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
972         {
973                 case 0: /* conforms, ie. bus-type dependent */
974                 {
975                         switch (mp_bus_id_to_type[bus])
976                         {
977                                 case MP_BUS_ISA: /* ISA pin */
978                                 {
979                                         trigger = default_ISA_trigger(idx);
980                                         break;
981                                 }
982                                 case MP_BUS_EISA: /* EISA pin */
983                                 {
984                                         trigger = default_EISA_trigger(idx);
985                                         break;
986                                 }
987                                 case MP_BUS_PCI: /* PCI pin */
988                                 {
989                                         trigger = default_PCI_trigger(idx);
990                                         break;
991                                 }
992                                 case MP_BUS_MCA: /* MCA pin */
993                                 {
994                                         trigger = default_MCA_trigger(idx);
995                                         break;
996                                 }
997                                 case MP_BUS_NEC98: /* NEC 98 pin */
998                                 {
999                                         trigger = default_NEC98_trigger(idx);
1000                                         break;
1001                                 }
1002                                 default:
1003                                 {
1004                                         printk(KERN_WARNING "broken BIOS!!\n");
1005                                         trigger = 1;
1006                                         break;
1007                                 }
1008                         }
1009                         break;
1010                 }
1011                 case 1: /* edge */
1012                 {
1013                         trigger = 0;
1014                         break;
1015                 }
1016                 case 2: /* reserved */
1017                 {
1018                         printk(KERN_WARNING "broken BIOS!!\n");
1019                         trigger = 1;
1020                         break;
1021                 }
1022                 case 3: /* level */
1023                 {
1024                         trigger = 1;
1025                         break;
1026                 }
1027                 default: /* invalid */
1028                 {
1029                         printk(KERN_WARNING "broken BIOS!!\n");
1030                         trigger = 0;
1031                         break;
1032                 }
1033         }
1034         return trigger;
1035 }
1036
1037 static inline int irq_polarity(int idx)
1038 {
1039         return MPBIOS_polarity(idx);
1040 }
1041
1042 static inline int irq_trigger(int idx)
1043 {
1044         return MPBIOS_trigger(idx);
1045 }
1046
1047 static int pin_2_irq(int idx, int apic, int pin)
1048 {
1049         int irq, i;
1050         int bus = mp_irqs[idx].mpc_srcbus;
1051
1052         /*
1053          * Debugging check, we are in big trouble if this message pops up!
1054          */
1055         if (mp_irqs[idx].mpc_dstirq != pin)
1056                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1057
1058         switch (mp_bus_id_to_type[bus])
1059         {
1060                 case MP_BUS_ISA: /* ISA pin */
1061                 case MP_BUS_EISA:
1062                 case MP_BUS_MCA:
1063                 case MP_BUS_NEC98:
1064                 {
1065                         irq = mp_irqs[idx].mpc_srcbusirq;
1066                         break;
1067                 }
1068                 case MP_BUS_PCI: /* PCI pin */
1069                 {
1070                         /*
1071                          * PCI IRQs are mapped in order
1072                          */
1073                         i = irq = 0;
1074                         while (i < apic)
1075                                 irq += nr_ioapic_registers[i++];
1076                         irq += pin;
1077
1078                         /*
1079                          * For MPS mode, so far only needed by ES7000 platform
1080                          */
1081                         if (ioapic_renumber_irq)
1082                                 irq = ioapic_renumber_irq(apic, irq);
1083
1084                         break;
1085                 }
1086                 default:
1087                 {
1088                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1089                         irq = 0;
1090                         break;
1091                 }
1092         }
1093
1094         /*
1095          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1096          */
1097         if ((pin >= 16) && (pin <= 23)) {
1098                 if (pirq_entries[pin-16] != -1) {
1099                         if (!pirq_entries[pin-16]) {
1100                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1101                                                 "disabling PIRQ%d\n", pin-16);
1102                         } else {
1103                                 irq = pirq_entries[pin-16];
1104                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1105                                                 "using PIRQ%d -> IRQ %d\n",
1106                                                 pin-16, irq);
1107                         }
1108                 }
1109         }
1110         return irq;
1111 }
1112
1113 static inline int IO_APIC_irq_trigger(int irq)
1114 {
1115         int apic, idx, pin;
1116
1117         for (apic = 0; apic < nr_ioapics; apic++) {
1118                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1119                         idx = find_irq_entry(apic,pin,mp_INT);
1120                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1121                                 return irq_trigger(idx);
1122                 }
1123         }
1124         /*
1125          * nonexistent IRQs are edge default
1126          */
1127         return 0;
1128 }
1129
1130 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1131 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1132
1133 int assign_irq_vector(int irq)
1134 {
1135         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1136
1137         BUG_ON(irq >= NR_IRQ_VECTORS);
1138         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1139                 return IO_APIC_VECTOR(irq);
1140 next:
1141         current_vector += 8;
1142         if (current_vector == SYSCALL_VECTOR)
1143                 goto next;
1144
1145         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1146                 offset++;
1147                 if (!(offset%8))
1148                         return -ENOSPC;
1149                 current_vector = FIRST_DEVICE_VECTOR + offset;
1150         }
1151
1152         vector_irq[current_vector] = irq;
1153         if (irq != AUTO_ASSIGN)
1154                 IO_APIC_VECTOR(irq) = current_vector;
1155
1156         return current_vector;
1157 }
1158
1159 static struct hw_interrupt_type ioapic_level_type;
1160 static struct hw_interrupt_type ioapic_edge_type;
1161
1162 #define IOAPIC_AUTO     -1
1163 #define IOAPIC_EDGE     0
1164 #define IOAPIC_LEVEL    1
1165
1166 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1167 {
1168         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1169                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1170                                 trigger == IOAPIC_LEVEL)
1171                         irq_desc[vector].handler = &ioapic_level_type;
1172                 else
1173                         irq_desc[vector].handler = &ioapic_edge_type;
1174                 set_intr_gate(vector, interrupt[vector]);
1175         } else  {
1176                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1177                                 trigger == IOAPIC_LEVEL)
1178                         irq_desc[irq].handler = &ioapic_level_type;
1179                 else
1180                         irq_desc[irq].handler = &ioapic_edge_type;
1181                 set_intr_gate(vector, interrupt[irq]);
1182         }
1183 }
1184
1185 static void __init setup_IO_APIC_irqs(void)
1186 {
1187         struct IO_APIC_route_entry entry;
1188         int apic, pin, idx, irq, first_notcon = 1, vector;
1189         unsigned long flags;
1190
1191         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1192
1193         for (apic = 0; apic < nr_ioapics; apic++) {
1194         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1195
1196                 /*
1197                  * add it to the IO-APIC irq-routing table:
1198                  */
1199                 memset(&entry,0,sizeof(entry));
1200
1201                 entry.delivery_mode = INT_DELIVERY_MODE;
1202                 entry.dest_mode = INT_DEST_MODE;
1203                 entry.mask = 0;                         /* enable IRQ */
1204                 entry.dest.logical.logical_dest = 
1205                                         cpu_mask_to_apicid(TARGET_CPUS);
1206
1207                 idx = find_irq_entry(apic,pin,mp_INT);
1208                 if (idx == -1) {
1209                         if (first_notcon) {
1210                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1211                                                 " IO-APIC (apicid-pin) %d-%d",
1212                                                 mp_ioapics[apic].mpc_apicid,
1213                                                 pin);
1214                                 first_notcon = 0;
1215                         } else
1216                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1217                                         mp_ioapics[apic].mpc_apicid, pin);
1218                         continue;
1219                 }
1220
1221                 entry.trigger = irq_trigger(idx);
1222                 entry.polarity = irq_polarity(idx);
1223
1224                 if (irq_trigger(idx)) {
1225                         entry.trigger = 1;
1226                         entry.mask = 1;
1227                 }
1228
1229                 irq = pin_2_irq(idx, apic, pin);
1230                 /*
1231                  * skip adding the timer int on secondary nodes, which causes
1232                  * a small but painful rift in the time-space continuum
1233                  */
1234                 if (multi_timer_check(apic, irq))
1235                         continue;
1236                 else
1237                         add_pin_to_irq(irq, apic, pin);
1238
1239                 if (!apic && !IO_APIC_IRQ(irq))
1240                         continue;
1241
1242                 if (IO_APIC_IRQ(irq)) {
1243                         vector = assign_irq_vector(irq);
1244                         entry.vector = vector;
1245                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1246                 
1247                         if (!apic && (irq < 16))
1248                                 disable_8259A_irq(irq);
1249                 }
1250                 spin_lock_irqsave(&ioapic_lock, flags);
1251                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1252                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1253                 spin_unlock_irqrestore(&ioapic_lock, flags);
1254         }
1255         }
1256
1257         if (!first_notcon)
1258                 apic_printk(APIC_VERBOSE, " not connected.\n");
1259 }
1260
1261 /*
1262  * Set up the 8259A-master output pin:
1263  */
1264 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1265 {
1266         struct IO_APIC_route_entry entry;
1267         unsigned long flags;
1268
1269         memset(&entry,0,sizeof(entry));
1270
1271         disable_8259A_irq(0);
1272
1273         /* mask LVT0 */
1274         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1275
1276         /*
1277          * We use logical delivery to get the timer IRQ
1278          * to the first CPU.
1279          */
1280         entry.dest_mode = INT_DEST_MODE;
1281         entry.mask = 0;                                 /* unmask IRQ now */
1282         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1283         entry.delivery_mode = INT_DELIVERY_MODE;
1284         entry.polarity = 0;
1285         entry.trigger = 0;
1286         entry.vector = vector;
1287
1288         /*
1289          * The timer IRQ doesn't have to know that behind the
1290          * scene we have a 8259A-master in AEOI mode ...
1291          */
1292         irq_desc[0].handler = &ioapic_edge_type;
1293
1294         /*
1295          * Add it to the IO-APIC irq-routing table:
1296          */
1297         spin_lock_irqsave(&ioapic_lock, flags);
1298         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1299         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1300         spin_unlock_irqrestore(&ioapic_lock, flags);
1301
1302         enable_8259A_irq(0);
1303 }
1304
1305 static inline void UNEXPECTED_IO_APIC(void)
1306 {
1307 }
1308
1309 void __init print_IO_APIC(void)
1310 {
1311         int apic, i;
1312         union IO_APIC_reg_00 reg_00;
1313         union IO_APIC_reg_01 reg_01;
1314         union IO_APIC_reg_02 reg_02;
1315         union IO_APIC_reg_03 reg_03;
1316         unsigned long flags;
1317
1318         if (apic_verbosity == APIC_QUIET)
1319                 return;
1320
1321         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1322         for (i = 0; i < nr_ioapics; i++)
1323                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1324                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1325
1326         /*
1327          * We are a bit conservative about what we expect.  We have to
1328          * know about every hardware change ASAP.
1329          */
1330         printk(KERN_INFO "testing the IO APIC.......................\n");
1331
1332         for (apic = 0; apic < nr_ioapics; apic++) {
1333
1334         spin_lock_irqsave(&ioapic_lock, flags);
1335         reg_00.raw = io_apic_read(apic, 0);
1336         reg_01.raw = io_apic_read(apic, 1);
1337         if (reg_01.bits.version >= 0x10)
1338                 reg_02.raw = io_apic_read(apic, 2);
1339         if (reg_01.bits.version >= 0x20)
1340                 reg_03.raw = io_apic_read(apic, 3);
1341         spin_unlock_irqrestore(&ioapic_lock, flags);
1342
1343         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1344         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1345         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1346         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1347         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1348         if (reg_00.bits.ID >= get_physical_broadcast())
1349                 UNEXPECTED_IO_APIC();
1350         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1351                 UNEXPECTED_IO_APIC();
1352
1353         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1354         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1355         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1356                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1357                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1358                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1359                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1360                 (reg_01.bits.entries != 0x2E) &&
1361                 (reg_01.bits.entries != 0x3F)
1362         )
1363                 UNEXPECTED_IO_APIC();
1364
1365         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1366         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1367         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1368                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1369                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1370                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1371                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1372         )
1373                 UNEXPECTED_IO_APIC();
1374         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1375                 UNEXPECTED_IO_APIC();
1376
1377         /*
1378          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1379          * but the value of reg_02 is read as the previous read register
1380          * value, so ignore it if reg_02 == reg_01.
1381          */
1382         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1383                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1384                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1385                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1386                         UNEXPECTED_IO_APIC();
1387         }
1388
1389         /*
1390          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1391          * or reg_03, but the value of reg_0[23] is read as the previous read
1392          * register value, so ignore it if reg_03 == reg_0[12].
1393          */
1394         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1395             reg_03.raw != reg_01.raw) {
1396                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1397                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1398                 if (reg_03.bits.__reserved_1)
1399                         UNEXPECTED_IO_APIC();
1400         }
1401
1402         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1403
1404         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1405                           " Stat Dest Deli Vect:   \n");
1406
1407         for (i = 0; i <= reg_01.bits.entries; i++) {
1408                 struct IO_APIC_route_entry entry;
1409
1410                 spin_lock_irqsave(&ioapic_lock, flags);
1411                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1412                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1413                 spin_unlock_irqrestore(&ioapic_lock, flags);
1414
1415                 printk(KERN_DEBUG " %02x %03X %02X  ",
1416                         i,
1417                         entry.dest.logical.logical_dest,
1418                         entry.dest.physical.physical_dest
1419                 );
1420
1421                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1422                         entry.mask,
1423                         entry.trigger,
1424                         entry.irr,
1425                         entry.polarity,
1426                         entry.delivery_status,
1427                         entry.dest_mode,
1428                         entry.delivery_mode,
1429                         entry.vector
1430                 );
1431         }
1432         }
1433         if (use_pci_vector())
1434                 printk(KERN_INFO "Using vector-based indexing\n");
1435         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1436         for (i = 0; i < NR_IRQS; i++) {
1437                 struct irq_pin_list *entry = irq_2_pin + i;
1438                 if (entry->pin < 0)
1439                         continue;
1440                 if (use_pci_vector() && !platform_legacy_irq(i))
1441                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1442                 else
1443                         printk(KERN_DEBUG "IRQ%d ", i);
1444                 for (;;) {
1445                         printk("-> %d:%d", entry->apic, entry->pin);
1446                         if (!entry->next)
1447                                 break;
1448                         entry = irq_2_pin + entry->next;
1449                 }
1450                 printk("\n");
1451         }
1452
1453         printk(KERN_INFO ".................................... done.\n");
1454
1455         return;
1456 }
1457
1458 #if 0
1459
1460 static void print_APIC_bitfield (int base)
1461 {
1462         unsigned int v;
1463         int i, j;
1464
1465         if (apic_verbosity == APIC_QUIET)
1466                 return;
1467
1468         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1469         for (i = 0; i < 8; i++) {
1470                 v = apic_read(base + i*0x10);
1471                 for (j = 0; j < 32; j++) {
1472                         if (v & (1<<j))
1473                                 printk("1");
1474                         else
1475                                 printk("0");
1476                 }
1477                 printk("\n");
1478         }
1479 }
1480
1481 void /*__init*/ print_local_APIC(void * dummy)
1482 {
1483         unsigned int v, ver, maxlvt;
1484
1485         if (apic_verbosity == APIC_QUIET)
1486                 return;
1487
1488         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1489                 smp_processor_id(), hard_smp_processor_id());
1490         v = apic_read(APIC_ID);
1491         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1492         v = apic_read(APIC_LVR);
1493         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1494         ver = GET_APIC_VERSION(v);
1495         maxlvt = get_maxlvt();
1496
1497         v = apic_read(APIC_TASKPRI);
1498         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1499
1500         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1501                 v = apic_read(APIC_ARBPRI);
1502                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1503                         v & APIC_ARBPRI_MASK);
1504                 v = apic_read(APIC_PROCPRI);
1505                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1506         }
1507
1508         v = apic_read(APIC_EOI);
1509         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1510         v = apic_read(APIC_RRR);
1511         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1512         v = apic_read(APIC_LDR);
1513         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1514         v = apic_read(APIC_DFR);
1515         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1516         v = apic_read(APIC_SPIV);
1517         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1518
1519         printk(KERN_DEBUG "... APIC ISR field:\n");
1520         print_APIC_bitfield(APIC_ISR);
1521         printk(KERN_DEBUG "... APIC TMR field:\n");
1522         print_APIC_bitfield(APIC_TMR);
1523         printk(KERN_DEBUG "... APIC IRR field:\n");
1524         print_APIC_bitfield(APIC_IRR);
1525
1526         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1527                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1528                         apic_write(APIC_ESR, 0);
1529                 v = apic_read(APIC_ESR);
1530                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1531         }
1532
1533         v = apic_read(APIC_ICR);
1534         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1535         v = apic_read(APIC_ICR2);
1536         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1537
1538         v = apic_read(APIC_LVTT);
1539         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1540
1541         if (maxlvt > 3) {                       /* PC is LVT#4. */
1542                 v = apic_read(APIC_LVTPC);
1543                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1544         }
1545         v = apic_read(APIC_LVT0);
1546         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1547         v = apic_read(APIC_LVT1);
1548         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1549
1550         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1551                 v = apic_read(APIC_LVTERR);
1552                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1553         }
1554
1555         v = apic_read(APIC_TMICT);
1556         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1557         v = apic_read(APIC_TMCCT);
1558         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1559         v = apic_read(APIC_TDCR);
1560         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1561         printk("\n");
1562 }
1563
1564 void print_all_local_APICs (void)
1565 {
1566         on_each_cpu(print_local_APIC, NULL, 1, 1);
1567 }
1568
1569 void /*__init*/ print_PIC(void)
1570 {
1571         extern spinlock_t i8259A_lock;
1572         unsigned int v;
1573         unsigned long flags;
1574
1575         if (apic_verbosity == APIC_QUIET)
1576                 return;
1577
1578         printk(KERN_DEBUG "\nprinting PIC contents\n");
1579
1580         spin_lock_irqsave(&i8259A_lock, flags);
1581
1582         v = inb(0xa1) << 8 | inb(0x21);
1583         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1584
1585         v = inb(0xa0) << 8 | inb(0x20);
1586         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1587
1588         outb(0x0b,0xa0);
1589         outb(0x0b,0x20);
1590         v = inb(0xa0) << 8 | inb(0x20);
1591         outb(0x0a,0xa0);
1592         outb(0x0a,0x20);
1593
1594         spin_unlock_irqrestore(&i8259A_lock, flags);
1595
1596         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1597
1598         v = inb(0x4d1) << 8 | inb(0x4d0);
1599         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1600 }
1601
1602 #endif  /*  0  */
1603
1604 static void __init enable_IO_APIC(void)
1605 {
1606         union IO_APIC_reg_01 reg_01;
1607         int i;
1608         unsigned long flags;
1609
1610         for (i = 0; i < PIN_MAP_SIZE; i++) {
1611                 irq_2_pin[i].pin = -1;
1612                 irq_2_pin[i].next = 0;
1613         }
1614         if (!pirqs_enabled)
1615                 for (i = 0; i < MAX_PIRQS; i++)
1616                         pirq_entries[i] = -1;
1617
1618         /*
1619          * The number of IO-APIC IRQ registers (== #pins):
1620          */
1621         for (i = 0; i < nr_ioapics; i++) {
1622                 spin_lock_irqsave(&ioapic_lock, flags);
1623                 reg_01.raw = io_apic_read(i, 1);
1624                 spin_unlock_irqrestore(&ioapic_lock, flags);
1625                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1626         }
1627
1628         /*
1629          * Do not trust the IO-APIC being empty at bootup
1630          */
1631         clear_IO_APIC();
1632 }
1633
1634 /*
1635  * Not an __init, needed by the reboot code
1636  */
1637 void disable_IO_APIC(void)
1638 {
1639         /*
1640          * Clear the IO-APIC before rebooting:
1641          */
1642         clear_IO_APIC();
1643
1644         disconnect_bsp_APIC();
1645 }
1646
1647 /*
1648  * function to set the IO-APIC physical IDs based on the
1649  * values stored in the MPC table.
1650  *
1651  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1652  */
1653
1654 #ifndef CONFIG_X86_NUMAQ
1655 static void __init setup_ioapic_ids_from_mpc(void)
1656 {
1657         union IO_APIC_reg_00 reg_00;
1658         physid_mask_t phys_id_present_map;
1659         int apic;
1660         int i;
1661         unsigned char old_id;
1662         unsigned long flags;
1663
1664         /*
1665          * Don't check I/O APIC IDs for xAPIC systems.  They have
1666          * no meaning without the serial APIC bus.
1667          */
1668         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1669                 return;
1670         /*
1671          * This is broken; anything with a real cpu count has to
1672          * circumvent this idiocy regardless.
1673          */
1674         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1675
1676         /*
1677          * Set the IOAPIC ID to the value stored in the MPC table.
1678          */
1679         for (apic = 0; apic < nr_ioapics; apic++) {
1680
1681                 /* Read the register 0 value */
1682                 spin_lock_irqsave(&ioapic_lock, flags);
1683                 reg_00.raw = io_apic_read(apic, 0);
1684                 spin_unlock_irqrestore(&ioapic_lock, flags);
1685                 
1686                 old_id = mp_ioapics[apic].mpc_apicid;
1687
1688                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1689                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1690                                 apic, mp_ioapics[apic].mpc_apicid);
1691                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1692                                 reg_00.bits.ID);
1693                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1694                 }
1695
1696                 /*
1697                  * Sanity check, is the ID really free? Every APIC in a
1698                  * system must have a unique ID or we get lots of nice
1699                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1700                  */
1701                 if (check_apicid_used(phys_id_present_map,
1702                                         mp_ioapics[apic].mpc_apicid)) {
1703                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1704                                 apic, mp_ioapics[apic].mpc_apicid);
1705                         for (i = 0; i < get_physical_broadcast(); i++)
1706                                 if (!physid_isset(i, phys_id_present_map))
1707                                         break;
1708                         if (i >= get_physical_broadcast())
1709                                 panic("Max APIC ID exceeded!\n");
1710                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1711                                 i);
1712                         physid_set(i, phys_id_present_map);
1713                         mp_ioapics[apic].mpc_apicid = i;
1714                 } else {
1715                         physid_mask_t tmp;
1716                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1717                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1718                                         "phys_id_present_map\n",
1719                                         mp_ioapics[apic].mpc_apicid);
1720                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1721                 }
1722
1723
1724                 /*
1725                  * We need to adjust the IRQ routing table
1726                  * if the ID changed.
1727                  */
1728                 if (old_id != mp_ioapics[apic].mpc_apicid)
1729                         for (i = 0; i < mp_irq_entries; i++)
1730                                 if (mp_irqs[i].mpc_dstapic == old_id)
1731                                         mp_irqs[i].mpc_dstapic
1732                                                 = mp_ioapics[apic].mpc_apicid;
1733
1734                 /*
1735                  * Read the right value from the MPC table and
1736                  * write it into the ID register.
1737                  */
1738                 apic_printk(APIC_VERBOSE, KERN_INFO
1739                         "...changing IO-APIC physical APIC ID to %d ...",
1740                         mp_ioapics[apic].mpc_apicid);
1741
1742                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1743                 spin_lock_irqsave(&ioapic_lock, flags);
1744                 io_apic_write(apic, 0, reg_00.raw);
1745                 spin_unlock_irqrestore(&ioapic_lock, flags);
1746
1747                 /*
1748                  * Sanity check
1749                  */
1750                 spin_lock_irqsave(&ioapic_lock, flags);
1751                 reg_00.raw = io_apic_read(apic, 0);
1752                 spin_unlock_irqrestore(&ioapic_lock, flags);
1753                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1754                         printk("could not set ID!\n");
1755                 else
1756                         apic_printk(APIC_VERBOSE, " ok.\n");
1757         }
1758 }
1759 #else
1760 static void __init setup_ioapic_ids_from_mpc(void) { }
1761 #endif
1762
1763 /*
1764  * There is a nasty bug in some older SMP boards, their mptable lies
1765  * about the timer IRQ. We do the following to work around the situation:
1766  *
1767  *      - timer IRQ defaults to IO-APIC IRQ
1768  *      - if this function detects that timer IRQs are defunct, then we fall
1769  *        back to ISA timer IRQs
1770  */
1771 static int __init timer_irq_works(void)
1772 {
1773         unsigned long t1 = jiffies;
1774
1775         local_irq_enable();
1776         /* Let ten ticks pass... */
1777         mdelay((10 * 1000) / HZ);
1778
1779         /*
1780          * Expect a few ticks at least, to be sure some possible
1781          * glue logic does not lock up after one or two first
1782          * ticks in a non-ExtINT mode.  Also the local APIC
1783          * might have cached one ExtINT interrupt.  Finally, at
1784          * least one tick may be lost due to delays.
1785          */
1786         if (jiffies - t1 > 4)
1787                 return 1;
1788
1789         return 0;
1790 }
1791
1792 /*
1793  * In the SMP+IOAPIC case it might happen that there are an unspecified
1794  * number of pending IRQ events unhandled. These cases are very rare,
1795  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1796  * better to do it this way as thus we do not have to be aware of
1797  * 'pending' interrupts in the IRQ path, except at this point.
1798  */
1799 /*
1800  * Edge triggered needs to resend any interrupt
1801  * that was delayed but this is now handled in the device
1802  * independent code.
1803  */
1804
1805 /*
1806  * Starting up a edge-triggered IO-APIC interrupt is
1807  * nasty - we need to make sure that we get the edge.
1808  * If it is already asserted for some reason, we need
1809  * return 1 to indicate that is was pending.
1810  *
1811  * This is not complete - we should be able to fake
1812  * an edge even if it isn't on the 8259A...
1813  */
1814 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1815 {
1816         int was_pending = 0;
1817         unsigned long flags;
1818
1819         spin_lock_irqsave(&ioapic_lock, flags);
1820         if (irq < 16) {
1821                 disable_8259A_irq(irq);
1822                 if (i8259A_irq_pending(irq))
1823                         was_pending = 1;
1824         }
1825         __unmask_IO_APIC_irq(irq);
1826         spin_unlock_irqrestore(&ioapic_lock, flags);
1827
1828         return was_pending;
1829 }
1830
1831 /*
1832  * Once we have recorded IRQ_PENDING already, we can mask the
1833  * interrupt for real. This prevents IRQ storms from unhandled
1834  * devices.
1835  */
1836 static void ack_edge_ioapic_irq(unsigned int irq)
1837 {
1838         move_irq(irq);
1839         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1840                                         == (IRQ_PENDING | IRQ_DISABLED))
1841                 mask_IO_APIC_irq(irq);
1842         ack_APIC_irq();
1843 }
1844
1845 /*
1846  * Level triggered interrupts can just be masked,
1847  * and shutting down and starting up the interrupt
1848  * is the same as enabling and disabling them -- except
1849  * with a startup need to return a "was pending" value.
1850  *
1851  * Level triggered interrupts are special because we
1852  * do not touch any IO-APIC register while handling
1853  * them. We ack the APIC in the end-IRQ handler, not
1854  * in the start-IRQ-handler. Protection against reentrance
1855  * from the same interrupt is still provided, both by the
1856  * generic IRQ layer and by the fact that an unacked local
1857  * APIC does not accept IRQs.
1858  */
1859 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1860 {
1861         unmask_IO_APIC_irq(irq);
1862
1863         return 0; /* don't check for pending */
1864 }
1865
1866 static void end_level_ioapic_irq (unsigned int irq)
1867 {
1868         unsigned long v;
1869         int i;
1870
1871         move_irq(irq);
1872 /*
1873  * It appears there is an erratum which affects at least version 0x11
1874  * of I/O APIC (that's the 82093AA and cores integrated into various
1875  * chipsets).  Under certain conditions a level-triggered interrupt is
1876  * erroneously delivered as edge-triggered one but the respective IRR
1877  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1878  * message but it will never arrive and further interrupts are blocked
1879  * from the source.  The exact reason is so far unknown, but the
1880  * phenomenon was observed when two consecutive interrupt requests
1881  * from a given source get delivered to the same CPU and the source is
1882  * temporarily disabled in between.
1883  *
1884  * A workaround is to simulate an EOI message manually.  We achieve it
1885  * by setting the trigger mode to edge and then to level when the edge
1886  * trigger mode gets detected in the TMR of a local APIC for a
1887  * level-triggered interrupt.  We mask the source for the time of the
1888  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1889  * The idea is from Manfred Spraul.  --macro
1890  */
1891         i = IO_APIC_VECTOR(irq);
1892
1893         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1894
1895         ack_APIC_irq();
1896
1897         if (!(v & (1 << (i & 0x1f)))) {
1898                 atomic_inc(&irq_mis_count);
1899                 spin_lock(&ioapic_lock);
1900                 __mask_and_edge_IO_APIC_irq(irq);
1901                 __unmask_and_level_IO_APIC_irq(irq);
1902                 spin_unlock(&ioapic_lock);
1903         }
1904 }
1905
1906 #ifdef CONFIG_PCI_MSI
1907 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1908 {
1909         int irq = vector_to_irq(vector);
1910
1911         return startup_edge_ioapic_irq(irq);
1912 }
1913
1914 static void ack_edge_ioapic_vector(unsigned int vector)
1915 {
1916         int irq = vector_to_irq(vector);
1917
1918         ack_edge_ioapic_irq(irq);
1919 }
1920
1921 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1922 {
1923         int irq = vector_to_irq(vector);
1924
1925         return startup_level_ioapic_irq (irq);
1926 }
1927
1928 static void end_level_ioapic_vector (unsigned int vector)
1929 {
1930         int irq = vector_to_irq(vector);
1931
1932         end_level_ioapic_irq(irq);
1933 }
1934
1935 static void mask_IO_APIC_vector (unsigned int vector)
1936 {
1937         int irq = vector_to_irq(vector);
1938
1939         mask_IO_APIC_irq(irq);
1940 }
1941
1942 static void unmask_IO_APIC_vector (unsigned int vector)
1943 {
1944         int irq = vector_to_irq(vector);
1945
1946         unmask_IO_APIC_irq(irq);
1947 }
1948
1949 static void set_ioapic_affinity_vector (unsigned int vector,
1950                                         cpumask_t cpu_mask)
1951 {
1952         int irq = vector_to_irq(vector);
1953
1954         set_ioapic_affinity_irq(irq, cpu_mask);
1955 }
1956 #endif
1957
1958 /*
1959  * Level and edge triggered IO-APIC interrupts need different handling,
1960  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1961  * handled with the level-triggered descriptor, but that one has slightly
1962  * more overhead. Level-triggered interrupts cannot be handled with the
1963  * edge-triggered handler, without risking IRQ storms and other ugly
1964  * races.
1965  */
1966 static struct hw_interrupt_type ioapic_edge_type = {
1967         .typename       = "IO-APIC-edge",
1968         .startup        = startup_edge_ioapic,
1969         .shutdown       = shutdown_edge_ioapic,
1970         .enable         = enable_edge_ioapic,
1971         .disable        = disable_edge_ioapic,
1972         .ack            = ack_edge_ioapic,
1973         .end            = end_edge_ioapic,
1974         .set_affinity   = set_ioapic_affinity,
1975 };
1976
1977 static struct hw_interrupt_type ioapic_level_type = {
1978         .typename       = "IO-APIC-level",
1979         .startup        = startup_level_ioapic,
1980         .shutdown       = shutdown_level_ioapic,
1981         .enable         = enable_level_ioapic,
1982         .disable        = disable_level_ioapic,
1983         .ack            = mask_and_ack_level_ioapic,
1984         .end            = end_level_ioapic,
1985         .set_affinity   = set_ioapic_affinity,
1986 };
1987
1988 static inline void init_IO_APIC_traps(void)
1989 {
1990         int irq;
1991
1992         /*
1993          * NOTE! The local APIC isn't very good at handling
1994          * multiple interrupts at the same interrupt level.
1995          * As the interrupt level is determined by taking the
1996          * vector number and shifting that right by 4, we
1997          * want to spread these out a bit so that they don't
1998          * all fall in the same interrupt level.
1999          *
2000          * Also, we've got to be careful not to trash gate
2001          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2002          */
2003         for (irq = 0; irq < NR_IRQS ; irq++) {
2004                 int tmp = irq;
2005                 if (use_pci_vector()) {
2006                         if (!platform_legacy_irq(tmp))
2007                                 if ((tmp = vector_to_irq(tmp)) == -1)
2008                                         continue;
2009                 }
2010                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2011                         /*
2012                          * Hmm.. We don't have an entry for this,
2013                          * so default to an old-fashioned 8259
2014                          * interrupt if we can..
2015                          */
2016                         if (irq < 16)
2017                                 make_8259A_irq(irq);
2018                         else
2019                                 /* Strange. Oh, well.. */
2020                                 irq_desc[irq].handler = &no_irq_type;
2021                 }
2022         }
2023 }
2024
2025 static void enable_lapic_irq (unsigned int irq)
2026 {
2027         unsigned long v;
2028
2029         v = apic_read(APIC_LVT0);
2030         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2031 }
2032
2033 static void disable_lapic_irq (unsigned int irq)
2034 {
2035         unsigned long v;
2036
2037         v = apic_read(APIC_LVT0);
2038         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2039 }
2040
2041 static void ack_lapic_irq (unsigned int irq)
2042 {
2043         ack_APIC_irq();
2044 }
2045
2046 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2047
2048 static struct hw_interrupt_type lapic_irq_type = {
2049         .typename       = "local-APIC-edge",
2050         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2051         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2052         .enable         = enable_lapic_irq,
2053         .disable        = disable_lapic_irq,
2054         .ack            = ack_lapic_irq,
2055         .end            = end_lapic_irq
2056 };
2057
2058 static void setup_nmi (void)
2059 {
2060         /*
2061          * Dirty trick to enable the NMI watchdog ...
2062          * We put the 8259A master into AEOI mode and
2063          * unmask on all local APICs LVT0 as NMI.
2064          *
2065          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2066          * is from Maciej W. Rozycki - so we do not have to EOI from
2067          * the NMI handler or the timer interrupt.
2068          */ 
2069         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2070
2071         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2072
2073         apic_printk(APIC_VERBOSE, " done.\n");
2074 }
2075
2076 /*
2077  * This looks a bit hackish but it's about the only one way of sending
2078  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2079  * not support the ExtINT mode, unfortunately.  We need to send these
2080  * cycles as some i82489DX-based boards have glue logic that keeps the
2081  * 8259A interrupt line asserted until INTA.  --macro
2082  */
2083 static inline void unlock_ExtINT_logic(void)
2084 {
2085         int pin, i;
2086         struct IO_APIC_route_entry entry0, entry1;
2087         unsigned char save_control, save_freq_select;
2088         unsigned long flags;
2089
2090         pin = find_isa_irq_pin(8, mp_INT);
2091         if (pin == -1)
2092                 return;
2093
2094         spin_lock_irqsave(&ioapic_lock, flags);
2095         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2096         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2097         spin_unlock_irqrestore(&ioapic_lock, flags);
2098         clear_IO_APIC_pin(0, pin);
2099
2100         memset(&entry1, 0, sizeof(entry1));
2101
2102         entry1.dest_mode = 0;                   /* physical delivery */
2103         entry1.mask = 0;                        /* unmask IRQ now */
2104         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2105         entry1.delivery_mode = dest_ExtINT;
2106         entry1.polarity = entry0.polarity;
2107         entry1.trigger = 0;
2108         entry1.vector = 0;
2109
2110         spin_lock_irqsave(&ioapic_lock, flags);
2111         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2112         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2113         spin_unlock_irqrestore(&ioapic_lock, flags);
2114
2115         save_control = CMOS_READ(RTC_CONTROL);
2116         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2117         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2118                    RTC_FREQ_SELECT);
2119         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2120
2121         i = 100;
2122         while (i-- > 0) {
2123                 mdelay(10);
2124                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2125                         i -= 10;
2126         }
2127
2128         CMOS_WRITE(save_control, RTC_CONTROL);
2129         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2130         clear_IO_APIC_pin(0, pin);
2131
2132         spin_lock_irqsave(&ioapic_lock, flags);
2133         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2134         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2135         spin_unlock_irqrestore(&ioapic_lock, flags);
2136 }
2137
2138 /*
2139  * This code may look a bit paranoid, but it's supposed to cooperate with
2140  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2141  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2142  * fanatically on his truly buggy board.
2143  */
2144 static inline void check_timer(void)
2145 {
2146         int pin1, pin2;
2147         int vector;
2148
2149         /*
2150          * get/set the timer IRQ vector:
2151          */
2152         disable_8259A_irq(0);
2153         vector = assign_irq_vector(0);
2154         set_intr_gate(vector, interrupt[0]);
2155
2156         /*
2157          * Subtle, code in do_timer_interrupt() expects an AEOI
2158          * mode for the 8259A whenever interrupts are routed
2159          * through I/O APICs.  Also IRQ0 has to be enabled in
2160          * the 8259A which implies the virtual wire has to be
2161          * disabled in the local APIC.
2162          */
2163         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2164         init_8259A(1);
2165         timer_ack = 1;
2166         enable_8259A_irq(0);
2167
2168         pin1 = find_isa_irq_pin(0, mp_INT);
2169         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2170
2171         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2172
2173         if (pin1 != -1) {
2174                 /*
2175                  * Ok, does IRQ0 through the IOAPIC work?
2176                  */
2177                 unmask_IO_APIC_irq(0);
2178                 if (timer_irq_works()) {
2179                         if (nmi_watchdog == NMI_IO_APIC) {
2180                                 disable_8259A_irq(0);
2181                                 setup_nmi();
2182                                 enable_8259A_irq(0);
2183                         }
2184                         return;
2185                 }
2186                 clear_IO_APIC_pin(0, pin1);
2187                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2188         }
2189
2190         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2191         if (pin2 != -1) {
2192                 printk("\n..... (found pin %d) ...", pin2);
2193                 /*
2194                  * legacy devices should be connected to IO APIC #0
2195                  */
2196                 setup_ExtINT_IRQ0_pin(pin2, vector);
2197                 if (timer_irq_works()) {
2198                         printk("works.\n");
2199                         if (pin1 != -1)
2200                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2201                         else
2202                                 add_pin_to_irq(0, 0, pin2);
2203                         if (nmi_watchdog == NMI_IO_APIC) {
2204                                 setup_nmi();
2205                         }
2206                         return;
2207                 }
2208                 /*
2209                  * Cleanup, just in case ...
2210                  */
2211                 clear_IO_APIC_pin(0, pin2);
2212         }
2213         printk(" failed.\n");
2214
2215         if (nmi_watchdog == NMI_IO_APIC) {
2216                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2217                 nmi_watchdog = 0;
2218         }
2219
2220         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2221
2222         disable_8259A_irq(0);
2223         irq_desc[0].handler = &lapic_irq_type;
2224         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2225         enable_8259A_irq(0);
2226
2227         if (timer_irq_works()) {
2228                 printk(" works.\n");
2229                 return;
2230         }
2231         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2232         printk(" failed.\n");
2233
2234         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2235
2236         timer_ack = 0;
2237         init_8259A(0);
2238         make_8259A_irq(0);
2239         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2240
2241         unlock_ExtINT_logic();
2242
2243         if (timer_irq_works()) {
2244                 printk(" works.\n");
2245                 return;
2246         }
2247         printk(" failed :(.\n");
2248         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2249                 "report.  Then try booting with the 'noapic' option");
2250 }
2251
2252 /*
2253  *
2254  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2255  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2256  *   Linux doesn't really care, as it's not actually used
2257  *   for any interrupt handling anyway.
2258  */
2259 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2260
2261 void __init setup_IO_APIC(void)
2262 {
2263         enable_IO_APIC();
2264
2265         if (acpi_ioapic)
2266                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2267         else
2268                 io_apic_irqs = ~PIC_IRQS;
2269
2270         printk("ENABLING IO-APIC IRQs\n");
2271
2272         /*
2273          * Set up IO-APIC IRQ routing.
2274          */
2275         if (!acpi_ioapic)
2276                 setup_ioapic_ids_from_mpc();
2277         sync_Arb_IDs();
2278         setup_IO_APIC_irqs();
2279         init_IO_APIC_traps();
2280         check_timer();
2281         if (!acpi_ioapic)
2282                 print_IO_APIC();
2283 }
2284
2285 /*
2286  *      Called after all the initialization is done. If we didnt find any
2287  *      APIC bugs then we can allow the modify fast path
2288  */
2289  
2290 static int __init io_apic_bug_finalize(void)
2291 {
2292         if(sis_apic_bug == -1)
2293                 sis_apic_bug = 0;
2294         return 0;
2295 }
2296
2297 late_initcall(io_apic_bug_finalize);
2298
2299 struct sysfs_ioapic_data {
2300         struct sys_device dev;
2301         struct IO_APIC_route_entry entry[0];
2302 };
2303 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2304
2305 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2306 {
2307         struct IO_APIC_route_entry *entry;
2308         struct sysfs_ioapic_data *data;
2309         unsigned long flags;
2310         int i;
2311         
2312         data = container_of(dev, struct sysfs_ioapic_data, dev);
2313         entry = data->entry;
2314         spin_lock_irqsave(&ioapic_lock, flags);
2315         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2316                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2317                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2318         }
2319         spin_unlock_irqrestore(&ioapic_lock, flags);
2320
2321         return 0;
2322 }
2323
2324 static int ioapic_resume(struct sys_device *dev)
2325 {
2326         struct IO_APIC_route_entry *entry;
2327         struct sysfs_ioapic_data *data;
2328         unsigned long flags;
2329         union IO_APIC_reg_00 reg_00;
2330         int i;
2331         
2332         data = container_of(dev, struct sysfs_ioapic_data, dev);
2333         entry = data->entry;
2334
2335         spin_lock_irqsave(&ioapic_lock, flags);
2336         reg_00.raw = io_apic_read(dev->id, 0);
2337         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2338                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2339                 io_apic_write(dev->id, 0, reg_00.raw);
2340         }
2341         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2342                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2343                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2344         }
2345         spin_unlock_irqrestore(&ioapic_lock, flags);
2346
2347         return 0;
2348 }
2349
2350 static struct sysdev_class ioapic_sysdev_class = {
2351         set_kset_name("ioapic"),
2352         .suspend = ioapic_suspend,
2353         .resume = ioapic_resume,
2354 };
2355
2356 static int __init ioapic_init_sysfs(void)
2357 {
2358         struct sys_device * dev;
2359         int i, size, error = 0;
2360
2361         error = sysdev_class_register(&ioapic_sysdev_class);
2362         if (error)
2363                 return error;
2364
2365         for (i = 0; i < nr_ioapics; i++ ) {
2366                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2367                         * sizeof(struct IO_APIC_route_entry);
2368                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2369                 if (!mp_ioapic_data[i]) {
2370                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2371                         continue;
2372                 }
2373                 memset(mp_ioapic_data[i], 0, size);
2374                 dev = &mp_ioapic_data[i]->dev;
2375                 dev->id = i; 
2376                 dev->cls = &ioapic_sysdev_class;
2377                 error = sysdev_register(dev);
2378                 if (error) {
2379                         kfree(mp_ioapic_data[i]);
2380                         mp_ioapic_data[i] = NULL;
2381                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2382                         continue;
2383                 }
2384         }
2385
2386         return 0;
2387 }
2388
2389 device_initcall(ioapic_init_sysfs);
2390
2391 /* --------------------------------------------------------------------------
2392                           ACPI-based IOAPIC Configuration
2393    -------------------------------------------------------------------------- */
2394
2395 #ifdef CONFIG_ACPI_BOOT
2396
2397 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2398 {
2399         union IO_APIC_reg_00 reg_00;
2400         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2401         physid_mask_t tmp;
2402         unsigned long flags;
2403         int i = 0;
2404
2405         /*
2406          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2407          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2408          * supports up to 16 on one shared APIC bus.
2409          * 
2410          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2411          *      advantage of new APIC bus architecture.
2412          */
2413
2414         if (physids_empty(apic_id_map))
2415                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2416
2417         spin_lock_irqsave(&ioapic_lock, flags);
2418         reg_00.raw = io_apic_read(ioapic, 0);
2419         spin_unlock_irqrestore(&ioapic_lock, flags);
2420
2421         if (apic_id >= get_physical_broadcast()) {
2422                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2423                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2424                 apic_id = reg_00.bits.ID;
2425         }
2426
2427         /*
2428          * Every APIC in a system must have a unique ID or we get lots of nice 
2429          * 'stuck on smp_invalidate_needed IPI wait' messages.
2430          */
2431         if (check_apicid_used(apic_id_map, apic_id)) {
2432
2433                 for (i = 0; i < get_physical_broadcast(); i++) {
2434                         if (!check_apicid_used(apic_id_map, i))
2435                                 break;
2436                 }
2437
2438                 if (i == get_physical_broadcast())
2439                         panic("Max apic_id exceeded!\n");
2440
2441                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2442                         "trying %d\n", ioapic, apic_id, i);
2443
2444                 apic_id = i;
2445         } 
2446
2447         tmp = apicid_to_cpu_present(apic_id);
2448         physids_or(apic_id_map, apic_id_map, tmp);
2449
2450         if (reg_00.bits.ID != apic_id) {
2451                 reg_00.bits.ID = apic_id;
2452
2453                 spin_lock_irqsave(&ioapic_lock, flags);
2454                 io_apic_write(ioapic, 0, reg_00.raw);
2455                 reg_00.raw = io_apic_read(ioapic, 0);
2456                 spin_unlock_irqrestore(&ioapic_lock, flags);
2457
2458                 /* Sanity check */
2459                 if (reg_00.bits.ID != apic_id)
2460                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2461         }
2462
2463         apic_printk(APIC_VERBOSE, KERN_INFO
2464                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2465
2466         return apic_id;
2467 }
2468
2469
2470 int __init io_apic_get_version (int ioapic)
2471 {
2472         union IO_APIC_reg_01    reg_01;
2473         unsigned long flags;
2474
2475         spin_lock_irqsave(&ioapic_lock, flags);
2476         reg_01.raw = io_apic_read(ioapic, 1);
2477         spin_unlock_irqrestore(&ioapic_lock, flags);
2478
2479         return reg_01.bits.version;
2480 }
2481
2482
2483 int __init io_apic_get_redir_entries (int ioapic)
2484 {
2485         union IO_APIC_reg_01    reg_01;
2486         unsigned long flags;
2487
2488         spin_lock_irqsave(&ioapic_lock, flags);
2489         reg_01.raw = io_apic_read(ioapic, 1);
2490         spin_unlock_irqrestore(&ioapic_lock, flags);
2491
2492         return reg_01.bits.entries;
2493 }
2494
2495
2496 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2497 {
2498         struct IO_APIC_route_entry entry;
2499         unsigned long flags;
2500
2501         if (!IO_APIC_IRQ(irq)) {
2502                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2503                         ioapic);
2504                 return -EINVAL;
2505         }
2506
2507         /*
2508          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2509          * Note that we mask (disable) IRQs now -- these get enabled when the
2510          * corresponding device driver registers for this IRQ.
2511          */
2512
2513         memset(&entry,0,sizeof(entry));
2514
2515         entry.delivery_mode = INT_DELIVERY_MODE;
2516         entry.dest_mode = INT_DEST_MODE;
2517         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2518         entry.trigger = edge_level;
2519         entry.polarity = active_high_low;
2520         entry.mask  = 1;
2521
2522         /*
2523          * IRQs < 16 are already in the irq_2_pin[] map
2524          */
2525         if (irq >= 16)
2526                 add_pin_to_irq(irq, ioapic, pin);
2527
2528         entry.vector = assign_irq_vector(irq);
2529
2530         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2531                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2532                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2533                 edge_level, active_high_low);
2534
2535         ioapic_register_intr(irq, entry.vector, edge_level);
2536
2537         if (!ioapic && (irq < 16))
2538                 disable_8259A_irq(irq);
2539
2540         spin_lock_irqsave(&ioapic_lock, flags);
2541         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2542         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2543         spin_unlock_irqrestore(&ioapic_lock, flags);
2544
2545         return 0;
2546 }
2547
2548 #endif /*CONFIG_ACPI_BOOT*/