Blackfin arch: Fix Bug - System with EMAC driver enabled - Core not idling
[linux-2.6.git] / arch / blackfin / mach-common / dpmc_modes.S
1 /*
2  * Copyright 2004-2008 Analog Devices Inc.
3  *
4  * Licensed under the GPL-2 or later.
5  */
6
7 #include <linux/linkage.h>
8 #include <asm/blackfin.h>
9 #include <asm/mach/irq.h>
10 #include <asm/dpmc.h>
11
12 .section .l1.text
13
14 ENTRY(_sleep_mode)
15         [--SP] = ( R7:0, P5:0 );
16         [--SP] =  RETS;
17
18         call _set_sic_iwr;
19
20         R0 = 0xFFFF (Z);
21         call _set_rtc_istat;
22
23         P0.H = hi(PLL_CTL);
24         P0.L = lo(PLL_CTL);
25         R1 = W[P0](z);
26         BITSET (R1, 3);
27         W[P0] = R1.L;
28
29         CLI R2;
30         SSYNC;
31         IDLE;
32         STI R2;
33
34         call _test_pll_locked;
35
36         R0 = IWR_ENABLE(0);
37         R1 = IWR_DISABLE_ALL;
38         R2 = IWR_DISABLE_ALL;
39
40         call _set_sic_iwr;
41
42         P0.H = hi(PLL_CTL);
43         P0.L = lo(PLL_CTL);
44         R7 = w[p0](z);
45         BITCLR (R7, 3);
46         BITCLR (R7, 5);
47         w[p0] = R7.L;
48         IDLE;
49         call _test_pll_locked;
50
51         RETS = [SP++];
52         ( R7:0, P5:0 ) = [SP++];
53         RTS;
54 ENDPROC(_sleep_mode)
55
56 ENTRY(_hibernate_mode)
57         [--SP] = ( R7:0, P5:0 );
58         [--SP] =  RETS;
59
60         R3 = R0;
61         R0 = IWR_DISABLE_ALL;
62         R1 = IWR_DISABLE_ALL;
63         R2 = IWR_DISABLE_ALL;
64         call _set_sic_iwr;
65         call _set_dram_srfs;
66         SSYNC;
67
68         R0 = 0xFFFF (Z);
69         call _set_rtc_istat;
70
71         P0.H = hi(VR_CTL);
72         P0.L = lo(VR_CTL);
73
74         W[P0] = R3.L;
75         CLI R2;
76         IDLE;
77 .Lforever:
78         jump .Lforever;
79 ENDPROC(_hibernate_mode)
80
81 ENTRY(_sleep_deeper)
82         [--SP] = ( R7:0, P5:0 );
83         [--SP] =  RETS;
84
85         CLI R4;
86
87         P3 = R0;
88         P4 = R1;
89         P5 = R2;
90
91         R0 = IWR_ENABLE(0);
92         R1 = IWR_DISABLE_ALL;
93         R2 = IWR_DISABLE_ALL;
94
95         call _set_sic_iwr;
96         call _set_dram_srfs;    /* Set SDRAM Self Refresh */
97
98         /* Clear all the interrupts,bits sticky */
99         R0 = 0xFFFF (Z);
100         call _set_rtc_istat;
101         P0.H = hi(PLL_DIV);
102         P0.L = lo(PLL_DIV);
103         R6 = W[P0](z);
104         R0.L = 0xF;
105         W[P0] = R0.l;           /* Set Max VCO to SCLK divider */
106
107         P0.H = hi(PLL_CTL);
108         P0.L = lo(PLL_CTL);
109         R5 = W[P0](z);
110         R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
111         W[P0] = R0.l;           /* Set Min CLKIN to VCO multiplier */
112
113         SSYNC;
114         IDLE;
115
116         call _test_pll_locked;
117
118         P0.H = hi(VR_CTL);
119         P0.L = lo(VR_CTL);
120         R7 = W[P0](z);
121         R1 = 0x6;
122         R1 <<= 16;
123         R2 = 0x0404(Z);
124         R1 = R1|R2;
125
126         R2 = DEPOSIT(R7, R1);
127         W[P0] = R2;             /* Set Min Core Voltage */
128
129         SSYNC;
130         IDLE;
131
132         call _test_pll_locked;
133
134         R0 = P3;
135         R1 = P4;
136         R3 = P5;
137         call _set_sic_iwr;      /* Set Awake from IDLE */
138
139         P0.H = hi(PLL_CTL);
140         P0.L = lo(PLL_CTL);
141         R0 = W[P0](z);
142         BITSET (R0, 3);
143         W[P0] = R0.L;           /* Turn CCLK OFF */
144         SSYNC;
145         IDLE;
146
147         call _test_pll_locked;
148
149         R0 = IWR_ENABLE(0);
150         R1 = IWR_DISABLE_ALL;
151         R2 = IWR_DISABLE_ALL;
152
153         call _set_sic_iwr;      /* Set Awake from IDLE PLL */
154
155         P0.H = hi(VR_CTL);
156         P0.L = lo(VR_CTL);
157         W[P0]= R7;
158
159         SSYNC;
160         IDLE;
161
162         call _test_pll_locked;
163
164         P0.H = hi(PLL_DIV);
165         P0.L = lo(PLL_DIV);
166         W[P0]= R6;              /* Restore CCLK and SCLK divider */
167
168         P0.H = hi(PLL_CTL);
169         P0.L = lo(PLL_CTL);
170         w[p0] = R5;             /* Restore VCO multiplier */
171         IDLE;
172         call _test_pll_locked;
173
174         call _unset_dram_srfs;  /* SDRAM Self Refresh Off */
175
176         STI R4;
177
178         RETS = [SP++];
179         ( R7:0, P5:0 ) = [SP++];
180         RTS;
181 ENDPROC(_sleep_deeper)
182
183 ENTRY(_set_dram_srfs)
184         /*  set the dram to self refresh mode */
185         SSYNC;
186 #if defined(EBIU_RSTCTL)        /* DDR */
187         P0.H = hi(EBIU_RSTCTL);
188         P0.L = lo(EBIU_RSTCTL);
189         R2 = [P0];
190         BITSET(R2, 3); /* SRREQ enter self-refresh mode */
191         [P0] = R2;
192         SSYNC;
193 1:
194         R2 = [P0];
195         CC = BITTST(R2, 4);
196         if !CC JUMP 1b;
197 #else                           /* SDRAM */
198         P0.L = lo(EBIU_SDGCTL);
199         P0.H = hi(EBIU_SDGCTL);
200         R2 = [P0];
201         BITSET(R2, 24); /* SRFS enter self-refresh mode */
202         [P0] = R2;
203         SSYNC;
204
205         P0.L = lo(EBIU_SDSTAT);
206         P0.H = hi(EBIU_SDSTAT);
207 1:
208         R2 = w[P0];
209         SSYNC;
210         cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
211         if !cc jump 1b;
212
213         P0.L = lo(EBIU_SDGCTL);
214         P0.H = hi(EBIU_SDGCTL);
215         R2 = [P0];
216         BITCLR(R2, 0); /* SCTLE disable CLKOUT */
217         [P0] = R2;
218 #endif
219         RTS;
220 ENDPROC(_set_dram_srfs)
221
222 ENTRY(_unset_dram_srfs)
223         /*  set the dram out of self refresh mode */
224 #if defined(EBIU_RSTCTL)        /* DDR */
225         P0.H = hi(EBIU_RSTCTL);
226         P0.L = lo(EBIU_RSTCTL);
227         R2 = [P0];
228         BITCLR(R2, 3); /* clear SRREQ bit */
229         [P0] = R2;
230 #elif defined(EBIU_SDGCTL)      /* SDRAM */
231
232         P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
233         P0.H = hi(EBIU_SDGCTL);
234         R2 = [P0];
235         BITSET(R2, 0); /* SCTLE enable CLKOUT */
236         [P0] = R2
237         SSYNC;
238
239         P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
240         P0.H = hi(EBIU_SDGCTL);
241         R2 = [P0];
242         BITCLR(R2, 24); /* clear SRFS bit */
243         [P0] = R2
244 #endif
245         SSYNC;
246         RTS;
247 ENDPROC(_unset_dram_srfs)
248
249 ENTRY(_set_sic_iwr)
250 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
251         P0.H = hi(SIC_IWR0);
252         P0.L = lo(SIC_IWR0);
253         P1.H = hi(SIC_IWR1);
254         P1.L = lo(SIC_IWR1);
255         [P1] = R1;
256 #if defined(CONFIG_BF54x)
257         P1.H = hi(SIC_IWR2);
258         P1.L = lo(SIC_IWR2);
259         [P1] = R2;
260 #endif
261 #else
262         P0.H = hi(SIC_IWR);
263         P0.L = lo(SIC_IWR);
264 #endif
265         [P0] = R0;
266
267         SSYNC;
268         RTS;
269 ENDPROC(_set_sic_iwr)
270
271 ENTRY(_set_rtc_istat)
272 #ifndef CONFIG_BF561
273         P0.H = hi(RTC_ISTAT);
274         P0.L = lo(RTC_ISTAT);
275         w[P0] = R0.L;
276         SSYNC;
277 #elif (ANOMALY_05000371)
278         nop;
279         nop;
280         nop;
281         nop;
282 #endif
283         RTS;
284 ENDPROC(_set_rtc_istat)
285
286 ENTRY(_test_pll_locked)
287         P0.H = hi(PLL_STAT);
288         P0.L = lo(PLL_STAT);
289 1:
290         R0 = W[P0] (Z);
291         CC = BITTST(R0,5);
292         IF !CC JUMP 1b;
293         RTS;
294 ENDPROC(_test_pll_locked)
295
296 .section .text
297
298 ENTRY(_do_hibernate)
299         [--SP] = ( R7:0, P5:0 );
300         [--SP] =  RETS;
301         /* Save System MMRs */
302         R2 = R0;
303         P0.H = hi(PLL_CTL);
304         P0.L = lo(PLL_CTL);
305
306 #ifdef SIC_IMASK0
307         PM_SYS_PUSH(SIC_IMASK0)
308 #endif
309 #ifdef SIC_IMASK1
310         PM_SYS_PUSH(SIC_IMASK1)
311 #endif
312 #ifdef SIC_IMASK2
313         PM_SYS_PUSH(SIC_IMASK2)
314 #endif
315 #ifdef SIC_IMASK
316         PM_SYS_PUSH(SIC_IMASK)
317 #endif
318 #ifdef SICA_IMASK0
319         PM_SYS_PUSH(SICA_IMASK0)
320 #endif
321 #ifdef SICA_IMASK1
322         PM_SYS_PUSH(SICA_IMASK1)
323 #endif
324 #ifdef SIC_IAR2
325         PM_SYS_PUSH(SIC_IAR0)
326         PM_SYS_PUSH(SIC_IAR1)
327         PM_SYS_PUSH(SIC_IAR2)
328 #endif
329 #ifdef SIC_IAR3
330         PM_SYS_PUSH(SIC_IAR3)
331 #endif
332 #ifdef SIC_IAR4
333         PM_SYS_PUSH(SIC_IAR4)
334         PM_SYS_PUSH(SIC_IAR5)
335         PM_SYS_PUSH(SIC_IAR6)
336 #endif
337 #ifdef SIC_IAR7
338         PM_SYS_PUSH(SIC_IAR7)
339 #endif
340 #ifdef SIC_IAR8
341         PM_SYS_PUSH(SIC_IAR8)
342         PM_SYS_PUSH(SIC_IAR9)
343         PM_SYS_PUSH(SIC_IAR10)
344         PM_SYS_PUSH(SIC_IAR11)
345 #endif
346
347 #ifdef SICA_IAR0
348         PM_SYS_PUSH(SICA_IAR0)
349         PM_SYS_PUSH(SICA_IAR1)
350         PM_SYS_PUSH(SICA_IAR2)
351         PM_SYS_PUSH(SICA_IAR3)
352         PM_SYS_PUSH(SICA_IAR4)
353         PM_SYS_PUSH(SICA_IAR5)
354         PM_SYS_PUSH(SICA_IAR6)
355         PM_SYS_PUSH(SICA_IAR7)
356 #endif
357
358 #ifdef SIC_IWR
359         PM_SYS_PUSH(SIC_IWR)
360 #endif
361 #ifdef SIC_IWR0
362         PM_SYS_PUSH(SIC_IWR0)
363 #endif
364 #ifdef SIC_IWR1
365         PM_SYS_PUSH(SIC_IWR1)
366 #endif
367 #ifdef SIC_IWR2
368         PM_SYS_PUSH(SIC_IWR2)
369 #endif
370 #ifdef SICA_IWR0
371         PM_SYS_PUSH(SICA_IWR0)
372 #endif
373 #ifdef SICA_IWR1
374         PM_SYS_PUSH(SICA_IWR1)
375 #endif
376
377 #ifdef PINT0_ASSIGN
378         PM_SYS_PUSH(PINT0_ASSIGN)
379         PM_SYS_PUSH(PINT1_ASSIGN)
380         PM_SYS_PUSH(PINT2_ASSIGN)
381         PM_SYS_PUSH(PINT3_ASSIGN)
382 #endif
383
384         PM_SYS_PUSH(EBIU_AMBCTL0)
385         PM_SYS_PUSH(EBIU_AMBCTL1)
386         PM_SYS_PUSH16(EBIU_AMGCTL)
387
388 #ifdef EBIU_FCTL
389         PM_SYS_PUSH(EBIU_MBSCTL)
390         PM_SYS_PUSH(EBIU_MODE)
391         PM_SYS_PUSH(EBIU_FCTL)
392 #endif
393
394         PM_SYS_PUSH16(SYSCR)
395
396         /* Save Core MMRs */
397         P0.H = hi(SRAM_BASE_ADDRESS);
398         P0.L = lo(SRAM_BASE_ADDRESS);
399
400         PM_PUSH(DMEM_CONTROL)
401         PM_PUSH(DCPLB_ADDR0)
402         PM_PUSH(DCPLB_ADDR1)
403         PM_PUSH(DCPLB_ADDR2)
404         PM_PUSH(DCPLB_ADDR3)
405         PM_PUSH(DCPLB_ADDR4)
406         PM_PUSH(DCPLB_ADDR5)
407         PM_PUSH(DCPLB_ADDR6)
408         PM_PUSH(DCPLB_ADDR7)
409         PM_PUSH(DCPLB_ADDR8)
410         PM_PUSH(DCPLB_ADDR9)
411         PM_PUSH(DCPLB_ADDR10)
412         PM_PUSH(DCPLB_ADDR11)
413         PM_PUSH(DCPLB_ADDR12)
414         PM_PUSH(DCPLB_ADDR13)
415         PM_PUSH(DCPLB_ADDR14)
416         PM_PUSH(DCPLB_ADDR15)
417         PM_PUSH(DCPLB_DATA0)
418         PM_PUSH(DCPLB_DATA1)
419         PM_PUSH(DCPLB_DATA2)
420         PM_PUSH(DCPLB_DATA3)
421         PM_PUSH(DCPLB_DATA4)
422         PM_PUSH(DCPLB_DATA5)
423         PM_PUSH(DCPLB_DATA6)
424         PM_PUSH(DCPLB_DATA7)
425         PM_PUSH(DCPLB_DATA8)
426         PM_PUSH(DCPLB_DATA9)
427         PM_PUSH(DCPLB_DATA10)
428         PM_PUSH(DCPLB_DATA11)
429         PM_PUSH(DCPLB_DATA12)
430         PM_PUSH(DCPLB_DATA13)
431         PM_PUSH(DCPLB_DATA14)
432         PM_PUSH(DCPLB_DATA15)
433         PM_PUSH(IMEM_CONTROL)
434         PM_PUSH(ICPLB_ADDR0)
435         PM_PUSH(ICPLB_ADDR1)
436         PM_PUSH(ICPLB_ADDR2)
437         PM_PUSH(ICPLB_ADDR3)
438         PM_PUSH(ICPLB_ADDR4)
439         PM_PUSH(ICPLB_ADDR5)
440         PM_PUSH(ICPLB_ADDR6)
441         PM_PUSH(ICPLB_ADDR7)
442         PM_PUSH(ICPLB_ADDR8)
443         PM_PUSH(ICPLB_ADDR9)
444         PM_PUSH(ICPLB_ADDR10)
445         PM_PUSH(ICPLB_ADDR11)
446         PM_PUSH(ICPLB_ADDR12)
447         PM_PUSH(ICPLB_ADDR13)
448         PM_PUSH(ICPLB_ADDR14)
449         PM_PUSH(ICPLB_ADDR15)
450         PM_PUSH(ICPLB_DATA0)
451         PM_PUSH(ICPLB_DATA1)
452         PM_PUSH(ICPLB_DATA2)
453         PM_PUSH(ICPLB_DATA3)
454         PM_PUSH(ICPLB_DATA4)
455         PM_PUSH(ICPLB_DATA5)
456         PM_PUSH(ICPLB_DATA6)
457         PM_PUSH(ICPLB_DATA7)
458         PM_PUSH(ICPLB_DATA8)
459         PM_PUSH(ICPLB_DATA9)
460         PM_PUSH(ICPLB_DATA10)
461         PM_PUSH(ICPLB_DATA11)
462         PM_PUSH(ICPLB_DATA12)
463         PM_PUSH(ICPLB_DATA13)
464         PM_PUSH(ICPLB_DATA14)
465         PM_PUSH(ICPLB_DATA15)
466         PM_PUSH(EVT0)
467         PM_PUSH(EVT1)
468         PM_PUSH(EVT2)
469         PM_PUSH(EVT3)
470         PM_PUSH(EVT4)
471         PM_PUSH(EVT5)
472         PM_PUSH(EVT6)
473         PM_PUSH(EVT7)
474         PM_PUSH(EVT8)
475         PM_PUSH(EVT9)
476         PM_PUSH(EVT10)
477         PM_PUSH(EVT11)
478         PM_PUSH(EVT12)
479         PM_PUSH(EVT13)
480         PM_PUSH(EVT14)
481         PM_PUSH(EVT15)
482         PM_PUSH(IMASK)
483         PM_PUSH(ILAT)
484         PM_PUSH(IPRIO)
485         PM_PUSH(TCNTL)
486         PM_PUSH(TPERIOD)
487         PM_PUSH(TSCALE)
488         PM_PUSH(TCOUNT)
489         PM_PUSH(TBUFCTL)
490
491         /* Save Core Registers */
492         [--sp] = SYSCFG;
493         [--sp] = ( R7:0, P5:0 );
494         [--sp] = fp;
495         [--sp] = usp;
496
497         [--sp] = i0;
498         [--sp] = i1;
499         [--sp] = i2;
500         [--sp] = i3;
501
502         [--sp] = m0;
503         [--sp] = m1;
504         [--sp] = m2;
505         [--sp] = m3;
506
507         [--sp] = l0;
508         [--sp] = l1;
509         [--sp] = l2;
510         [--sp] = l3;
511
512         [--sp] = b0;
513         [--sp] = b1;
514         [--sp] = b2;
515         [--sp] = b3;
516         [--sp] = a0.x;
517         [--sp] = a0.w;
518         [--sp] = a1.x;
519         [--sp] = a1.w;
520
521         [--sp] = LC0;
522         [--sp] = LC1;
523         [--sp] = LT0;
524         [--sp] = LT1;
525         [--sp] = LB0;
526         [--sp] = LB1;
527
528         [--sp] = ASTAT;
529         [--sp] = CYCLES;
530         [--sp] = CYCLES2;
531
532         [--sp] = RETS;
533         r0 = RETI;
534         [--sp] = r0;
535         [--sp] = RETX;
536         [--sp] = RETN;
537         [--sp] = RETE;
538         [--sp] = SEQSTAT;
539
540         /* Save Magic, return address and Stack Pointer */
541         P0.H = 0;
542         P0.L = 0;
543         R0.H = 0xDEAD;  /* Hibernate Magic */
544         R0.L = 0xBEEF;
545         [P0++] = R0;    /* Store Hibernate Magic */
546         R0.H = .Lpm_resume_here;
547         R0.L = .Lpm_resume_here;
548         [P0++] = R0;    /* Save Return Address */
549         [P0++] = SP;    /* Save Stack Pointer */
550         P0.H = _hibernate_mode;
551         P0.L = _hibernate_mode;
552         R0 = R2;
553         call (P0); /* Goodbye */
554
555 .Lpm_resume_here:
556
557         /* Restore Core Registers */
558         SEQSTAT = [sp++];
559         RETE = [sp++];
560         RETN = [sp++];
561         RETX = [sp++];
562         r0 = [sp++];
563         RETI = r0;
564         RETS = [sp++];
565
566         CYCLES2 = [sp++];
567         CYCLES = [sp++];
568         ASTAT = [sp++];
569
570         LB1 = [sp++];
571         LB0 = [sp++];
572         LT1 = [sp++];
573         LT0 = [sp++];
574         LC1 = [sp++];
575         LC0 = [sp++];
576
577         a1.w = [sp++];
578         a1.x = [sp++];
579         a0.w = [sp++];
580         a0.x = [sp++];
581         b3 = [sp++];
582         b2 = [sp++];
583         b1 = [sp++];
584         b0 = [sp++];
585
586         l3 = [sp++];
587         l2 = [sp++];
588         l1 = [sp++];
589         l0 = [sp++];
590
591         m3 = [sp++];
592         m2 = [sp++];
593         m1 = [sp++];
594         m0 = [sp++];
595
596         i3 = [sp++];
597         i2 = [sp++];
598         i1 = [sp++];
599         i0 = [sp++];
600
601         usp = [sp++];
602         fp = [sp++];
603
604         ( R7 : 0, P5 : 0) = [ SP ++ ];
605         SYSCFG = [sp++];
606
607         /* Restore Core MMRs */
608
609         PM_POP(TBUFCTL)
610         PM_POP(TCOUNT)
611         PM_POP(TSCALE)
612         PM_POP(TPERIOD)
613         PM_POP(TCNTL)
614         PM_POP(IPRIO)
615         PM_POP(ILAT)
616         PM_POP(IMASK)
617         PM_POP(EVT15)
618         PM_POP(EVT14)
619         PM_POP(EVT13)
620         PM_POP(EVT12)
621         PM_POP(EVT11)
622         PM_POP(EVT10)
623         PM_POP(EVT9)
624         PM_POP(EVT8)
625         PM_POP(EVT7)
626         PM_POP(EVT6)
627         PM_POP(EVT5)
628         PM_POP(EVT4)
629         PM_POP(EVT3)
630         PM_POP(EVT2)
631         PM_POP(EVT1)
632         PM_POP(EVT0)
633         PM_POP(ICPLB_DATA15)
634         PM_POP(ICPLB_DATA14)
635         PM_POP(ICPLB_DATA13)
636         PM_POP(ICPLB_DATA12)
637         PM_POP(ICPLB_DATA11)
638         PM_POP(ICPLB_DATA10)
639         PM_POP(ICPLB_DATA9)
640         PM_POP(ICPLB_DATA8)
641         PM_POP(ICPLB_DATA7)
642         PM_POP(ICPLB_DATA6)
643         PM_POP(ICPLB_DATA5)
644         PM_POP(ICPLB_DATA4)
645         PM_POP(ICPLB_DATA3)
646         PM_POP(ICPLB_DATA2)
647         PM_POP(ICPLB_DATA1)
648         PM_POP(ICPLB_DATA0)
649         PM_POP(ICPLB_ADDR15)
650         PM_POP(ICPLB_ADDR14)
651         PM_POP(ICPLB_ADDR13)
652         PM_POP(ICPLB_ADDR12)
653         PM_POP(ICPLB_ADDR11)
654         PM_POP(ICPLB_ADDR10)
655         PM_POP(ICPLB_ADDR9)
656         PM_POP(ICPLB_ADDR8)
657         PM_POP(ICPLB_ADDR7)
658         PM_POP(ICPLB_ADDR6)
659         PM_POP(ICPLB_ADDR5)
660         PM_POP(ICPLB_ADDR4)
661         PM_POP(ICPLB_ADDR3)
662         PM_POP(ICPLB_ADDR2)
663         PM_POP(ICPLB_ADDR1)
664         PM_POP(ICPLB_ADDR0)
665         PM_POP(IMEM_CONTROL)
666         PM_POP(DCPLB_DATA15)
667         PM_POP(DCPLB_DATA14)
668         PM_POP(DCPLB_DATA13)
669         PM_POP(DCPLB_DATA12)
670         PM_POP(DCPLB_DATA11)
671         PM_POP(DCPLB_DATA10)
672         PM_POP(DCPLB_DATA9)
673         PM_POP(DCPLB_DATA8)
674         PM_POP(DCPLB_DATA7)
675         PM_POP(DCPLB_DATA6)
676         PM_POP(DCPLB_DATA5)
677         PM_POP(DCPLB_DATA4)
678         PM_POP(DCPLB_DATA3)
679         PM_POP(DCPLB_DATA2)
680         PM_POP(DCPLB_DATA1)
681         PM_POP(DCPLB_DATA0)
682         PM_POP(DCPLB_ADDR15)
683         PM_POP(DCPLB_ADDR14)
684         PM_POP(DCPLB_ADDR13)
685         PM_POP(DCPLB_ADDR12)
686         PM_POP(DCPLB_ADDR11)
687         PM_POP(DCPLB_ADDR10)
688         PM_POP(DCPLB_ADDR9)
689         PM_POP(DCPLB_ADDR8)
690         PM_POP(DCPLB_ADDR7)
691         PM_POP(DCPLB_ADDR6)
692         PM_POP(DCPLB_ADDR5)
693         PM_POP(DCPLB_ADDR4)
694         PM_POP(DCPLB_ADDR3)
695         PM_POP(DCPLB_ADDR2)
696         PM_POP(DCPLB_ADDR1)
697         PM_POP(DCPLB_ADDR0)
698         PM_POP(DMEM_CONTROL)
699
700         /* Restore System MMRs */
701
702         P0.H = hi(PLL_CTL);
703         P0.L = lo(PLL_CTL);
704         PM_SYS_POP16(SYSCR)
705
706 #ifdef EBIU_FCTL
707         PM_SYS_POP(EBIU_FCTL)
708         PM_SYS_POP(EBIU_MODE)
709         PM_SYS_POP(EBIU_MBSCTL)
710 #endif
711         PM_SYS_POP16(EBIU_AMGCTL)
712         PM_SYS_POP(EBIU_AMBCTL1)
713         PM_SYS_POP(EBIU_AMBCTL0)
714
715 #ifdef PINT0_ASSIGN
716         PM_SYS_POP(PINT3_ASSIGN)
717         PM_SYS_POP(PINT2_ASSIGN)
718         PM_SYS_POP(PINT1_ASSIGN)
719         PM_SYS_POP(PINT0_ASSIGN)
720 #endif
721
722 #ifdef SICA_IWR1
723         PM_SYS_POP(SICA_IWR1)
724 #endif
725 #ifdef SICA_IWR0
726         PM_SYS_POP(SICA_IWR0)
727 #endif
728 #ifdef SIC_IWR2
729         PM_SYS_POP(SIC_IWR2)
730 #endif
731 #ifdef SIC_IWR1
732         PM_SYS_POP(SIC_IWR1)
733 #endif
734 #ifdef SIC_IWR0
735         PM_SYS_POP(SIC_IWR0)
736 #endif
737 #ifdef SIC_IWR
738         PM_SYS_POP(SIC_IWR)
739 #endif
740
741 #ifdef SICA_IAR0
742         PM_SYS_POP(SICA_IAR7)
743         PM_SYS_POP(SICA_IAR6)
744         PM_SYS_POP(SICA_IAR5)
745         PM_SYS_POP(SICA_IAR4)
746         PM_SYS_POP(SICA_IAR3)
747         PM_SYS_POP(SICA_IAR2)
748         PM_SYS_POP(SICA_IAR1)
749         PM_SYS_POP(SICA_IAR0)
750 #endif
751
752 #ifdef SIC_IAR8
753         PM_SYS_POP(SIC_IAR11)
754         PM_SYS_POP(SIC_IAR10)
755         PM_SYS_POP(SIC_IAR9)
756         PM_SYS_POP(SIC_IAR8)
757 #endif
758 #ifdef SIC_IAR7
759         PM_SYS_POP(SIC_IAR7)
760 #endif
761 #ifdef SIC_IAR6
762         PM_SYS_POP(SIC_IAR6)
763         PM_SYS_POP(SIC_IAR5)
764         PM_SYS_POP(SIC_IAR4)
765 #endif
766 #ifdef SIC_IAR3
767         PM_SYS_POP(SIC_IAR3)
768 #endif
769 #ifdef SIC_IAR2
770         PM_SYS_POP(SIC_IAR2)
771         PM_SYS_POP(SIC_IAR1)
772         PM_SYS_POP(SIC_IAR0)
773 #endif
774 #ifdef SICA_IMASK1
775         PM_SYS_POP(SICA_IMASK1)
776 #endif
777 #ifdef SICA_IMASK0
778         PM_SYS_POP(SICA_IMASK0)
779 #endif
780 #ifdef SIC_IMASK
781         PM_SYS_POP(SIC_IMASK)
782 #endif
783 #ifdef SIC_IMASK2
784         PM_SYS_POP(SIC_IMASK2)
785 #endif
786 #ifdef SIC_IMASK1
787         PM_SYS_POP(SIC_IMASK1)
788 #endif
789 #ifdef SIC_IMASK0
790         PM_SYS_POP(SIC_IMASK0)
791 #endif
792
793         [--sp] = RETI;  /* Clear Global Interrupt Disable */
794         SP += 4;
795
796         RETS = [SP++];
797         ( R7:0, P5:0 ) = [SP++];
798         RTS;
799 ENDPROC(_do_hibernate)