Blackfin: SMP: don't start up core b until its state has been completely onlined
[linux-2.6.git] / arch / blackfin / mach-bf561 / smp.c
1 /*
2  * Copyright 2007-2009 Analog Devices Inc.
3  *               Philippe Gerum <rpm@xenomai.org>
4  *
5  * Licensed under the GPL-2 or later.
6  */
7
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/delay.h>
12 #include <asm/smp.h>
13 #include <asm/dma.h>
14
15 static DEFINE_SPINLOCK(boot_lock);
16
17 static cpumask_t cpu_callin_map;
18
19 /*
20  * platform_init_cpus() - Tell the world about how many cores we
21  * have. This is called while setting up the architecture support
22  * (setup_arch()), so don't be too demanding here with respect to
23  * available kernel services.
24  */
25
26 void __init platform_init_cpus(void)
27 {
28         cpu_set(0, cpu_possible_map); /* CoreA */
29         cpu_set(1, cpu_possible_map); /* CoreB */
30 }
31
32 void __init platform_prepare_cpus(unsigned int max_cpus)
33 {
34         int len;
35
36         len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
37         BUG_ON(len > L1_CODE_LENGTH);
38
39         dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
40
41         /* Both cores ought to be present on a bf561! */
42         cpu_set(0, cpu_present_map); /* CoreA */
43         cpu_set(1, cpu_present_map); /* CoreB */
44
45         printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
46 }
47
48 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
49 {
50         return -EINVAL;
51 }
52
53 void __cpuinit platform_secondary_init(unsigned int cpu)
54 {
55         /* Clone setup for peripheral interrupt sources from CoreA. */
56         bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
57         bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
58         SSYNC();
59
60         /* Clone setup for IARs from CoreA. */
61         bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
62         bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
63         bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
64         bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
65         bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
66         bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
67         bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
68         bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
69         SSYNC();
70
71         /* Store CPU-private information to the cpu_data array. */
72         bfin_setup_cpudata(cpu);
73
74         /* We are done with local CPU inits, unblock the boot CPU. */
75         cpu_set(cpu, cpu_callin_map);
76         spin_lock(&boot_lock);
77         spin_unlock(&boot_lock);
78 }
79
80 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
81 {
82         unsigned long timeout;
83
84         /* CoreB already running?! */
85         BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
86
87         printk(KERN_INFO "Booting Core B.\n");
88
89         spin_lock(&boot_lock);
90
91         /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
92         SSYNC();
93         bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
94         SSYNC();
95
96         timeout = jiffies + 1 * HZ;
97         while (time_before(jiffies, timeout)) {
98                 if (cpu_isset(cpu, cpu_callin_map))
99                         break;
100                 udelay(100);
101                 barrier();
102         }
103
104         if (cpu_isset(cpu, cpu_callin_map)) {
105                 cpu_set(cpu, cpu_online_map);
106                 /* release the lock and let coreb run */
107                 spin_unlock(&boot_lock);
108                 return 0;
109         } else
110                 panic("CPU%u: processor failed to boot\n", cpu);
111 }
112
113 void __init platform_request_ipi(irq_handler_t handler)
114 {
115         int ret;
116
117         ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
118                           "Supplemental Interrupt0", handler);
119         if (ret)
120                 panic("Cannot request supplemental interrupt 0 for IPI service");
121 }
122
123 void platform_send_ipi(cpumask_t callmap)
124 {
125         unsigned int cpu;
126
127         for_each_cpu_mask(cpu, callmap) {
128                 BUG_ON(cpu >= 2);
129                 SSYNC();
130                 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
131                 SSYNC();
132         }
133 }
134
135 void platform_send_ipi_cpu(unsigned int cpu)
136 {
137         BUG_ON(cpu >= 2);
138         SSYNC();
139         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
140         SSYNC();
141 }
142
143 void platform_clear_ipi(unsigned int cpu)
144 {
145         BUG_ON(cpu >= 2);
146         SSYNC();
147         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
148         SSYNC();
149 }