Blackfin: SMP: add PM/CPU hotplug support
[linux-2.6.git] / arch / blackfin / mach-bf561 / smp.c
1 /*
2  * Copyright 2007-2009 Analog Devices Inc.
3  *               Philippe Gerum <rpm@xenomai.org>
4  *
5  * Licensed under the GPL-2 or later.
6  */
7
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/delay.h>
12 #include <asm/smp.h>
13 #include <asm/dma.h>
14 #include <asm/time.h>
15
16 static DEFINE_SPINLOCK(boot_lock);
17
18 /*
19  * platform_init_cpus() - Tell the world about how many cores we
20  * have. This is called while setting up the architecture support
21  * (setup_arch()), so don't be too demanding here with respect to
22  * available kernel services.
23  */
24
25 void __init platform_init_cpus(void)
26 {
27         cpu_set(0, cpu_possible_map); /* CoreA */
28         cpu_set(1, cpu_possible_map); /* CoreB */
29 }
30
31 void __init platform_prepare_cpus(unsigned int max_cpus)
32 {
33         int len;
34
35         len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
36         BUG_ON(len > L1_CODE_LENGTH);
37
38         dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
39
40         /* Both cores ought to be present on a bf561! */
41         cpu_set(0, cpu_present_map); /* CoreA */
42         cpu_set(1, cpu_present_map); /* CoreB */
43
44         printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
45 }
46
47 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
48 {
49         return -EINVAL;
50 }
51
52 void __cpuinit platform_secondary_init(unsigned int cpu)
53 {
54         /* Clone setup for peripheral interrupt sources from CoreA. */
55         bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
56         bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
57         SSYNC();
58
59         /* Clone setup for IARs from CoreA. */
60         bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
61         bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
62         bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
63         bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
64         bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
65         bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
66         bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
67         bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
68         bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
69         bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
70         SSYNC();
71
72         /* Store CPU-private information to the cpu_data array. */
73         bfin_setup_cpudata(cpu);
74
75         /* We are done with local CPU inits, unblock the boot CPU. */
76         set_cpu_online(cpu, true);
77         spin_lock(&boot_lock);
78         spin_unlock(&boot_lock);
79 }
80
81 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
82 {
83         unsigned long timeout;
84
85         printk(KERN_INFO "Booting Core B.\n");
86
87         spin_lock(&boot_lock);
88
89         if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) {
90                 /* CoreB already running, sending ipi to wakeup it */
91                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92         } else {
93                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
94                 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
95                 SSYNC();
96         }
97
98         timeout = jiffies + 1 * HZ;
99         while (time_before(jiffies, timeout)) {
100                 if (cpu_online(cpu))
101                         break;
102                 udelay(100);
103                 barrier();
104         }
105
106         if (cpu_online(cpu)) {
107                 /* release the lock and let coreb run */
108                 spin_unlock(&boot_lock);
109                 return 0;
110         } else
111                 panic("CPU%u: processor failed to boot\n", cpu);
112 }
113
114 void __init platform_request_ipi(irq_handler_t handler)
115 {
116         int ret;
117
118         ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
119                           "Supplemental Interrupt0", handler);
120         if (ret)
121                 panic("Cannot request supplemental interrupt 0 for IPI service");
122 }
123
124 void platform_send_ipi(cpumask_t callmap)
125 {
126         unsigned int cpu;
127
128         for_each_cpu_mask(cpu, callmap) {
129                 BUG_ON(cpu >= 2);
130                 SSYNC();
131                 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
132                 SSYNC();
133         }
134 }
135
136 void platform_send_ipi_cpu(unsigned int cpu)
137 {
138         BUG_ON(cpu >= 2);
139         SSYNC();
140         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
141         SSYNC();
142 }
143
144 void platform_clear_ipi(unsigned int cpu)
145 {
146         BUG_ON(cpu >= 2);
147         SSYNC();
148         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
149         SSYNC();
150 }
151
152 /*
153  * Setup core B's local core timer.
154  * In SMP, core timer is used for clock event device.
155  */
156 void __cpuinit bfin_local_timer_setup(void)
157 {
158 #if defined(CONFIG_TICKSOURCE_CORETMR)
159         bfin_coretmr_init();
160         bfin_coretmr_clockevent_init();
161         get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR);
162 #else
163         /* Power down the core timer, just to play safe. */
164         bfin_write_TCNTL(0);
165 #endif
166
167 }