Blackfin arch: dma add some API and cleanup bf54x DMA definition
[linux-2.6.git] / arch / blackfin / mach-bf548 / dma.c
1 /*
2  * File:         arch/blackfin/mach-bf561/dma.c
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:  This file contains the simple DMA Implementation for Blackfin
8  *
9  * Modified:
10  *               Copyright 2004-2007 Analog Devices Inc.
11  *
12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License as published by
16  * the Free Software Foundation; either version 2 of the License, or
17  * (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, see the file COPYING, or write
26  * to the Free Software Foundation, Inc.,
27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
28  */
29
30 #include <asm/blackfin.h>
31 #include <asm/dma.h>
32
33  struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
34         (struct dma_register *) DMA0_NEXT_DESC_PTR,
35         (struct dma_register *) DMA1_NEXT_DESC_PTR,
36         (struct dma_register *) DMA2_NEXT_DESC_PTR,
37         (struct dma_register *) DMA3_NEXT_DESC_PTR,
38         (struct dma_register *) DMA4_NEXT_DESC_PTR,
39         (struct dma_register *) DMA5_NEXT_DESC_PTR,
40         (struct dma_register *) DMA6_NEXT_DESC_PTR,
41         (struct dma_register *) DMA7_NEXT_DESC_PTR,
42         (struct dma_register *) DMA8_NEXT_DESC_PTR,
43         (struct dma_register *) DMA9_NEXT_DESC_PTR,
44         (struct dma_register *) DMA10_NEXT_DESC_PTR,
45         (struct dma_register *) DMA11_NEXT_DESC_PTR,
46         (struct dma_register *) DMA12_NEXT_DESC_PTR,
47         (struct dma_register *) DMA13_NEXT_DESC_PTR,
48         (struct dma_register *) DMA14_NEXT_DESC_PTR,
49         (struct dma_register *) DMA15_NEXT_DESC_PTR,
50         (struct dma_register *) DMA16_NEXT_DESC_PTR,
51         (struct dma_register *) DMA17_NEXT_DESC_PTR,
52         (struct dma_register *) DMA18_NEXT_DESC_PTR,
53         (struct dma_register *) DMA19_NEXT_DESC_PTR,
54         (struct dma_register *) DMA20_NEXT_DESC_PTR,
55         (struct dma_register *) DMA21_NEXT_DESC_PTR,
56         (struct dma_register *) DMA22_NEXT_DESC_PTR,
57         (struct dma_register *) DMA23_NEXT_DESC_PTR,
58         (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
59         (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
60         (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
61         (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
62         (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
63         (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
64         (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
65         (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
66 };
67 EXPORT_SYMBOL(base_addr);
68
69 int channel2irq(unsigned int channel)
70 {
71         int ret_irq = -1;
72
73         switch (channel) {
74         case CH_SPORT0_RX:
75                 ret_irq = IRQ_SPORT0_RX;
76                 break;
77         case CH_SPORT0_TX:
78                 ret_irq = IRQ_SPORT0_TX;
79                 break;
80         case CH_SPORT1_RX:
81                 ret_irq = IRQ_SPORT1_RX;
82                 break;
83         case CH_SPORT1_TX:
84                 ret_irq = IRQ_SPORT1_TX;
85         case CH_SPI0:
86                 ret_irq = IRQ_SPI0;
87                 break;
88         case CH_SPI1:
89                 ret_irq = IRQ_SPI1;
90                 break;
91         case CH_UART0_RX:
92                 ret_irq = IRQ_UART_RX;
93                 break;
94         case CH_UART0_TX:
95                 ret_irq = IRQ_UART_TX;
96                 break;
97         case CH_UART1_RX:
98                 ret_irq = IRQ_UART_RX;
99                 break;
100         case CH_UART1_TX:
101                 ret_irq = IRQ_UART_TX;
102                 break;
103         case CH_EPPI0:
104                 ret_irq = IRQ_EPPI0;
105                 break;
106         case CH_EPPI1:
107                 ret_irq = IRQ_EPPI1;
108                 break;
109         case CH_EPPI2:
110                 ret_irq = IRQ_EPPI2;
111                 break;
112         case CH_PIXC_IMAGE:
113                 ret_irq = IRQ_PIXC_IN0;
114                 break;
115         case CH_PIXC_OVERLAY:
116                 ret_irq = IRQ_PIXC_IN1;
117                 break;
118         case CH_PIXC_OUTPUT:
119                 ret_irq = IRQ_PIXC_OUT;
120                 break;
121         case CH_SPORT2_RX:
122                 ret_irq = IRQ_SPORT2_RX;
123                 break;
124         case CH_SPORT2_TX:
125                 ret_irq = IRQ_SPORT2_TX;
126                 break;
127         case CH_SPORT3_RX:
128                 ret_irq = IRQ_SPORT3_RX;
129                 break;
130         case CH_SPORT3_TX:
131                 ret_irq = IRQ_SPORT3_TX;
132                 break;
133         case CH_SDH:
134                 ret_irq = IRQ_SDH;
135                 break;
136         case CH_SPI2:
137                 ret_irq = IRQ_SPI2;
138                 break;
139         case CH_MEM_STREAM0_SRC:
140         case CH_MEM_STREAM0_DEST:
141                 ret_irq = IRQ_MDMAS0;
142                 break;
143         case CH_MEM_STREAM1_SRC:
144         case CH_MEM_STREAM1_DEST:
145                 ret_irq = IRQ_MDMAS1;
146                 break;
147         case CH_MEM_STREAM2_SRC:
148         case CH_MEM_STREAM2_DEST:
149                 ret_irq = IRQ_MDMAS2;
150                 break;
151         case CH_MEM_STREAM3_SRC:
152         case CH_MEM_STREAM3_DEST:
153                 ret_irq = IRQ_MDMAS3;
154                 break;
155         }
156         return ret_irq;
157 }