Blackfin arch: Fix bug using usb keyboard crashes kernel
[linux-2.6.git] / arch / blackfin / kernel / setup.c
1 /*
2  * File:         arch/blackfin/kernel/setup.c
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Modified:
10  *               Copyright 2004-2006 Analog Devices Inc.
11  *
12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License as published by
16  * the Free Software Foundation; either version 2 of the License, or
17  * (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, see the file COPYING, or write
26  * to the Free Software Foundation, Inc.,
27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
28  */
29
30 #include <linux/delay.h>
31 #include <linux/console.h>
32 #include <linux/bootmem.h>
33 #include <linux/seq_file.h>
34 #include <linux/cpu.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37
38 #include <linux/ext2_fs.h>
39 #include <linux/cramfs_fs.h>
40 #include <linux/romfs_fs.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/blackfin.h>
44 #include <asm/cplbinit.h>
45
46 unsigned long memory_start, memory_end, physical_mem_end;
47 unsigned long reserved_mem_dcache_on;
48 unsigned long reserved_mem_icache_on;
49 EXPORT_SYMBOL(memory_start);
50 EXPORT_SYMBOL(memory_end);
51 EXPORT_SYMBOL(physical_mem_end);
52 EXPORT_SYMBOL(_ramend);
53
54 #ifdef CONFIG_MTD_UCLINUX
55 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
56 unsigned long _ebss;
57 EXPORT_SYMBOL(memory_mtd_end);
58 EXPORT_SYMBOL(memory_mtd_start);
59 EXPORT_SYMBOL(mtd_size);
60 #endif
61
62 char command_line[COMMAND_LINE_SIZE];
63
64 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
65 static void generate_cpl_tables(void);
66 #endif
67
68 void __init bf53x_cache_init(void)
69 {
70 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
71         generate_cpl_tables();
72 #endif
73
74 #ifdef CONFIG_BLKFIN_CACHE
75         bfin_icache_init();
76         printk(KERN_INFO "Instruction Cache Enabled\n");
77 #endif
78
79 #ifdef CONFIG_BLKFIN_DCACHE
80         bfin_dcache_init();
81         printk(KERN_INFO "Data Cache Enabled"
82 # if defined CONFIG_BLKFIN_WB
83                 " (write-back)"
84 # elif defined CONFIG_BLKFIN_WT
85                 " (write-through)"
86 # endif
87                 "\n");
88 #endif
89 }
90
91 void bf53x_relocate_l1_mem(void)
92 {
93         unsigned long l1_code_length;
94         unsigned long l1_data_a_length;
95         unsigned long l1_data_b_length;
96
97         l1_code_length = _etext_l1 - _stext_l1;
98         if (l1_code_length > L1_CODE_LENGTH)
99                 l1_code_length = L1_CODE_LENGTH;
100         /* cannot complain as printk is not available as yet.
101          * But we can continue booting and complain later!
102          */
103
104         /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
105         dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
106
107         l1_data_a_length = _ebss_l1 - _sdata_l1;
108         if (l1_data_a_length > L1_DATA_A_LENGTH)
109                 l1_data_a_length = L1_DATA_A_LENGTH;
110
111         /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
112         dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
113
114         l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
115         if (l1_data_b_length > L1_DATA_B_LENGTH)
116                 l1_data_b_length = L1_DATA_B_LENGTH;
117
118         /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
119         dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
120                         l1_data_a_length, l1_data_b_length);
121
122 }
123
124 /*
125  * Initial parsing of the command line.  Currently, we support:
126  *  - Controlling the linux memory size: mem=xxx[KMG]
127  *  - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
128  *       $ -> reserved memory is dcacheable
129  *       # -> reserved memory is icacheable
130  */
131 static __init void parse_cmdline_early(char *cmdline_p)
132 {
133         char c = ' ', *to = cmdline_p;
134         unsigned int memsize;
135         for (;;) {
136                 if (c == ' ') {
137
138                         if (!memcmp(to, "mem=", 4)) {
139                                 to += 4;
140                                 memsize = memparse(to, &to);
141                                 if (memsize)
142                                         _ramend = memsize;
143
144                         } else if (!memcmp(to, "max_mem=", 8)) {
145                                 to += 8;
146                                 memsize = memparse(to, &to);
147                                 if (memsize) {
148                                         physical_mem_end = memsize;
149                                         if (*to != ' ') {
150                                                 if (*to == '$'
151                                                     || *(to + 1) == '$')
152                                                         reserved_mem_dcache_on =
153                                                             1;
154                                                 if (*to == '#'
155                                                     || *(to + 1) == '#')
156                                                         reserved_mem_icache_on =
157                                                             1;
158                                         }
159                                 }
160                         }
161
162                 }
163                 c = *(to++);
164                 if (!c)
165                         break;
166         }
167 }
168
169 void __init setup_arch(char **cmdline_p)
170 {
171         int bootmap_size;
172         unsigned long l1_length, sclk, cclk;
173 #ifdef CONFIG_MTD_UCLINUX
174         unsigned long mtd_phys = 0;
175 #endif
176
177 #ifdef CONFIG_DUMMY_CONSOLE
178         conswitchp = &dummy_con;
179 #endif
180         cclk = get_cclk();
181         sclk = get_sclk();
182
183 #if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
184         if (cclk == sclk)
185                 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
186 #endif
187
188 #if defined(ANOMALY_05000266)
189         bfin_read_IMDMA_D0_IRQ_STATUS();
190         bfin_read_IMDMA_D1_IRQ_STATUS();
191 #endif
192
193 #ifdef DEBUG_SERIAL_EARLY_INIT
194         bfin_console_init();    /* early console registration */
195         /* this give a chance to get printk() working before crash. */
196 #endif
197
198 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
199         /* we need to initialize the Flashrom device here since we might
200          * do things with flash early on in the boot
201          */
202         flash_probe();
203 #endif
204
205 #if defined(CONFIG_CMDLINE_BOOL)
206         memset(command_line, 0, sizeof(command_line));
207         strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
208         command_line[sizeof(command_line) - 1] = 0;
209 #endif
210
211         /* Keep a copy of command line */
212         *cmdline_p = &command_line[0];
213         memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
214         boot_command_line[COMMAND_LINE_SIZE - 1] = 0;
215
216         /* setup memory defaults from the user config */
217         physical_mem_end = 0;
218         _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
219
220         parse_cmdline_early(&command_line[0]);
221
222         if (physical_mem_end == 0)
223                 physical_mem_end = _ramend;
224
225         /* by now the stack is part of the init task */
226         memory_end = _ramend - DMA_UNCACHED_REGION;
227
228         _ramstart = (unsigned long)__bss_stop;
229         memory_start = PAGE_ALIGN(_ramstart);
230
231 #if defined(CONFIG_MTD_UCLINUX)
232         /* generic memory mapped MTD driver */
233         memory_mtd_end = memory_end;
234
235         mtd_phys = _ramstart;
236         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
237
238 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
239         if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
240                 mtd_size =
241                     PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
242 # endif
243
244 # if defined(CONFIG_CRAMFS)
245         if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
246                 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
247 # endif
248
249 # if defined(CONFIG_ROMFS_FS)
250         if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
251             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
252                 mtd_size =
253                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
254 #  if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
255         /* Due to a Hardware Anomaly we need to limit the size of usable
256          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
257          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
258          */
259 #   if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
260         if (memory_end >= 56 * 1024 * 1024)
261                 memory_end = 56 * 1024 * 1024;
262 #   else
263         if (memory_end >= 60 * 1024 * 1024)
264                 memory_end = 60 * 1024 * 1024;
265 #   endif                               /* CONFIG_DEBUG_HUNT_FOR_ZERO */
266 #  endif                                /* ANOMALY_05000263 */
267 # endif                         /* CONFIG_ROMFS_FS */
268
269         memory_end -= mtd_size;
270
271         if (mtd_size == 0) {
272                 console_init();
273                 panic("Don't boot kernel without rootfs attached.\n");
274         }
275
276         /* Relocate MTD image to the top of memory after the uncached memory area */
277         dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
278
279         memory_mtd_start = memory_end;
280         _ebss = memory_mtd_start;       /* define _ebss for compatible */
281 #endif                          /* CONFIG_MTD_UCLINUX */
282
283 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
284         /* Due to a Hardware Anomaly we need to limit the size of usable
285          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
286          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
287          */
288 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
289         if (memory_end >= 56 * 1024 * 1024)
290                 memory_end = 56 * 1024 * 1024;
291 #else
292         if (memory_end >= 60 * 1024 * 1024)
293                 memory_end = 60 * 1024 * 1024;
294 #endif                          /* CONFIG_DEBUG_HUNT_FOR_ZERO */
295         printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
296 #endif                          /* ANOMALY_05000263 */
297
298 #if !defined(CONFIG_MTD_UCLINUX)
299         memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
300 #endif
301         init_mm.start_code = (unsigned long)_stext;
302         init_mm.end_code = (unsigned long)_etext;
303         init_mm.end_data = (unsigned long)_edata;
304         init_mm.brk = (unsigned long)0;
305
306         init_leds();
307
308         printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
309         printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
310         if (bfin_revid() != bfin_compiled_revid())
311                 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
312                        bfin_compiled_revid(), bfin_revid());
313         if (bfin_revid() < SUPPORTED_REVID)
314                 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
315                        CPU, bfin_revid());
316         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
317
318         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
319                cclk / 1000000,  sclk / 1000000);
320
321 #if defined(ANOMALY_05000273)
322         if ((cclk >> 1) <= sclk)
323                 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
324 #endif
325
326         printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
327         printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
328
329         printk(KERN_INFO "Memory map:\n"
330                KERN_INFO "  text      = 0x%p-0x%p\n"
331                KERN_INFO "  init      = 0x%p-0x%p\n"
332                KERN_INFO "  data      = 0x%p-0x%p\n"
333                KERN_INFO "  stack     = 0x%p-0x%p\n"
334                KERN_INFO "  bss       = 0x%p-0x%p\n"
335                KERN_INFO "  available = 0x%p-0x%p\n"
336 #ifdef CONFIG_MTD_UCLINUX
337                KERN_INFO "  rootfs    = 0x%p-0x%p\n"
338 #endif
339 #if DMA_UNCACHED_REGION > 0
340                KERN_INFO "  DMA Zone  = 0x%p-0x%p\n"
341 #endif
342                , _stext, _etext,
343                __init_begin, __init_end,
344                _sdata, _edata,
345                (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
346                __bss_start, __bss_stop,
347                (void*)_ramstart, (void*)memory_end
348 #ifdef CONFIG_MTD_UCLINUX
349                , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
350 #endif
351 #if DMA_UNCACHED_REGION > 0
352                , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
353 #endif
354                );
355
356         /*
357          * give all the memory to the bootmap allocator,  tell it to put the
358          * boot mem_map at the start of memory
359          */
360         bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT,      /* map goes here */
361                                          PAGE_OFFSET >> PAGE_SHIFT,
362                                          memory_end >> PAGE_SHIFT);
363         /*
364          * free the usable memory,  we have to make sure we do not free
365          * the bootmem bitmap so we then reserve it after freeing it :-)
366          */
367         free_bootmem(memory_start, memory_end - memory_start);
368
369         reserve_bootmem(memory_start, bootmap_size);
370         /*
371          * get kmalloc into gear
372          */
373         paging_init();
374
375         /* check the size of the l1 area */
376         l1_length = _etext_l1 - _stext_l1;
377         if (l1_length > L1_CODE_LENGTH)
378                 panic("L1 memory overflow\n");
379
380         l1_length = _ebss_l1 - _sdata_l1;
381         if (l1_length > L1_DATA_A_LENGTH)
382                 panic("L1 memory overflow\n");
383
384         bf53x_cache_init();
385
386 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
387 # if defined(CONFIG_BFIN_SHARED_FLASH_ENET) && defined(CONFIG_BFIN533_STAMP)
388         /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
389         bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1 << CONFIG_ENET_FLASH_PIN));
390         bfin_write_FIO_FLAG_S(1 << CONFIG_ENET_FLASH_PIN);
391         SSYNC();
392 # endif
393 # if defined (CONFIG_BFIN561_EZKIT)
394         bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
395         SSYNC();
396 # endif /* defined (CONFIG_BFIN561_EZKIT) */
397 #endif
398
399         printk(KERN_INFO "Hardware Trace Enabled\n");
400         bfin_write_TBUFCTL(0x03);
401 }
402
403 #if defined(CONFIG_BF561)
404 static struct cpu cpu[2];
405 #else
406 static struct cpu cpu[1];
407 #endif
408 static int __init topology_init(void)
409 {
410 #if defined (CONFIG_BF561)
411         register_cpu(&cpu[0], 0);
412         register_cpu(&cpu[1], 1);
413         return 0;
414 #else
415         return register_cpu(cpu, 0);
416 #endif
417 }
418
419 subsys_initcall(topology_init);
420
421 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
422 u16 lock_kernel_check(u32 start, u32 end)
423 {
424         if ((start <= (u32) _stext && end >= (u32) _end)
425             || (start >= (u32) _stext && end <= (u32) _end))
426                 return IN_KERNEL;
427         return 0;
428 }
429
430 static unsigned short __init
431 fill_cplbtab(struct cplb_tab *table,
432              unsigned long start, unsigned long end,
433              unsigned long block_size, unsigned long cplb_data)
434 {
435         int i;
436
437         switch (block_size) {
438         case SIZE_4M:
439                 i = 3;
440                 break;
441         case SIZE_1M:
442                 i = 2;
443                 break;
444         case SIZE_4K:
445                 i = 1;
446                 break;
447         case SIZE_1K:
448         default:
449                 i = 0;
450                 break;
451         }
452
453         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
454
455         while ((start < end) && (table->pos < table->size)) {
456
457                 table->tab[table->pos++] = start;
458
459                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
460                         table->tab[table->pos++] =
461                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
462                 else
463                         table->tab[table->pos++] = cplb_data;
464
465                 start += block_size;
466         }
467         return 0;
468 }
469
470 static unsigned short __init
471 close_cplbtab(struct cplb_tab *table)
472 {
473
474         while (table->pos < table->size) {
475
476                 table->tab[table->pos++] = 0;
477                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
478         }
479         return 0;
480 }
481
482 static void __init generate_cpl_tables(void)
483 {
484
485         u16 i, j, process;
486         u32 a_start, a_end, as, ae, as_1m;
487
488         struct cplb_tab *t_i = NULL;
489         struct cplb_tab *t_d = NULL;
490         struct s_cplb cplb;
491
492         cplb.init_i.size = MAX_CPLBS;
493         cplb.init_d.size = MAX_CPLBS;
494         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
495         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
496
497         cplb.init_i.pos = 0;
498         cplb.init_d.pos = 0;
499         cplb.switch_i.pos = 0;
500         cplb.switch_d.pos = 0;
501
502         cplb.init_i.tab = icplb_table;
503         cplb.init_d.tab = dcplb_table;
504         cplb.switch_i.tab = ipdt_table;
505         cplb.switch_d.tab = dpdt_table;
506
507         cplb_data[SDRAM_KERN].end = memory_end;
508
509 #ifdef CONFIG_MTD_UCLINUX
510         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
511         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
512         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
513 # if defined(CONFIG_ROMFS_FS)
514         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
515
516         /*
517          * The ROMFS_FS size is often not multiple of 1MB.
518          * This can cause multiple CPLB sets covering the same memory area.
519          * This will then cause multiple CPLB hit exceptions.
520          * Workaround: We ensure a contiguous memory area by extending the kernel
521          * memory section over the mtd section.
522          * For ROMFS_FS memory must be covered with ICPLBs anyways.
523          * So there is no difference between kernel and mtd memory setup.
524          */
525
526         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
527         cplb_data[SDRAM_RAM_MTD].valid = 0;
528
529 # endif
530 #else
531         cplb_data[SDRAM_RAM_MTD].valid = 0;
532 #endif
533
534         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
535         cplb_data[SDRAM_DMAZ].end = _ramend;
536
537         cplb_data[RES_MEM].start = _ramend;
538         cplb_data[RES_MEM].end = physical_mem_end;
539
540         if (reserved_mem_dcache_on)
541                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
542         else
543                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
544
545         if (reserved_mem_icache_on)
546                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
547         else
548                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
549
550         for (i = ZERO_P; i <= L2_MEM; i++) {
551
552                 if (cplb_data[i].valid) {
553
554                         as_1m = cplb_data[i].start % SIZE_1M;
555
556                         /* We need to make sure all sections are properly 1M aligned
557                          * However between Kernel Memory and the Kernel mtd section, depending on the
558                          * rootfs size, there can be overlapping memory areas.
559                          */
560
561                         if (as_1m &&  i!=L1I_MEM && i!=L1D_MEM) {
562 #ifdef CONFIG_MTD_UCLINUX
563                                 if (i == SDRAM_RAM_MTD) {
564                                         if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
565                                                 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
566                                         else
567                                                 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
568                                 } else
569 #endif
570                                         printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
571                                                cplb_data[i].name, cplb_data[i].start);
572                         }
573
574                         as = cplb_data[i].start % SIZE_4M;
575                         ae = cplb_data[i].end % SIZE_4M;
576
577                         if (as)
578                                 a_start = cplb_data[i].start + (SIZE_4M - (as));
579                         else
580                                 a_start = cplb_data[i].start;
581
582                         a_end = cplb_data[i].end - ae;
583
584                         for (j = INITIAL_T; j <= SWITCH_T; j++) {
585
586                                 switch (j) {
587                                 case INITIAL_T:
588                                         if (cplb_data[i].attr & INITIAL_T) {
589                                                 t_i = &cplb.init_i;
590                                                 t_d = &cplb.init_d;
591                                                 process = 1;
592                                         } else
593                                                 process = 0;
594                                         break;
595                                 case SWITCH_T:
596                                         if (cplb_data[i].attr & SWITCH_T) {
597                                                 t_i = &cplb.switch_i;
598                                                 t_d = &cplb.switch_d;
599                                                 process = 1;
600                                         } else
601                                                 process = 0;
602                                         break;
603                                 default:
604                                                 process = 0;
605                                         break;
606                                 }
607
608         if (process) {
609                                 if (cplb_data[i].attr & I_CPLB) {
610
611                                         if (cplb_data[i].psize) {
612                                                 fill_cplbtab(t_i,
613                                                              cplb_data[i].start,
614                                                              cplb_data[i].end,
615                                                              cplb_data[i].psize,
616                                                              cplb_data[i].i_conf);
617                                         } else {
618                                                 /*icplb_table */
619 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
620                                                 if (i == SDRAM_KERN) {
621                                                         fill_cplbtab(t_i,
622                                                                      cplb_data[i].start,
623                                                                      cplb_data[i].end,
624                                                                      SIZE_4M,
625                                                                      cplb_data[i].i_conf);
626                                                 } else
627 #endif
628                                                 {
629                                                         fill_cplbtab(t_i,
630                                                                      cplb_data[i].start,
631                                                                      a_start,
632                                                                      SIZE_1M,
633                                                                      cplb_data[i].i_conf);
634                                                         fill_cplbtab(t_i,
635                                                                      a_start,
636                                                                      a_end,
637                                                                      SIZE_4M,
638                                                                      cplb_data[i].i_conf);
639                                                         fill_cplbtab(t_i, a_end,
640                                                                      cplb_data[i].end,
641                                                                      SIZE_1M,
642                                                                      cplb_data[i].i_conf);
643                                                 }
644                                         }
645
646                                 }
647                                 if (cplb_data[i].attr & D_CPLB) {
648
649                                         if (cplb_data[i].psize) {
650                                                 fill_cplbtab(t_d,
651                                                              cplb_data[i].start,
652                                                              cplb_data[i].end,
653                                                              cplb_data[i].psize,
654                                                              cplb_data[i].d_conf);
655                                         } else {
656 /*dcplb_table*/
657                                                 fill_cplbtab(t_d,
658                                                              cplb_data[i].start,
659                                                              a_start, SIZE_1M,
660                                                              cplb_data[i].d_conf);
661                                                 fill_cplbtab(t_d, a_start,
662                                                              a_end, SIZE_4M,
663                                                              cplb_data[i].d_conf);
664                                                 fill_cplbtab(t_d, a_end,
665                                                              cplb_data[i].end,
666                                                              SIZE_1M,
667                                                              cplb_data[i].d_conf);
668
669                                         }
670
671                                 }
672                         }
673                         }
674
675                 }
676         }
677
678 /* close tables */
679
680         close_cplbtab(&cplb.init_i);
681         close_cplbtab(&cplb.init_d);
682
683         cplb.init_i.tab[cplb.init_i.pos] = -1;
684         cplb.init_d.tab[cplb.init_d.pos] = -1;
685         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
686         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
687
688 }
689
690 #endif
691
692 static inline u_long get_vco(void)
693 {
694         u_long msel;
695         u_long vco;
696
697         msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
698         if (0 == msel)
699                 msel = 64;
700
701         vco = CONFIG_CLKIN_HZ;
702         vco >>= (1 & bfin_read_PLL_CTL());      /* DF bit */
703         vco = msel * vco;
704         return vco;
705 }
706
707 /*Get the Core clock*/
708 u_long get_cclk(void)
709 {
710         u_long csel, ssel;
711         if (bfin_read_PLL_STAT() & 0x1)
712                 return CONFIG_CLKIN_HZ;
713
714         ssel = bfin_read_PLL_DIV();
715         csel = ((ssel >> 4) & 0x03);
716         ssel &= 0xf;
717         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
718                 return get_vco() / ssel;
719         return get_vco() >> csel;
720 }
721
722 EXPORT_SYMBOL(get_cclk);
723
724 /* Get the System clock */
725 u_long get_sclk(void)
726 {
727         u_long ssel;
728
729         if (bfin_read_PLL_STAT() & 0x1)
730                 return CONFIG_CLKIN_HZ;
731
732         ssel = (bfin_read_PLL_DIV() & 0xf);
733         if (0 == ssel) {
734                 printk(KERN_WARNING "Invalid System Clock\n");
735                 ssel = 1;
736         }
737
738         return get_vco() / ssel;
739 }
740
741 EXPORT_SYMBOL(get_sclk);
742
743 /*
744  *      Get CPU information for use by the procfs.
745  */
746 static int show_cpuinfo(struct seq_file *m, void *v)
747 {
748         char *cpu, *mmu, *fpu, *name;
749         uint32_t revid;
750
751         u_long cclk = 0, sclk = 0;
752         u_int dcache_size = 0, dsup_banks = 0;
753
754         cpu = CPU;
755         mmu = "none";
756         fpu = "none";
757         revid = bfin_revid();
758         name = bfin_board_name;
759
760         cclk = get_cclk();
761         sclk = get_sclk();
762
763         seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
764                    "MMU:\t\t%s\n"
765                    "FPU:\t\t%s\n"
766                    "Core Clock:\t%9lu Hz\n"
767                    "System Clock:\t%9lu Hz\n"
768                    "BogoMips:\t%lu.%02lu\n"
769                    "Calibration:\t%lu loops\n",
770                    cpu, revid, mmu, fpu,
771                    cclk,
772                    sclk,
773                    (loops_per_jiffy * HZ) / 500000,
774                    ((loops_per_jiffy * HZ) / 5000) % 100,
775                    (loops_per_jiffy * HZ));
776         seq_printf(m, "Board Name:\t%s\n", name);
777         seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
778         seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
779         if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
780                 seq_printf(m, "I-CACHE:\tON\n");
781         else
782                 seq_printf(m, "I-CACHE:\tOFF\n");
783         if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
784                 seq_printf(m, "D-CACHE:\tON"
785 #if defined CONFIG_BLKFIN_WB
786                            " (write-back)"
787 #elif defined CONFIG_BLKFIN_WT
788                            " (write-through)"
789 #endif
790                            "\n");
791         else
792                 seq_printf(m, "D-CACHE:\tOFF\n");
793
794
795         switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
796                 case ACACHE_BSRAM:
797                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
798                         dcache_size = 16;
799                         dsup_banks = 1;
800                         break;
801                 case ACACHE_BCACHE:
802                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
803                         dcache_size = 32;
804                         dsup_banks = 2;
805                         break;
806                 case ASRAM_BSRAM:
807                         seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
808                         dcache_size = 0;
809                         dsup_banks = 0;
810                         break;
811                 default:
812                 break;
813         }
814
815
816         seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
817         seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
818         seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
819                    BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
820         seq_printf(m,
821                    "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
822                    dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
823                    BLKFIN_DLINES);
824 #ifdef CONFIG_BLKFIN_CACHE_LOCK
825         switch (read_iloc()) {
826         case WAY0_L:
827                 seq_printf(m, "Way0 Locked-Down\n");
828                 break;
829         case WAY1_L:
830                 seq_printf(m, "Way1 Locked-Down\n");
831                 break;
832         case WAY01_L:
833                 seq_printf(m, "Way0,Way1 Locked-Down\n");
834                 break;
835         case WAY2_L:
836                 seq_printf(m, "Way2 Locked-Down\n");
837                 break;
838         case WAY02_L:
839                 seq_printf(m, "Way0,Way2 Locked-Down\n");
840                 break;
841         case WAY12_L:
842                 seq_printf(m, "Way1,Way2 Locked-Down\n");
843                 break;
844         case WAY012_L:
845                 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
846                 break;
847         case WAY3_L:
848                 seq_printf(m, "Way3 Locked-Down\n");
849                 break;
850         case WAY03_L:
851                 seq_printf(m, "Way0,Way3 Locked-Down\n");
852                 break;
853         case WAY13_L:
854                 seq_printf(m, "Way1,Way3 Locked-Down\n");
855                 break;
856         case WAY013_L:
857                 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
858                 break;
859         case WAY32_L:
860                 seq_printf(m, "Way3,Way2 Locked-Down\n");
861                 break;
862         case WAY320_L:
863                 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
864                 break;
865         case WAY321_L:
866                 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
867                 break;
868         case WAYALL_L:
869                 seq_printf(m, "All Ways are locked\n");
870                 break;
871         default:
872                 seq_printf(m, "No Ways are locked\n");
873         }
874 #endif
875         return 0;
876 }
877
878 static void *c_start(struct seq_file *m, loff_t *pos)
879 {
880         return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
881 }
882
883 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
884 {
885         ++*pos;
886         return c_start(m, pos);
887 }
888
889 static void c_stop(struct seq_file *m, void *v)
890 {
891 }
892
893 struct seq_operations cpuinfo_op = {
894         .start = c_start,
895         .next = c_next,
896         .stop = c_stop,
897         .show = show_cpuinfo,
898 };
899
900 void cmdline_init(unsigned long r0)
901 {
902         if (r0)
903                 strncpy(command_line, (char *)r0, COMMAND_LINE_SIZE);
904 }