Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[linux-2.6.git] / arch / avr32 / mach-at32ap / at32ap700x.c
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
18 #include <linux/atmel-mci.h>
19
20 #include <asm/io.h>
21 #include <asm/irq.h>
22
23 #include <mach/at32ap700x.h>
24 #include <mach/board.h>
25 #include <mach/hmatrix.h>
26 #include <mach/portmux.h>
27 #include <mach/sram.h>
28
29 #include <video/atmel_lcdc.h>
30
31 #include "clock.h"
32 #include "pio.h"
33 #include "pm.h"
34
35
36 #define PBMEM(base)                                     \
37         {                                               \
38                 .start          = base,                 \
39                 .end            = base + 0x3ff,         \
40                 .flags          = IORESOURCE_MEM,       \
41         }
42 #define IRQ(num)                                        \
43         {                                               \
44                 .start          = num,                  \
45                 .end            = num,                  \
46                 .flags          = IORESOURCE_IRQ,       \
47         }
48 #define NAMED_IRQ(num, _name)                           \
49         {                                               \
50                 .start          = num,                  \
51                 .end            = num,                  \
52                 .name           = _name,                \
53                 .flags          = IORESOURCE_IRQ,       \
54         }
55
56 /* REVISIT these assume *every* device supports DMA, but several
57  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
58  */
59 #define DEFINE_DEV(_name, _id)                                  \
60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
61 static struct platform_device _name##_id##_device = {           \
62         .name           = #_name,                               \
63         .id             = _id,                                  \
64         .dev            = {                                     \
65                 .dma_mask = &_name##_id##_dma_mask,             \
66                 .coherent_dma_mask = DMA_32BIT_MASK,            \
67         },                                                      \
68         .resource       = _name##_id##_resource,                \
69         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
70 }
71 #define DEFINE_DEV_DATA(_name, _id)                             \
72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
73 static struct platform_device _name##_id##_device = {           \
74         .name           = #_name,                               \
75         .id             = _id,                                  \
76         .dev            = {                                     \
77                 .dma_mask = &_name##_id##_dma_mask,             \
78                 .platform_data  = &_name##_id##_data,           \
79                 .coherent_dma_mask = DMA_32BIT_MASK,            \
80         },                                                      \
81         .resource       = _name##_id##_resource,                \
82         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
83 }
84
85 #define select_peripheral(port, pin_mask, periph, flags)        \
86         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
87                            GPIO_##periph, flags)
88
89 #define DEV_CLK(_name, devname, bus, _index)                    \
90 static struct clk devname##_##_name = {                         \
91         .name           = #_name,                               \
92         .dev            = &devname##_device.dev,                \
93         .parent         = &bus##_clk,                           \
94         .mode           = bus##_clk_mode,                       \
95         .get_rate       = bus##_clk_get_rate,                   \
96         .index          = _index,                               \
97 }
98
99 static DEFINE_SPINLOCK(pm_lock);
100
101 static struct clk osc0;
102 static struct clk osc1;
103
104 static unsigned long osc_get_rate(struct clk *clk)
105 {
106         return at32_board_osc_rates[clk->index];
107 }
108
109 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
110 {
111         unsigned long div, mul, rate;
112
113         div = PM_BFEXT(PLLDIV, control) + 1;
114         mul = PM_BFEXT(PLLMUL, control) + 1;
115
116         rate = clk->parent->get_rate(clk->parent);
117         rate = (rate + div / 2) / div;
118         rate *= mul;
119
120         return rate;
121 }
122
123 static long pll_set_rate(struct clk *clk, unsigned long rate,
124                          u32 *pll_ctrl)
125 {
126         unsigned long mul;
127         unsigned long mul_best_fit = 0;
128         unsigned long div;
129         unsigned long div_min;
130         unsigned long div_max;
131         unsigned long div_best_fit = 0;
132         unsigned long base;
133         unsigned long pll_in;
134         unsigned long actual = 0;
135         unsigned long rate_error;
136         unsigned long rate_error_prev = ~0UL;
137         u32 ctrl;
138
139         /* Rate must be between 80 MHz and 200 Mhz. */
140         if (rate < 80000000UL || rate > 200000000UL)
141                 return -EINVAL;
142
143         ctrl = PM_BF(PLLOPT, 4);
144         base = clk->parent->get_rate(clk->parent);
145
146         /* PLL input frequency must be between 6 MHz and 32 MHz. */
147         div_min = DIV_ROUND_UP(base, 32000000UL);
148         div_max = base / 6000000UL;
149
150         if (div_max < div_min)
151                 return -EINVAL;
152
153         for (div = div_min; div <= div_max; div++) {
154                 pll_in = (base + div / 2) / div;
155                 mul = (rate + pll_in / 2) / pll_in;
156
157                 if (mul == 0)
158                         continue;
159
160                 actual = pll_in * mul;
161                 rate_error = abs(actual - rate);
162
163                 if (rate_error < rate_error_prev) {
164                         mul_best_fit = mul;
165                         div_best_fit = div;
166                         rate_error_prev = rate_error;
167                 }
168
169                 if (rate_error == 0)
170                         break;
171         }
172
173         if (div_best_fit == 0)
174                 return -EINVAL;
175
176         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
177         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
178         ctrl |= PM_BF(PLLCOUNT, 16);
179
180         if (clk->parent == &osc1)
181                 ctrl |= PM_BIT(PLLOSC);
182
183         *pll_ctrl = ctrl;
184
185         return actual;
186 }
187
188 static unsigned long pll0_get_rate(struct clk *clk)
189 {
190         u32 control;
191
192         control = pm_readl(PLL0);
193
194         return pll_get_rate(clk, control);
195 }
196
197 static void pll1_mode(struct clk *clk, int enabled)
198 {
199         unsigned long timeout;
200         u32 status;
201         u32 ctrl;
202
203         ctrl = pm_readl(PLL1);
204
205         if (enabled) {
206                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
207                         pr_debug("clk %s: failed to enable, rate not set\n",
208                                         clk->name);
209                         return;
210                 }
211
212                 ctrl |= PM_BIT(PLLEN);
213                 pm_writel(PLL1, ctrl);
214
215                 /* Wait for PLL lock. */
216                 for (timeout = 10000; timeout; timeout--) {
217                         status = pm_readl(ISR);
218                         if (status & PM_BIT(LOCK1))
219                                 break;
220                         udelay(10);
221                 }
222
223                 if (!(status & PM_BIT(LOCK1)))
224                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
225                                         clk->name);
226         } else {
227                 ctrl &= ~PM_BIT(PLLEN);
228                 pm_writel(PLL1, ctrl);
229         }
230 }
231
232 static unsigned long pll1_get_rate(struct clk *clk)
233 {
234         u32 control;
235
236         control = pm_readl(PLL1);
237
238         return pll_get_rate(clk, control);
239 }
240
241 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
242 {
243         u32 ctrl = 0;
244         unsigned long actual_rate;
245
246         actual_rate = pll_set_rate(clk, rate, &ctrl);
247
248         if (apply) {
249                 if (actual_rate != rate)
250                         return -EINVAL;
251                 if (clk->users > 0)
252                         return -EBUSY;
253                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
254                                 clk->name, rate, actual_rate);
255                 pm_writel(PLL1, ctrl);
256         }
257
258         return actual_rate;
259 }
260
261 static int pll1_set_parent(struct clk *clk, struct clk *parent)
262 {
263         u32 ctrl;
264
265         if (clk->users > 0)
266                 return -EBUSY;
267
268         ctrl = pm_readl(PLL1);
269         WARN_ON(ctrl & PM_BIT(PLLEN));
270
271         if (parent == &osc0)
272                 ctrl &= ~PM_BIT(PLLOSC);
273         else if (parent == &osc1)
274                 ctrl |= PM_BIT(PLLOSC);
275         else
276                 return -EINVAL;
277
278         pm_writel(PLL1, ctrl);
279         clk->parent = parent;
280
281         return 0;
282 }
283
284 /*
285  * The AT32AP7000 has five primary clock sources: One 32kHz
286  * oscillator, two crystal oscillators and two PLLs.
287  */
288 static struct clk osc32k = {
289         .name           = "osc32k",
290         .get_rate       = osc_get_rate,
291         .users          = 1,
292         .index          = 0,
293 };
294 static struct clk osc0 = {
295         .name           = "osc0",
296         .get_rate       = osc_get_rate,
297         .users          = 1,
298         .index          = 1,
299 };
300 static struct clk osc1 = {
301         .name           = "osc1",
302         .get_rate       = osc_get_rate,
303         .index          = 2,
304 };
305 static struct clk pll0 = {
306         .name           = "pll0",
307         .get_rate       = pll0_get_rate,
308         .parent         = &osc0,
309 };
310 static struct clk pll1 = {
311         .name           = "pll1",
312         .mode           = pll1_mode,
313         .get_rate       = pll1_get_rate,
314         .set_rate       = pll1_set_rate,
315         .set_parent     = pll1_set_parent,
316         .parent         = &osc0,
317 };
318
319 /*
320  * The main clock can be either osc0 or pll0.  The boot loader may
321  * have chosen one for us, so we don't really know which one until we
322  * have a look at the SM.
323  */
324 static struct clk *main_clock;
325
326 /*
327  * Synchronous clocks are generated from the main clock. The clocks
328  * must satisfy the constraint
329  *   fCPU >= fHSB >= fPB
330  * i.e. each clock must not be faster than its parent.
331  */
332 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
333 {
334         return main_clock->get_rate(main_clock) >> shift;
335 };
336
337 static void cpu_clk_mode(struct clk *clk, int enabled)
338 {
339         unsigned long flags;
340         u32 mask;
341
342         spin_lock_irqsave(&pm_lock, flags);
343         mask = pm_readl(CPU_MASK);
344         if (enabled)
345                 mask |= 1 << clk->index;
346         else
347                 mask &= ~(1 << clk->index);
348         pm_writel(CPU_MASK, mask);
349         spin_unlock_irqrestore(&pm_lock, flags);
350 }
351
352 static unsigned long cpu_clk_get_rate(struct clk *clk)
353 {
354         unsigned long cksel, shift = 0;
355
356         cksel = pm_readl(CKSEL);
357         if (cksel & PM_BIT(CPUDIV))
358                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
359
360         return bus_clk_get_rate(clk, shift);
361 }
362
363 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
364 {
365         u32 control;
366         unsigned long parent_rate, child_div, actual_rate, div;
367
368         parent_rate = clk->parent->get_rate(clk->parent);
369         control = pm_readl(CKSEL);
370
371         if (control & PM_BIT(HSBDIV))
372                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
373         else
374                 child_div = 1;
375
376         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
377                 actual_rate = parent_rate;
378                 control &= ~PM_BIT(CPUDIV);
379         } else {
380                 unsigned int cpusel;
381                 div = (parent_rate + rate / 2) / rate;
382                 if (div > child_div)
383                         div = child_div;
384                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
385                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
386                 actual_rate = parent_rate / (1 << (cpusel + 1));
387         }
388
389         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
390                         clk->name, rate, actual_rate);
391
392         if (apply)
393                 pm_writel(CKSEL, control);
394
395         return actual_rate;
396 }
397
398 static void hsb_clk_mode(struct clk *clk, int enabled)
399 {
400         unsigned long flags;
401         u32 mask;
402
403         spin_lock_irqsave(&pm_lock, flags);
404         mask = pm_readl(HSB_MASK);
405         if (enabled)
406                 mask |= 1 << clk->index;
407         else
408                 mask &= ~(1 << clk->index);
409         pm_writel(HSB_MASK, mask);
410         spin_unlock_irqrestore(&pm_lock, flags);
411 }
412
413 static unsigned long hsb_clk_get_rate(struct clk *clk)
414 {
415         unsigned long cksel, shift = 0;
416
417         cksel = pm_readl(CKSEL);
418         if (cksel & PM_BIT(HSBDIV))
419                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
420
421         return bus_clk_get_rate(clk, shift);
422 }
423
424 void pba_clk_mode(struct clk *clk, int enabled)
425 {
426         unsigned long flags;
427         u32 mask;
428
429         spin_lock_irqsave(&pm_lock, flags);
430         mask = pm_readl(PBA_MASK);
431         if (enabled)
432                 mask |= 1 << clk->index;
433         else
434                 mask &= ~(1 << clk->index);
435         pm_writel(PBA_MASK, mask);
436         spin_unlock_irqrestore(&pm_lock, flags);
437 }
438
439 unsigned long pba_clk_get_rate(struct clk *clk)
440 {
441         unsigned long cksel, shift = 0;
442
443         cksel = pm_readl(CKSEL);
444         if (cksel & PM_BIT(PBADIV))
445                 shift = PM_BFEXT(PBASEL, cksel) + 1;
446
447         return bus_clk_get_rate(clk, shift);
448 }
449
450 static void pbb_clk_mode(struct clk *clk, int enabled)
451 {
452         unsigned long flags;
453         u32 mask;
454
455         spin_lock_irqsave(&pm_lock, flags);
456         mask = pm_readl(PBB_MASK);
457         if (enabled)
458                 mask |= 1 << clk->index;
459         else
460                 mask &= ~(1 << clk->index);
461         pm_writel(PBB_MASK, mask);
462         spin_unlock_irqrestore(&pm_lock, flags);
463 }
464
465 static unsigned long pbb_clk_get_rate(struct clk *clk)
466 {
467         unsigned long cksel, shift = 0;
468
469         cksel = pm_readl(CKSEL);
470         if (cksel & PM_BIT(PBBDIV))
471                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
472
473         return bus_clk_get_rate(clk, shift);
474 }
475
476 static struct clk cpu_clk = {
477         .name           = "cpu",
478         .get_rate       = cpu_clk_get_rate,
479         .set_rate       = cpu_clk_set_rate,
480         .users          = 1,
481 };
482 static struct clk hsb_clk = {
483         .name           = "hsb",
484         .parent         = &cpu_clk,
485         .get_rate       = hsb_clk_get_rate,
486 };
487 static struct clk pba_clk = {
488         .name           = "pba",
489         .parent         = &hsb_clk,
490         .mode           = hsb_clk_mode,
491         .get_rate       = pba_clk_get_rate,
492         .index          = 1,
493 };
494 static struct clk pbb_clk = {
495         .name           = "pbb",
496         .parent         = &hsb_clk,
497         .mode           = hsb_clk_mode,
498         .get_rate       = pbb_clk_get_rate,
499         .users          = 1,
500         .index          = 2,
501 };
502
503 /* --------------------------------------------------------------------
504  *  Generic Clock operations
505  * -------------------------------------------------------------------- */
506
507 static void genclk_mode(struct clk *clk, int enabled)
508 {
509         u32 control;
510
511         control = pm_readl(GCCTRL(clk->index));
512         if (enabled)
513                 control |= PM_BIT(CEN);
514         else
515                 control &= ~PM_BIT(CEN);
516         pm_writel(GCCTRL(clk->index), control);
517 }
518
519 static unsigned long genclk_get_rate(struct clk *clk)
520 {
521         u32 control;
522         unsigned long div = 1;
523
524         control = pm_readl(GCCTRL(clk->index));
525         if (control & PM_BIT(DIVEN))
526                 div = 2 * (PM_BFEXT(DIV, control) + 1);
527
528         return clk->parent->get_rate(clk->parent) / div;
529 }
530
531 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
532 {
533         u32 control;
534         unsigned long parent_rate, actual_rate, div;
535
536         parent_rate = clk->parent->get_rate(clk->parent);
537         control = pm_readl(GCCTRL(clk->index));
538
539         if (rate > 3 * parent_rate / 4) {
540                 actual_rate = parent_rate;
541                 control &= ~PM_BIT(DIVEN);
542         } else {
543                 div = (parent_rate + rate) / (2 * rate) - 1;
544                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
545                 actual_rate = parent_rate / (2 * (div + 1));
546         }
547
548         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
549                 clk->name, rate, actual_rate);
550
551         if (apply)
552                 pm_writel(GCCTRL(clk->index), control);
553
554         return actual_rate;
555 }
556
557 int genclk_set_parent(struct clk *clk, struct clk *parent)
558 {
559         u32 control;
560
561         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
562                 clk->name, parent->name, clk->parent->name);
563
564         control = pm_readl(GCCTRL(clk->index));
565
566         if (parent == &osc1 || parent == &pll1)
567                 control |= PM_BIT(OSCSEL);
568         else if (parent == &osc0 || parent == &pll0)
569                 control &= ~PM_BIT(OSCSEL);
570         else
571                 return -EINVAL;
572
573         if (parent == &pll0 || parent == &pll1)
574                 control |= PM_BIT(PLLSEL);
575         else
576                 control &= ~PM_BIT(PLLSEL);
577
578         pm_writel(GCCTRL(clk->index), control);
579         clk->parent = parent;
580
581         return 0;
582 }
583
584 static void __init genclk_init_parent(struct clk *clk)
585 {
586         u32 control;
587         struct clk *parent;
588
589         BUG_ON(clk->index > 7);
590
591         control = pm_readl(GCCTRL(clk->index));
592         if (control & PM_BIT(OSCSEL))
593                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
594         else
595                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
596
597         clk->parent = parent;
598 }
599
600 static struct dw_dma_platform_data dw_dmac0_data = {
601         .nr_channels    = 3,
602 };
603
604 static struct resource dw_dmac0_resource[] = {
605         PBMEM(0xff200000),
606         IRQ(2),
607 };
608 DEFINE_DEV_DATA(dw_dmac, 0);
609 DEV_CLK(hclk, dw_dmac0, hsb, 10);
610
611 /* --------------------------------------------------------------------
612  *  System peripherals
613  * -------------------------------------------------------------------- */
614 static struct resource at32_pm0_resource[] = {
615         {
616                 .start  = 0xfff00000,
617                 .end    = 0xfff0007f,
618                 .flags  = IORESOURCE_MEM,
619         },
620         IRQ(20),
621 };
622
623 static struct resource at32ap700x_rtc0_resource[] = {
624         {
625                 .start  = 0xfff00080,
626                 .end    = 0xfff000af,
627                 .flags  = IORESOURCE_MEM,
628         },
629         IRQ(21),
630 };
631
632 static struct resource at32_wdt0_resource[] = {
633         {
634                 .start  = 0xfff000b0,
635                 .end    = 0xfff000cf,
636                 .flags  = IORESOURCE_MEM,
637         },
638 };
639
640 static struct resource at32_eic0_resource[] = {
641         {
642                 .start  = 0xfff00100,
643                 .end    = 0xfff0013f,
644                 .flags  = IORESOURCE_MEM,
645         },
646         IRQ(19),
647 };
648
649 DEFINE_DEV(at32_pm, 0);
650 DEFINE_DEV(at32ap700x_rtc, 0);
651 DEFINE_DEV(at32_wdt, 0);
652 DEFINE_DEV(at32_eic, 0);
653
654 /*
655  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
656  * is always running.
657  */
658 static struct clk at32_pm_pclk = {
659         .name           = "pclk",
660         .dev            = &at32_pm0_device.dev,
661         .parent         = &pbb_clk,
662         .mode           = pbb_clk_mode,
663         .get_rate       = pbb_clk_get_rate,
664         .users          = 1,
665         .index          = 0,
666 };
667
668 static struct resource intc0_resource[] = {
669         PBMEM(0xfff00400),
670 };
671 struct platform_device at32_intc0_device = {
672         .name           = "intc",
673         .id             = 0,
674         .resource       = intc0_resource,
675         .num_resources  = ARRAY_SIZE(intc0_resource),
676 };
677 DEV_CLK(pclk, at32_intc0, pbb, 1);
678
679 static struct clk ebi_clk = {
680         .name           = "ebi",
681         .parent         = &hsb_clk,
682         .mode           = hsb_clk_mode,
683         .get_rate       = hsb_clk_get_rate,
684         .users          = 1,
685 };
686 static struct clk hramc_clk = {
687         .name           = "hramc",
688         .parent         = &hsb_clk,
689         .mode           = hsb_clk_mode,
690         .get_rate       = hsb_clk_get_rate,
691         .users          = 1,
692         .index          = 3,
693 };
694 static struct clk sdramc_clk = {
695         .name           = "sdramc_clk",
696         .parent         = &pbb_clk,
697         .mode           = pbb_clk_mode,
698         .get_rate       = pbb_clk_get_rate,
699         .users          = 1,
700         .index          = 14,
701 };
702
703 static struct resource smc0_resource[] = {
704         PBMEM(0xfff03400),
705 };
706 DEFINE_DEV(smc, 0);
707 DEV_CLK(pclk, smc0, pbb, 13);
708 DEV_CLK(mck, smc0, hsb, 0);
709
710 static struct platform_device pdc_device = {
711         .name           = "pdc",
712         .id             = 0,
713 };
714 DEV_CLK(hclk, pdc, hsb, 4);
715 DEV_CLK(pclk, pdc, pba, 16);
716
717 static struct clk pico_clk = {
718         .name           = "pico",
719         .parent         = &cpu_clk,
720         .mode           = cpu_clk_mode,
721         .get_rate       = cpu_clk_get_rate,
722         .users          = 1,
723 };
724
725 /* --------------------------------------------------------------------
726  * HMATRIX
727  * -------------------------------------------------------------------- */
728
729 struct clk at32_hmatrix_clk = {
730         .name           = "hmatrix_clk",
731         .parent         = &pbb_clk,
732         .mode           = pbb_clk_mode,
733         .get_rate       = pbb_clk_get_rate,
734         .index          = 2,
735         .users          = 1,
736 };
737
738 /*
739  * Set bits in the HMATRIX Special Function Register (SFR) used by the
740  * External Bus Interface (EBI). This can be used to enable special
741  * features like CompactFlash support, NAND Flash support, etc. on
742  * certain chipselects.
743  */
744 static inline void set_ebi_sfr_bits(u32 mask)
745 {
746         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
747 }
748
749 /* --------------------------------------------------------------------
750  *  Timer/Counter (TC)
751  * -------------------------------------------------------------------- */
752
753 static struct resource at32_tcb0_resource[] = {
754         PBMEM(0xfff00c00),
755         IRQ(22),
756 };
757 static struct platform_device at32_tcb0_device = {
758         .name           = "atmel_tcb",
759         .id             = 0,
760         .resource       = at32_tcb0_resource,
761         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
762 };
763 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
764
765 static struct resource at32_tcb1_resource[] = {
766         PBMEM(0xfff01000),
767         IRQ(23),
768 };
769 static struct platform_device at32_tcb1_device = {
770         .name           = "atmel_tcb",
771         .id             = 1,
772         .resource       = at32_tcb1_resource,
773         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
774 };
775 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
776
777 /* --------------------------------------------------------------------
778  *  PIO
779  * -------------------------------------------------------------------- */
780
781 static struct resource pio0_resource[] = {
782         PBMEM(0xffe02800),
783         IRQ(13),
784 };
785 DEFINE_DEV(pio, 0);
786 DEV_CLK(mck, pio0, pba, 10);
787
788 static struct resource pio1_resource[] = {
789         PBMEM(0xffe02c00),
790         IRQ(14),
791 };
792 DEFINE_DEV(pio, 1);
793 DEV_CLK(mck, pio1, pba, 11);
794
795 static struct resource pio2_resource[] = {
796         PBMEM(0xffe03000),
797         IRQ(15),
798 };
799 DEFINE_DEV(pio, 2);
800 DEV_CLK(mck, pio2, pba, 12);
801
802 static struct resource pio3_resource[] = {
803         PBMEM(0xffe03400),
804         IRQ(16),
805 };
806 DEFINE_DEV(pio, 3);
807 DEV_CLK(mck, pio3, pba, 13);
808
809 static struct resource pio4_resource[] = {
810         PBMEM(0xffe03800),
811         IRQ(17),
812 };
813 DEFINE_DEV(pio, 4);
814 DEV_CLK(mck, pio4, pba, 14);
815
816 static int __init system_device_init(void)
817 {
818         platform_device_register(&at32_pm0_device);
819         platform_device_register(&at32_intc0_device);
820         platform_device_register(&at32ap700x_rtc0_device);
821         platform_device_register(&at32_wdt0_device);
822         platform_device_register(&at32_eic0_device);
823         platform_device_register(&smc0_device);
824         platform_device_register(&pdc_device);
825         platform_device_register(&dw_dmac0_device);
826
827         platform_device_register(&at32_tcb0_device);
828         platform_device_register(&at32_tcb1_device);
829
830         platform_device_register(&pio0_device);
831         platform_device_register(&pio1_device);
832         platform_device_register(&pio2_device);
833         platform_device_register(&pio3_device);
834         platform_device_register(&pio4_device);
835
836         return 0;
837 }
838 core_initcall(system_device_init);
839
840 /* --------------------------------------------------------------------
841  *  PSIF
842  * -------------------------------------------------------------------- */
843 static struct resource atmel_psif0_resource[] __initdata = {
844         {
845                 .start  = 0xffe03c00,
846                 .end    = 0xffe03cff,
847                 .flags  = IORESOURCE_MEM,
848         },
849         IRQ(18),
850 };
851 static struct clk atmel_psif0_pclk = {
852         .name           = "pclk",
853         .parent         = &pba_clk,
854         .mode           = pba_clk_mode,
855         .get_rate       = pba_clk_get_rate,
856         .index          = 15,
857 };
858
859 static struct resource atmel_psif1_resource[] __initdata = {
860         {
861                 .start  = 0xffe03d00,
862                 .end    = 0xffe03dff,
863                 .flags  = IORESOURCE_MEM,
864         },
865         IRQ(18),
866 };
867 static struct clk atmel_psif1_pclk = {
868         .name           = "pclk",
869         .parent         = &pba_clk,
870         .mode           = pba_clk_mode,
871         .get_rate       = pba_clk_get_rate,
872         .index          = 15,
873 };
874
875 struct platform_device *__init at32_add_device_psif(unsigned int id)
876 {
877         struct platform_device *pdev;
878         u32 pin_mask;
879
880         if (!(id == 0 || id == 1))
881                 return NULL;
882
883         pdev = platform_device_alloc("atmel_psif", id);
884         if (!pdev)
885                 return NULL;
886
887         switch (id) {
888         case 0:
889                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
890
891                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
892                                         ARRAY_SIZE(atmel_psif0_resource)))
893                         goto err_add_resources;
894                 atmel_psif0_pclk.dev = &pdev->dev;
895                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
896                 break;
897         case 1:
898                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
899
900                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
901                                         ARRAY_SIZE(atmel_psif1_resource)))
902                         goto err_add_resources;
903                 atmel_psif1_pclk.dev = &pdev->dev;
904                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
905                 break;
906         default:
907                 return NULL;
908         }
909
910         platform_device_add(pdev);
911         return pdev;
912
913 err_add_resources:
914         platform_device_put(pdev);
915         return NULL;
916 }
917
918 /* --------------------------------------------------------------------
919  *  USART
920  * -------------------------------------------------------------------- */
921
922 static struct atmel_uart_data atmel_usart0_data = {
923         .use_dma_tx     = 1,
924         .use_dma_rx     = 1,
925 };
926 static struct resource atmel_usart0_resource[] = {
927         PBMEM(0xffe00c00),
928         IRQ(6),
929 };
930 DEFINE_DEV_DATA(atmel_usart, 0);
931 DEV_CLK(usart, atmel_usart0, pba, 3);
932
933 static struct atmel_uart_data atmel_usart1_data = {
934         .use_dma_tx     = 1,
935         .use_dma_rx     = 1,
936 };
937 static struct resource atmel_usart1_resource[] = {
938         PBMEM(0xffe01000),
939         IRQ(7),
940 };
941 DEFINE_DEV_DATA(atmel_usart, 1);
942 DEV_CLK(usart, atmel_usart1, pba, 4);
943
944 static struct atmel_uart_data atmel_usart2_data = {
945         .use_dma_tx     = 1,
946         .use_dma_rx     = 1,
947 };
948 static struct resource atmel_usart2_resource[] = {
949         PBMEM(0xffe01400),
950         IRQ(8),
951 };
952 DEFINE_DEV_DATA(atmel_usart, 2);
953 DEV_CLK(usart, atmel_usart2, pba, 5);
954
955 static struct atmel_uart_data atmel_usart3_data = {
956         .use_dma_tx     = 1,
957         .use_dma_rx     = 1,
958 };
959 static struct resource atmel_usart3_resource[] = {
960         PBMEM(0xffe01800),
961         IRQ(9),
962 };
963 DEFINE_DEV_DATA(atmel_usart, 3);
964 DEV_CLK(usart, atmel_usart3, pba, 6);
965
966 static inline void configure_usart0_pins(void)
967 {
968         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
969
970         select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
971 }
972
973 static inline void configure_usart1_pins(void)
974 {
975         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
976
977         select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
978 }
979
980 static inline void configure_usart2_pins(void)
981 {
982         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
983
984         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
985 }
986
987 static inline void configure_usart3_pins(void)
988 {
989         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
990
991         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
992 }
993
994 static struct platform_device *__initdata at32_usarts[4];
995
996 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
997 {
998         struct platform_device *pdev;
999
1000         switch (hw_id) {
1001         case 0:
1002                 pdev = &atmel_usart0_device;
1003                 configure_usart0_pins();
1004                 break;
1005         case 1:
1006                 pdev = &atmel_usart1_device;
1007                 configure_usart1_pins();
1008                 break;
1009         case 2:
1010                 pdev = &atmel_usart2_device;
1011                 configure_usart2_pins();
1012                 break;
1013         case 3:
1014                 pdev = &atmel_usart3_device;
1015                 configure_usart3_pins();
1016                 break;
1017         default:
1018                 return;
1019         }
1020
1021         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1022                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1023                 struct atmel_uart_data *data = pdev->dev.platform_data;
1024                 data->regs = (void __iomem *)pdev->resource[0].start;
1025         }
1026
1027         pdev->id = line;
1028         at32_usarts[line] = pdev;
1029 }
1030
1031 struct platform_device *__init at32_add_device_usart(unsigned int id)
1032 {
1033         platform_device_register(at32_usarts[id]);
1034         return at32_usarts[id];
1035 }
1036
1037 struct platform_device *atmel_default_console_device;
1038
1039 void __init at32_setup_serial_console(unsigned int usart_id)
1040 {
1041         atmel_default_console_device = at32_usarts[usart_id];
1042 }
1043
1044 /* --------------------------------------------------------------------
1045  *  Ethernet
1046  * -------------------------------------------------------------------- */
1047
1048 #ifdef CONFIG_CPU_AT32AP7000
1049 static struct eth_platform_data macb0_data;
1050 static struct resource macb0_resource[] = {
1051         PBMEM(0xfff01800),
1052         IRQ(25),
1053 };
1054 DEFINE_DEV_DATA(macb, 0);
1055 DEV_CLK(hclk, macb0, hsb, 8);
1056 DEV_CLK(pclk, macb0, pbb, 6);
1057
1058 static struct eth_platform_data macb1_data;
1059 static struct resource macb1_resource[] = {
1060         PBMEM(0xfff01c00),
1061         IRQ(26),
1062 };
1063 DEFINE_DEV_DATA(macb, 1);
1064 DEV_CLK(hclk, macb1, hsb, 9);
1065 DEV_CLK(pclk, macb1, pbb, 7);
1066
1067 struct platform_device *__init
1068 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1069 {
1070         struct platform_device *pdev;
1071         u32 pin_mask;
1072
1073         switch (id) {
1074         case 0:
1075                 pdev = &macb0_device;
1076
1077                 pin_mask  = (1 << 3);   /* TXD0 */
1078                 pin_mask |= (1 << 4);   /* TXD1 */
1079                 pin_mask |= (1 << 7);   /* TXEN */
1080                 pin_mask |= (1 << 8);   /* TXCK */
1081                 pin_mask |= (1 << 9);   /* RXD0 */
1082                 pin_mask |= (1 << 10);  /* RXD1 */
1083                 pin_mask |= (1 << 13);  /* RXER */
1084                 pin_mask |= (1 << 15);  /* RXDV */
1085                 pin_mask |= (1 << 16);  /* MDC  */
1086                 pin_mask |= (1 << 17);  /* MDIO */
1087
1088                 if (!data->is_rmii) {
1089                         pin_mask |= (1 << 0);   /* COL  */
1090                         pin_mask |= (1 << 1);   /* CRS  */
1091                         pin_mask |= (1 << 2);   /* TXER */
1092                         pin_mask |= (1 << 5);   /* TXD2 */
1093                         pin_mask |= (1 << 6);   /* TXD3 */
1094                         pin_mask |= (1 << 11);  /* RXD2 */
1095                         pin_mask |= (1 << 12);  /* RXD3 */
1096                         pin_mask |= (1 << 14);  /* RXCK */
1097 #ifndef CONFIG_BOARD_MIMC200
1098                         pin_mask |= (1 << 18);  /* SPD  */
1099 #endif
1100                 }
1101
1102                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1103
1104                 break;
1105
1106         case 1:
1107                 pdev = &macb1_device;
1108
1109                 pin_mask  = (1 << 13);  /* TXD0 */
1110                 pin_mask |= (1 << 14);  /* TXD1 */
1111                 pin_mask |= (1 << 11);  /* TXEN */
1112                 pin_mask |= (1 << 12);  /* TXCK */
1113                 pin_mask |= (1 << 10);  /* RXD0 */
1114                 pin_mask |= (1 << 6);   /* RXD1 */
1115                 pin_mask |= (1 << 5);   /* RXER */
1116                 pin_mask |= (1 << 4);   /* RXDV */
1117                 pin_mask |= (1 << 3);   /* MDC  */
1118                 pin_mask |= (1 << 2);   /* MDIO */
1119
1120 #ifndef CONFIG_BOARD_MIMC200
1121                 if (!data->is_rmii)
1122                         pin_mask |= (1 << 15);  /* SPD  */
1123 #endif
1124
1125                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1126
1127                 if (!data->is_rmii) {
1128                         pin_mask  = (1 << 19);  /* COL  */
1129                         pin_mask |= (1 << 23);  /* CRS  */
1130                         pin_mask |= (1 << 26);  /* TXER */
1131                         pin_mask |= (1 << 27);  /* TXD2 */
1132                         pin_mask |= (1 << 28);  /* TXD3 */
1133                         pin_mask |= (1 << 29);  /* RXD2 */
1134                         pin_mask |= (1 << 30);  /* RXD3 */
1135                         pin_mask |= (1 << 24);  /* RXCK */
1136
1137                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1138                 }
1139                 break;
1140
1141         default:
1142                 return NULL;
1143         }
1144
1145         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1146         platform_device_register(pdev);
1147
1148         return pdev;
1149 }
1150 #endif
1151
1152 /* --------------------------------------------------------------------
1153  *  SPI
1154  * -------------------------------------------------------------------- */
1155 static struct resource atmel_spi0_resource[] = {
1156         PBMEM(0xffe00000),
1157         IRQ(3),
1158 };
1159 DEFINE_DEV(atmel_spi, 0);
1160 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1161
1162 static struct resource atmel_spi1_resource[] = {
1163         PBMEM(0xffe00400),
1164         IRQ(4),
1165 };
1166 DEFINE_DEV(atmel_spi, 1);
1167 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1168
1169 static void __init
1170 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1171                       unsigned int n, const u8 *pins)
1172 {
1173         unsigned int pin, mode;
1174
1175         for (; n; n--, b++) {
1176                 b->bus_num = bus_num;
1177                 if (b->chip_select >= 4)
1178                         continue;
1179                 pin = (unsigned)b->controller_data;
1180                 if (!pin) {
1181                         pin = pins[b->chip_select];
1182                         b->controller_data = (void *)pin;
1183                 }
1184                 mode = AT32_GPIOF_OUTPUT;
1185                 if (!(b->mode & SPI_CS_HIGH))
1186                         mode |= AT32_GPIOF_HIGH;
1187                 at32_select_gpio(pin, mode);
1188         }
1189 }
1190
1191 struct platform_device *__init
1192 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1193 {
1194         /*
1195          * Manage the chipselects as GPIOs, normally using the same pins
1196          * the SPI controller expects; but boards can use other pins.
1197          */
1198         static u8 __initdata spi0_pins[] =
1199                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1200                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1201         static u8 __initdata spi1_pins[] =
1202                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1203                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1204         struct platform_device *pdev;
1205         u32 pin_mask;
1206
1207         switch (id) {
1208         case 0:
1209                 pdev = &atmel_spi0_device;
1210                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1211
1212                 /* pullup MISO so a level is always defined */
1213                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1214                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1215
1216                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1217                 break;
1218
1219         case 1:
1220                 pdev = &atmel_spi1_device;
1221                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1222
1223                 /* pullup MISO so a level is always defined */
1224                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1225                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1226
1227                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1228                 break;
1229
1230         default:
1231                 return NULL;
1232         }
1233
1234         spi_register_board_info(b, n);
1235         platform_device_register(pdev);
1236         return pdev;
1237 }
1238
1239 /* --------------------------------------------------------------------
1240  *  TWI
1241  * -------------------------------------------------------------------- */
1242 static struct resource atmel_twi0_resource[] __initdata = {
1243         PBMEM(0xffe00800),
1244         IRQ(5),
1245 };
1246 static struct clk atmel_twi0_pclk = {
1247         .name           = "twi_pclk",
1248         .parent         = &pba_clk,
1249         .mode           = pba_clk_mode,
1250         .get_rate       = pba_clk_get_rate,
1251         .index          = 2,
1252 };
1253
1254 struct platform_device *__init at32_add_device_twi(unsigned int id,
1255                                                     struct i2c_board_info *b,
1256                                                     unsigned int n)
1257 {
1258         struct platform_device *pdev;
1259         u32 pin_mask;
1260
1261         if (id != 0)
1262                 return NULL;
1263
1264         pdev = platform_device_alloc("atmel_twi", id);
1265         if (!pdev)
1266                 return NULL;
1267
1268         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1269                                 ARRAY_SIZE(atmel_twi0_resource)))
1270                 goto err_add_resources;
1271
1272         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1273
1274         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1275
1276         atmel_twi0_pclk.dev = &pdev->dev;
1277
1278         if (b)
1279                 i2c_register_board_info(id, b, n);
1280
1281         platform_device_add(pdev);
1282         return pdev;
1283
1284 err_add_resources:
1285         platform_device_put(pdev);
1286         return NULL;
1287 }
1288
1289 /* --------------------------------------------------------------------
1290  * MMC
1291  * -------------------------------------------------------------------- */
1292 static struct resource atmel_mci0_resource[] __initdata = {
1293         PBMEM(0xfff02400),
1294         IRQ(28),
1295 };
1296 static struct clk atmel_mci0_pclk = {
1297         .name           = "mci_clk",
1298         .parent         = &pbb_clk,
1299         .mode           = pbb_clk_mode,
1300         .get_rate       = pbb_clk_get_rate,
1301         .index          = 9,
1302 };
1303
1304 struct platform_device *__init
1305 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1306 {
1307         struct platform_device          *pdev;
1308         struct dw_dma_slave             *dws = &data->dma_slave;
1309         u32                             pioa_mask;
1310         u32                             piob_mask;
1311
1312         if (id != 0 || !data)
1313                 return NULL;
1314
1315         /* Must have at least one usable slot */
1316         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1317                 return NULL;
1318
1319         pdev = platform_device_alloc("atmel_mci", id);
1320         if (!pdev)
1321                 goto fail;
1322
1323         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1324                                 ARRAY_SIZE(atmel_mci0_resource)))
1325                 goto fail;
1326
1327         dws->dma_dev = &dw_dmac0_device.dev;
1328         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1329         dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1330                                 | DWC_CFGH_DST_PER(1));
1331         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1332                                 | DWC_CFGL_HS_SRC_POL);
1333
1334         if (platform_device_add_data(pdev, data,
1335                                 sizeof(struct mci_platform_data)))
1336                 goto fail;
1337
1338         /* CLK line is common to both slots */
1339         pioa_mask = 1 << 10;
1340
1341         switch (data->slot[0].bus_width) {
1342         case 4:
1343                 pioa_mask |= 1 << 13;           /* DATA1 */
1344                 pioa_mask |= 1 << 14;           /* DATA2 */
1345                 pioa_mask |= 1 << 15;           /* DATA3 */
1346                 /* fall through */
1347         case 1:
1348                 pioa_mask |= 1 << 11;           /* CMD   */
1349                 pioa_mask |= 1 << 12;           /* DATA0 */
1350
1351                 if (gpio_is_valid(data->slot[0].detect_pin))
1352                         at32_select_gpio(data->slot[0].detect_pin, 0);
1353                 if (gpio_is_valid(data->slot[0].wp_pin))
1354                         at32_select_gpio(data->slot[0].wp_pin, 0);
1355                 break;
1356         case 0:
1357                 /* Slot is unused */
1358                 break;
1359         default:
1360                 goto fail;
1361         }
1362
1363         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1364         piob_mask = 0;
1365
1366         switch (data->slot[1].bus_width) {
1367         case 4:
1368                 piob_mask |= 1 <<  8;           /* DATA1 */
1369                 piob_mask |= 1 <<  9;           /* DATA2 */
1370                 piob_mask |= 1 << 10;           /* DATA3 */
1371                 /* fall through */
1372         case 1:
1373                 piob_mask |= 1 <<  6;           /* CMD   */
1374                 piob_mask |= 1 <<  7;           /* DATA0 */
1375                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1376
1377                 if (gpio_is_valid(data->slot[1].detect_pin))
1378                         at32_select_gpio(data->slot[1].detect_pin, 0);
1379                 if (gpio_is_valid(data->slot[1].wp_pin))
1380                         at32_select_gpio(data->slot[1].wp_pin, 0);
1381                 break;
1382         case 0:
1383                 /* Slot is unused */
1384                 break;
1385         default:
1386                 if (!data->slot[0].bus_width)
1387                         goto fail;
1388
1389                 data->slot[1].bus_width = 0;
1390                 break;
1391         }
1392
1393         atmel_mci0_pclk.dev = &pdev->dev;
1394
1395         platform_device_add(pdev);
1396         return pdev;
1397
1398 fail:
1399         platform_device_put(pdev);
1400         return NULL;
1401 }
1402
1403 /* --------------------------------------------------------------------
1404  *  LCDC
1405  * -------------------------------------------------------------------- */
1406 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1407 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1408 static struct resource atmel_lcdfb0_resource[] = {
1409         {
1410                 .start          = 0xff000000,
1411                 .end            = 0xff000fff,
1412                 .flags          = IORESOURCE_MEM,
1413         },
1414         IRQ(1),
1415         {
1416                 /* Placeholder for pre-allocated fb memory */
1417                 .start          = 0x00000000,
1418                 .end            = 0x00000000,
1419                 .flags          = 0,
1420         },
1421 };
1422 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1423 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1424 static struct clk atmel_lcdfb0_pixclk = {
1425         .name           = "lcdc_clk",
1426         .dev            = &atmel_lcdfb0_device.dev,
1427         .mode           = genclk_mode,
1428         .get_rate       = genclk_get_rate,
1429         .set_rate       = genclk_set_rate,
1430         .set_parent     = genclk_set_parent,
1431         .index          = 7,
1432 };
1433
1434 struct platform_device *__init
1435 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1436                      unsigned long fbmem_start, unsigned long fbmem_len,
1437                      u64 pin_mask)
1438 {
1439         struct platform_device *pdev;
1440         struct atmel_lcdfb_info *info;
1441         struct fb_monspecs *monspecs;
1442         struct fb_videomode *modedb;
1443         unsigned int modedb_size;
1444         u32 portc_mask, portd_mask, porte_mask;
1445
1446         /*
1447          * Do a deep copy of the fb data, monspecs and modedb. Make
1448          * sure all allocations are done before setting up the
1449          * portmux.
1450          */
1451         monspecs = kmemdup(data->default_monspecs,
1452                            sizeof(struct fb_monspecs), GFP_KERNEL);
1453         if (!monspecs)
1454                 return NULL;
1455
1456         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1457         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1458         if (!modedb)
1459                 goto err_dup_modedb;
1460         monspecs->modedb = modedb;
1461
1462         switch (id) {
1463         case 0:
1464                 pdev = &atmel_lcdfb0_device;
1465
1466                 if (pin_mask == 0ULL)
1467                         /* Default to "full" lcdc control signals and 24bit */
1468                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1469
1470                 /* LCDC on port C */
1471                 portc_mask = pin_mask & 0xfff80000;
1472                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1473
1474                 /* LCDC on port D */
1475                 portd_mask = pin_mask & 0x0003ffff;
1476                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1477
1478                 /* LCDC on port E */
1479                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1480                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1481
1482                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1483                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1484                 break;
1485
1486         default:
1487                 goto err_invalid_id;
1488         }
1489
1490         if (fbmem_len) {
1491                 pdev->resource[2].start = fbmem_start;
1492                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1493                 pdev->resource[2].flags = IORESOURCE_MEM;
1494         }
1495
1496         info = pdev->dev.platform_data;
1497         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1498         info->default_monspecs = monspecs;
1499
1500         platform_device_register(pdev);
1501         return pdev;
1502
1503 err_invalid_id:
1504         kfree(modedb);
1505 err_dup_modedb:
1506         kfree(monspecs);
1507         return NULL;
1508 }
1509 #endif
1510
1511 /* --------------------------------------------------------------------
1512  *  PWM
1513  * -------------------------------------------------------------------- */
1514 static struct resource atmel_pwm0_resource[] __initdata = {
1515         PBMEM(0xfff01400),
1516         IRQ(24),
1517 };
1518 static struct clk atmel_pwm0_mck = {
1519         .name           = "pwm_clk",
1520         .parent         = &pbb_clk,
1521         .mode           = pbb_clk_mode,
1522         .get_rate       = pbb_clk_get_rate,
1523         .index          = 5,
1524 };
1525
1526 struct platform_device *__init at32_add_device_pwm(u32 mask)
1527 {
1528         struct platform_device *pdev;
1529         u32 pin_mask;
1530
1531         if (!mask)
1532                 return NULL;
1533
1534         pdev = platform_device_alloc("atmel_pwm", 0);
1535         if (!pdev)
1536                 return NULL;
1537
1538         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1539                                 ARRAY_SIZE(atmel_pwm0_resource)))
1540                 goto out_free_pdev;
1541
1542         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1543                 goto out_free_pdev;
1544
1545         pin_mask = 0;
1546         if (mask & (1 << 0))
1547                 pin_mask |= (1 << 28);
1548         if (mask & (1 << 1))
1549                 pin_mask |= (1 << 29);
1550         if (pin_mask > 0)
1551                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1552
1553         pin_mask = 0;
1554         if (mask & (1 << 2))
1555                 pin_mask |= (1 << 21);
1556         if (mask & (1 << 3))
1557                 pin_mask |= (1 << 22);
1558         if (pin_mask > 0)
1559                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1560
1561         atmel_pwm0_mck.dev = &pdev->dev;
1562
1563         platform_device_add(pdev);
1564
1565         return pdev;
1566
1567 out_free_pdev:
1568         platform_device_put(pdev);
1569         return NULL;
1570 }
1571
1572 /* --------------------------------------------------------------------
1573  *  SSC
1574  * -------------------------------------------------------------------- */
1575 static struct resource ssc0_resource[] = {
1576         PBMEM(0xffe01c00),
1577         IRQ(10),
1578 };
1579 DEFINE_DEV(ssc, 0);
1580 DEV_CLK(pclk, ssc0, pba, 7);
1581
1582 static struct resource ssc1_resource[] = {
1583         PBMEM(0xffe02000),
1584         IRQ(11),
1585 };
1586 DEFINE_DEV(ssc, 1);
1587 DEV_CLK(pclk, ssc1, pba, 8);
1588
1589 static struct resource ssc2_resource[] = {
1590         PBMEM(0xffe02400),
1591         IRQ(12),
1592 };
1593 DEFINE_DEV(ssc, 2);
1594 DEV_CLK(pclk, ssc2, pba, 9);
1595
1596 struct platform_device *__init
1597 at32_add_device_ssc(unsigned int id, unsigned int flags)
1598 {
1599         struct platform_device *pdev;
1600         u32 pin_mask = 0;
1601
1602         switch (id) {
1603         case 0:
1604                 pdev = &ssc0_device;
1605                 if (flags & ATMEL_SSC_RF)
1606                         pin_mask |= (1 << 21);  /* RF */
1607                 if (flags & ATMEL_SSC_RK)
1608                         pin_mask |= (1 << 22);  /* RK */
1609                 if (flags & ATMEL_SSC_TK)
1610                         pin_mask |= (1 << 23);  /* TK */
1611                 if (flags & ATMEL_SSC_TF)
1612                         pin_mask |= (1 << 24);  /* TF */
1613                 if (flags & ATMEL_SSC_TD)
1614                         pin_mask |= (1 << 25);  /* TD */
1615                 if (flags & ATMEL_SSC_RD)
1616                         pin_mask |= (1 << 26);  /* RD */
1617
1618                 if (pin_mask > 0)
1619                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1620
1621                 break;
1622         case 1:
1623                 pdev = &ssc1_device;
1624                 if (flags & ATMEL_SSC_RF)
1625                         pin_mask |= (1 << 0);   /* RF */
1626                 if (flags & ATMEL_SSC_RK)
1627                         pin_mask |= (1 << 1);   /* RK */
1628                 if (flags & ATMEL_SSC_TK)
1629                         pin_mask |= (1 << 2);   /* TK */
1630                 if (flags & ATMEL_SSC_TF)
1631                         pin_mask |= (1 << 3);   /* TF */
1632                 if (flags & ATMEL_SSC_TD)
1633                         pin_mask |= (1 << 4);   /* TD */
1634                 if (flags & ATMEL_SSC_RD)
1635                         pin_mask |= (1 << 5);   /* RD */
1636
1637                 if (pin_mask > 0)
1638                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1639
1640                 break;
1641         case 2:
1642                 pdev = &ssc2_device;
1643                 if (flags & ATMEL_SSC_TD)
1644                         pin_mask |= (1 << 13);  /* TD */
1645                 if (flags & ATMEL_SSC_RD)
1646                         pin_mask |= (1 << 14);  /* RD */
1647                 if (flags & ATMEL_SSC_TK)
1648                         pin_mask |= (1 << 15);  /* TK */
1649                 if (flags & ATMEL_SSC_TF)
1650                         pin_mask |= (1 << 16);  /* TF */
1651                 if (flags & ATMEL_SSC_RF)
1652                         pin_mask |= (1 << 17);  /* RF */
1653                 if (flags & ATMEL_SSC_RK)
1654                         pin_mask |= (1 << 18);  /* RK */
1655
1656                 if (pin_mask > 0)
1657                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1658
1659                 break;
1660         default:
1661                 return NULL;
1662         }
1663
1664         platform_device_register(pdev);
1665         return pdev;
1666 }
1667
1668 /* --------------------------------------------------------------------
1669  *  USB Device Controller
1670  * -------------------------------------------------------------------- */
1671 static struct resource usba0_resource[] __initdata = {
1672         {
1673                 .start          = 0xff300000,
1674                 .end            = 0xff3fffff,
1675                 .flags          = IORESOURCE_MEM,
1676         }, {
1677                 .start          = 0xfff03000,
1678                 .end            = 0xfff033ff,
1679                 .flags          = IORESOURCE_MEM,
1680         },
1681         IRQ(31),
1682 };
1683 static struct clk usba0_pclk = {
1684         .name           = "pclk",
1685         .parent         = &pbb_clk,
1686         .mode           = pbb_clk_mode,
1687         .get_rate       = pbb_clk_get_rate,
1688         .index          = 12,
1689 };
1690 static struct clk usba0_hclk = {
1691         .name           = "hclk",
1692         .parent         = &hsb_clk,
1693         .mode           = hsb_clk_mode,
1694         .get_rate       = hsb_clk_get_rate,
1695         .index          = 6,
1696 };
1697
1698 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1699         [idx] = {                                               \
1700                 .name           = nam,                          \
1701                 .index          = idx,                          \
1702                 .fifo_size      = maxpkt,                       \
1703                 .nr_banks       = maxbk,                        \
1704                 .can_dma        = dma,                          \
1705                 .can_isoc       = isoc,                         \
1706         }
1707
1708 static struct usba_ep_data at32_usba_ep[] __initdata = {
1709         EP("ep0",     0,   64, 1, 0, 0),
1710         EP("ep1",     1,  512, 2, 1, 1),
1711         EP("ep2",     2,  512, 2, 1, 1),
1712         EP("ep3-int", 3,   64, 3, 1, 0),
1713         EP("ep4-int", 4,   64, 3, 1, 0),
1714         EP("ep5",     5, 1024, 3, 1, 1),
1715         EP("ep6",     6, 1024, 3, 1, 1),
1716 };
1717
1718 #undef EP
1719
1720 struct platform_device *__init
1721 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1722 {
1723         /*
1724          * pdata doesn't have room for any endpoints, so we need to
1725          * append room for the ones we need right after it.
1726          */
1727         struct {
1728                 struct usba_platform_data pdata;
1729                 struct usba_ep_data ep[7];
1730         } usba_data;
1731         struct platform_device *pdev;
1732
1733         if (id != 0)
1734                 return NULL;
1735
1736         pdev = platform_device_alloc("atmel_usba_udc", 0);
1737         if (!pdev)
1738                 return NULL;
1739
1740         if (platform_device_add_resources(pdev, usba0_resource,
1741                                           ARRAY_SIZE(usba0_resource)))
1742                 goto out_free_pdev;
1743
1744         if (data)
1745                 usba_data.pdata.vbus_pin = data->vbus_pin;
1746         else
1747                 usba_data.pdata.vbus_pin = -EINVAL;
1748
1749         data = &usba_data.pdata;
1750         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1751         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1752
1753         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1754                 goto out_free_pdev;
1755
1756         if (data->vbus_pin >= 0)
1757                 at32_select_gpio(data->vbus_pin, 0);
1758
1759         usba0_pclk.dev = &pdev->dev;
1760         usba0_hclk.dev = &pdev->dev;
1761
1762         platform_device_add(pdev);
1763
1764         return pdev;
1765
1766 out_free_pdev:
1767         platform_device_put(pdev);
1768         return NULL;
1769 }
1770
1771 /* --------------------------------------------------------------------
1772  * IDE / CompactFlash
1773  * -------------------------------------------------------------------- */
1774 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1775 static struct resource at32_smc_cs4_resource[] __initdata = {
1776         {
1777                 .start  = 0x04000000,
1778                 .end    = 0x07ffffff,
1779                 .flags  = IORESOURCE_MEM,
1780         },
1781         IRQ(~0UL), /* Magic IRQ will be overridden */
1782 };
1783 static struct resource at32_smc_cs5_resource[] __initdata = {
1784         {
1785                 .start  = 0x20000000,
1786                 .end    = 0x23ffffff,
1787                 .flags  = IORESOURCE_MEM,
1788         },
1789         IRQ(~0UL), /* Magic IRQ will be overridden */
1790 };
1791
1792 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1793                 unsigned int cs, unsigned int extint)
1794 {
1795         static unsigned int extint_pin_map[4] __initdata = {
1796                 (1 << 25),
1797                 (1 << 26),
1798                 (1 << 27),
1799                 (1 << 28),
1800         };
1801         static bool common_pins_initialized __initdata = false;
1802         unsigned int extint_pin;
1803         int ret;
1804         u32 pin_mask;
1805
1806         if (extint >= ARRAY_SIZE(extint_pin_map))
1807                 return -EINVAL;
1808         extint_pin = extint_pin_map[extint];
1809
1810         switch (cs) {
1811         case 4:
1812                 ret = platform_device_add_resources(pdev,
1813                                 at32_smc_cs4_resource,
1814                                 ARRAY_SIZE(at32_smc_cs4_resource));
1815                 if (ret)
1816                         return ret;
1817
1818                 /* NCS4   -> OE_N  */
1819                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1820                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1821                 break;
1822         case 5:
1823                 ret = platform_device_add_resources(pdev,
1824                                 at32_smc_cs5_resource,
1825                                 ARRAY_SIZE(at32_smc_cs5_resource));
1826                 if (ret)
1827                         return ret;
1828
1829                 /* NCS5   -> OE_N  */
1830                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1831                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1832                 break;
1833         default:
1834                 return -EINVAL;
1835         }
1836
1837         if (!common_pins_initialized) {
1838                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1839                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1840                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1841                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1842
1843                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1844
1845                 common_pins_initialized = true;
1846         }
1847
1848         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1849
1850         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1851         pdev->resource[1].end = pdev->resource[1].start;
1852
1853         return 0;
1854 }
1855
1856 struct platform_device *__init
1857 at32_add_device_ide(unsigned int id, unsigned int extint,
1858                     struct ide_platform_data *data)
1859 {
1860         struct platform_device *pdev;
1861
1862         pdev = platform_device_alloc("at32_ide", id);
1863         if (!pdev)
1864                 goto fail;
1865
1866         if (platform_device_add_data(pdev, data,
1867                                 sizeof(struct ide_platform_data)))
1868                 goto fail;
1869
1870         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1871                 goto fail;
1872
1873         platform_device_add(pdev);
1874         return pdev;
1875
1876 fail:
1877         platform_device_put(pdev);
1878         return NULL;
1879 }
1880
1881 struct platform_device *__init
1882 at32_add_device_cf(unsigned int id, unsigned int extint,
1883                     struct cf_platform_data *data)
1884 {
1885         struct platform_device *pdev;
1886
1887         pdev = platform_device_alloc("at32_cf", id);
1888         if (!pdev)
1889                 goto fail;
1890
1891         if (platform_device_add_data(pdev, data,
1892                                 sizeof(struct cf_platform_data)))
1893                 goto fail;
1894
1895         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1896                 goto fail;
1897
1898         if (gpio_is_valid(data->detect_pin))
1899                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1900         if (gpio_is_valid(data->reset_pin))
1901                 at32_select_gpio(data->reset_pin, 0);
1902         if (gpio_is_valid(data->vcc_pin))
1903                 at32_select_gpio(data->vcc_pin, 0);
1904         /* READY is used as extint, so we can't select it as gpio */
1905
1906         platform_device_add(pdev);
1907         return pdev;
1908
1909 fail:
1910         platform_device_put(pdev);
1911         return NULL;
1912 }
1913 #endif
1914
1915 /* --------------------------------------------------------------------
1916  * NAND Flash / SmartMedia
1917  * -------------------------------------------------------------------- */
1918 static struct resource smc_cs3_resource[] __initdata = {
1919         {
1920                 .start  = 0x0c000000,
1921                 .end    = 0x0fffffff,
1922                 .flags  = IORESOURCE_MEM,
1923         }, {
1924                 .start  = 0xfff03c00,
1925                 .end    = 0xfff03fff,
1926                 .flags  = IORESOURCE_MEM,
1927         },
1928 };
1929
1930 struct platform_device *__init
1931 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1932 {
1933         struct platform_device *pdev;
1934
1935         if (id != 0 || !data)
1936                 return NULL;
1937
1938         pdev = platform_device_alloc("atmel_nand", id);
1939         if (!pdev)
1940                 goto fail;
1941
1942         if (platform_device_add_resources(pdev, smc_cs3_resource,
1943                                 ARRAY_SIZE(smc_cs3_resource)))
1944                 goto fail;
1945
1946         if (platform_device_add_data(pdev, data,
1947                                 sizeof(struct atmel_nand_data)))
1948                 goto fail;
1949
1950         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1951         if (data->enable_pin)
1952                 at32_select_gpio(data->enable_pin,
1953                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1954         if (data->rdy_pin)
1955                 at32_select_gpio(data->rdy_pin, 0);
1956         if (data->det_pin)
1957                 at32_select_gpio(data->det_pin, 0);
1958
1959         platform_device_add(pdev);
1960         return pdev;
1961
1962 fail:
1963         platform_device_put(pdev);
1964         return NULL;
1965 }
1966
1967 /* --------------------------------------------------------------------
1968  * AC97C
1969  * -------------------------------------------------------------------- */
1970 static struct resource atmel_ac97c0_resource[] __initdata = {
1971         PBMEM(0xfff02800),
1972         IRQ(29),
1973 };
1974 static struct clk atmel_ac97c0_pclk = {
1975         .name           = "pclk",
1976         .parent         = &pbb_clk,
1977         .mode           = pbb_clk_mode,
1978         .get_rate       = pbb_clk_get_rate,
1979         .index          = 10,
1980 };
1981
1982 struct platform_device *__init
1983 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1984 {
1985         struct platform_device *pdev;
1986         struct ac97c_platform_data _data;
1987         u32 pin_mask;
1988
1989         if (id != 0)
1990                 return NULL;
1991
1992         pdev = platform_device_alloc("atmel_ac97c", id);
1993         if (!pdev)
1994                 return NULL;
1995
1996         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1997                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1998                 goto fail;
1999
2000         if (!data) {
2001                 data = &_data;
2002                 memset(data, 0, sizeof(struct ac97c_platform_data));
2003                 data->reset_pin = GPIO_PIN_NONE;
2004         }
2005
2006         data->dma_rx_periph_id = 3;
2007         data->dma_tx_periph_id = 4;
2008         data->dma_controller_id = 0;
2009
2010         if (platform_device_add_data(pdev, data,
2011                                 sizeof(struct ac97c_platform_data)))
2012                 goto fail;
2013
2014         pin_mask  = (1 << 20) | (1 << 21);      /* SDO & SYNC */
2015         pin_mask |= (1 << 22) | (1 << 23);      /* SCLK & SDI */
2016
2017         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2018
2019         /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
2020         if (data->reset_pin != GPIO_PIN_NONE)
2021                 at32_select_gpio(data->reset_pin, 0);
2022
2023         atmel_ac97c0_pclk.dev = &pdev->dev;
2024
2025         platform_device_add(pdev);
2026         return pdev;
2027
2028 fail:
2029         platform_device_put(pdev);
2030         return NULL;
2031 }
2032
2033 /* --------------------------------------------------------------------
2034  * ABDAC
2035  * -------------------------------------------------------------------- */
2036 static struct resource abdac0_resource[] __initdata = {
2037         PBMEM(0xfff02000),
2038         IRQ(27),
2039 };
2040 static struct clk abdac0_pclk = {
2041         .name           = "pclk",
2042         .parent         = &pbb_clk,
2043         .mode           = pbb_clk_mode,
2044         .get_rate       = pbb_clk_get_rate,
2045         .index          = 8,
2046 };
2047 static struct clk abdac0_sample_clk = {
2048         .name           = "sample_clk",
2049         .mode           = genclk_mode,
2050         .get_rate       = genclk_get_rate,
2051         .set_rate       = genclk_set_rate,
2052         .set_parent     = genclk_set_parent,
2053         .index          = 6,
2054 };
2055
2056 struct platform_device *__init at32_add_device_abdac(unsigned int id)
2057 {
2058         struct platform_device *pdev;
2059         u32 pin_mask;
2060
2061         if (id != 0)
2062                 return NULL;
2063
2064         pdev = platform_device_alloc("abdac", id);
2065         if (!pdev)
2066                 return NULL;
2067
2068         if (platform_device_add_resources(pdev, abdac0_resource,
2069                                 ARRAY_SIZE(abdac0_resource)))
2070                 goto err_add_resources;
2071
2072         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2073         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2074
2075         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2076
2077         abdac0_pclk.dev = &pdev->dev;
2078         abdac0_sample_clk.dev = &pdev->dev;
2079
2080         platform_device_add(pdev);
2081         return pdev;
2082
2083 err_add_resources:
2084         platform_device_put(pdev);
2085         return NULL;
2086 }
2087
2088 /* --------------------------------------------------------------------
2089  *  GCLK
2090  * -------------------------------------------------------------------- */
2091 static struct clk gclk0 = {
2092         .name           = "gclk0",
2093         .mode           = genclk_mode,
2094         .get_rate       = genclk_get_rate,
2095         .set_rate       = genclk_set_rate,
2096         .set_parent     = genclk_set_parent,
2097         .index          = 0,
2098 };
2099 static struct clk gclk1 = {
2100         .name           = "gclk1",
2101         .mode           = genclk_mode,
2102         .get_rate       = genclk_get_rate,
2103         .set_rate       = genclk_set_rate,
2104         .set_parent     = genclk_set_parent,
2105         .index          = 1,
2106 };
2107 static struct clk gclk2 = {
2108         .name           = "gclk2",
2109         .mode           = genclk_mode,
2110         .get_rate       = genclk_get_rate,
2111         .set_rate       = genclk_set_rate,
2112         .set_parent     = genclk_set_parent,
2113         .index          = 2,
2114 };
2115 static struct clk gclk3 = {
2116         .name           = "gclk3",
2117         .mode           = genclk_mode,
2118         .get_rate       = genclk_get_rate,
2119         .set_rate       = genclk_set_rate,
2120         .set_parent     = genclk_set_parent,
2121         .index          = 3,
2122 };
2123 static struct clk gclk4 = {
2124         .name           = "gclk4",
2125         .mode           = genclk_mode,
2126         .get_rate       = genclk_get_rate,
2127         .set_rate       = genclk_set_rate,
2128         .set_parent     = genclk_set_parent,
2129         .index          = 4,
2130 };
2131
2132 static __initdata struct clk *init_clocks[] = {
2133         &osc32k,
2134         &osc0,
2135         &osc1,
2136         &pll0,
2137         &pll1,
2138         &cpu_clk,
2139         &hsb_clk,
2140         &pba_clk,
2141         &pbb_clk,
2142         &at32_pm_pclk,
2143         &at32_intc0_pclk,
2144         &at32_hmatrix_clk,
2145         &ebi_clk,
2146         &hramc_clk,
2147         &sdramc_clk,
2148         &smc0_pclk,
2149         &smc0_mck,
2150         &pdc_hclk,
2151         &pdc_pclk,
2152         &dw_dmac0_hclk,
2153         &pico_clk,
2154         &pio0_mck,
2155         &pio1_mck,
2156         &pio2_mck,
2157         &pio3_mck,
2158         &pio4_mck,
2159         &at32_tcb0_t0_clk,
2160         &at32_tcb1_t0_clk,
2161         &atmel_psif0_pclk,
2162         &atmel_psif1_pclk,
2163         &atmel_usart0_usart,
2164         &atmel_usart1_usart,
2165         &atmel_usart2_usart,
2166         &atmel_usart3_usart,
2167         &atmel_pwm0_mck,
2168 #if defined(CONFIG_CPU_AT32AP7000)
2169         &macb0_hclk,
2170         &macb0_pclk,
2171         &macb1_hclk,
2172         &macb1_pclk,
2173 #endif
2174         &atmel_spi0_spi_clk,
2175         &atmel_spi1_spi_clk,
2176         &atmel_twi0_pclk,
2177         &atmel_mci0_pclk,
2178 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2179         &atmel_lcdfb0_hck1,
2180         &atmel_lcdfb0_pixclk,
2181 #endif
2182         &ssc0_pclk,
2183         &ssc1_pclk,
2184         &ssc2_pclk,
2185         &usba0_hclk,
2186         &usba0_pclk,
2187         &atmel_ac97c0_pclk,
2188         &abdac0_pclk,
2189         &abdac0_sample_clk,
2190         &gclk0,
2191         &gclk1,
2192         &gclk2,
2193         &gclk3,
2194         &gclk4,
2195 };
2196
2197 void __init setup_platform(void)
2198 {
2199         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2200         int i;
2201
2202         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2203                 main_clock = &pll0;
2204                 cpu_clk.parent = &pll0;
2205         } else {
2206                 main_clock = &osc0;
2207                 cpu_clk.parent = &osc0;
2208         }
2209
2210         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2211                 pll0.parent = &osc1;
2212         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2213                 pll1.parent = &osc1;
2214
2215         genclk_init_parent(&gclk0);
2216         genclk_init_parent(&gclk1);
2217         genclk_init_parent(&gclk2);
2218         genclk_init_parent(&gclk3);
2219         genclk_init_parent(&gclk4);
2220 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2221         genclk_init_parent(&atmel_lcdfb0_pixclk);
2222 #endif
2223         genclk_init_parent(&abdac0_sample_clk);
2224
2225         /*
2226          * Build initial dynamic clock list by registering all clocks
2227          * from the array.
2228          * At the same time, turn on all clocks that have at least one
2229          * user already, and turn off everything else. We only do this
2230          * for module clocks, and even though it isn't particularly
2231          * pretty to  check the address of the mode function, it should
2232          * do the trick...
2233          */
2234         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2235                 struct clk *clk = init_clocks[i];
2236
2237                 /* first, register clock */
2238                 at32_clk_register(clk);
2239
2240                 if (clk->users == 0)
2241                         continue;
2242
2243                 if (clk->mode == &cpu_clk_mode)
2244                         cpu_mask |= 1 << clk->index;
2245                 else if (clk->mode == &hsb_clk_mode)
2246                         hsb_mask |= 1 << clk->index;
2247                 else if (clk->mode == &pba_clk_mode)
2248                         pba_mask |= 1 << clk->index;
2249                 else if (clk->mode == &pbb_clk_mode)
2250                         pbb_mask |= 1 << clk->index;
2251         }
2252
2253         pm_writel(CPU_MASK, cpu_mask);
2254         pm_writel(HSB_MASK, hsb_mask);
2255         pm_writel(PBA_MASK, pba_mask);
2256         pm_writel(PBB_MASK, pbb_mask);
2257
2258         /* Initialize the port muxes */
2259         at32_init_pio(&pio0_device);
2260         at32_init_pio(&pio1_device);
2261         at32_init_pio(&pio2_device);
2262         at32_init_pio(&pio3_device);
2263         at32_init_pio(&pio4_device);
2264 }
2265
2266 struct gen_pool *sram_pool;
2267
2268 static int __init sram_init(void)
2269 {
2270         struct gen_pool *pool;
2271
2272         /* 1KiB granularity */
2273         pool = gen_pool_create(10, -1);
2274         if (!pool)
2275                 goto fail;
2276
2277         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2278                 goto err_pool_add;
2279
2280         sram_pool = pool;
2281         return 0;
2282
2283 err_pool_add:
2284         gen_pool_destroy(pool);
2285 fail:
2286         pr_err("Failed to create SRAM pool\n");
2287         return -ENOMEM;
2288 }
2289 core_initcall(sram_init);