2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <asm/hardware.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * omap24xx specific GPIO registers
89 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP24XX_GPIO_REVISION 0x0000
94 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
95 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
96 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
98 #define OMAP24XX_GPIO_CTRL 0x0030
99 #define OMAP24XX_GPIO_OE 0x0034
100 #define OMAP24XX_GPIO_DATAIN 0x0038
101 #define OMAP24XX_GPIO_DATAOUT 0x003c
102 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
103 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
104 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
105 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
106 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
107 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
108 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
109 #define OMAP24XX_GPIO_SETWKUENA 0x0084
110 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
111 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
116 u16 virtual_irq_start;
124 #define METHOD_MPUIO 0
125 #define METHOD_GPIO_1510 1
126 #define METHOD_GPIO_1610 2
127 #define METHOD_GPIO_730 3
128 #define METHOD_GPIO_24XX 4
130 #ifdef CONFIG_ARCH_OMAP16XX
131 static struct gpio_bank gpio_bank_1610[5] = {
132 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
133 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
134 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
135 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
136 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
140 #ifdef CONFIG_ARCH_OMAP15XX
141 static struct gpio_bank gpio_bank_1510[2] = {
142 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
143 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
147 #ifdef CONFIG_ARCH_OMAP730
148 static struct gpio_bank gpio_bank_730[7] = {
149 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
150 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
151 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
152 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
153 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
154 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
155 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
159 #ifdef CONFIG_ARCH_OMAP24XX
160 static struct gpio_bank gpio_bank_24xx[4] = {
161 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
162 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
163 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
164 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
168 static struct gpio_bank *gpio_bank;
169 static int gpio_bank_count;
171 static inline struct gpio_bank *get_gpio_bank(int gpio)
173 #ifdef CONFIG_ARCH_OMAP15XX
174 if (cpu_is_omap15xx()) {
175 if (OMAP_GPIO_IS_MPUIO(gpio))
176 return &gpio_bank[0];
177 return &gpio_bank[1];
180 #if defined(CONFIG_ARCH_OMAP16XX)
181 if (cpu_is_omap16xx()) {
182 if (OMAP_GPIO_IS_MPUIO(gpio))
183 return &gpio_bank[0];
184 return &gpio_bank[1 + (gpio >> 4)];
187 #ifdef CONFIG_ARCH_OMAP730
188 if (cpu_is_omap730()) {
189 if (OMAP_GPIO_IS_MPUIO(gpio))
190 return &gpio_bank[0];
191 return &gpio_bank[1 + (gpio >> 5)];
194 #ifdef CONFIG_ARCH_OMAP24XX
195 if (cpu_is_omap24xx())
196 return &gpio_bank[gpio >> 5];
200 static inline int get_gpio_index(int gpio)
202 #ifdef CONFIG_ARCH_OMAP730
203 if (cpu_is_omap730())
206 #ifdef CONFIG_ARCH_OMAP24XX
207 if (cpu_is_omap24xx())
213 static inline int gpio_valid(int gpio)
217 #ifndef CONFIG_ARCH_OMAP24XX
218 if (OMAP_GPIO_IS_MPUIO(gpio)) {
219 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
224 #ifdef CONFIG_ARCH_OMAP15XX
225 if (cpu_is_omap15xx() && gpio < 16)
228 #if defined(CONFIG_ARCH_OMAP16XX)
229 if ((cpu_is_omap16xx()) && gpio < 64)
232 #ifdef CONFIG_ARCH_OMAP730
233 if (cpu_is_omap730() && gpio < 192)
236 #ifdef CONFIG_ARCH_OMAP24XX
237 if (cpu_is_omap24xx() && gpio < 128)
243 static int check_gpio(int gpio)
245 if (unlikely(gpio_valid(gpio)) < 0) {
246 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
253 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
255 void __iomem *reg = bank->base;
258 switch (bank->method) {
260 reg += OMAP_MPUIO_IO_CNTL;
262 case METHOD_GPIO_1510:
263 reg += OMAP1510_GPIO_DIR_CONTROL;
265 case METHOD_GPIO_1610:
266 reg += OMAP1610_GPIO_DIRECTION;
268 case METHOD_GPIO_730:
269 reg += OMAP730_GPIO_DIR_CONTROL;
271 case METHOD_GPIO_24XX:
272 reg += OMAP24XX_GPIO_OE;
275 l = __raw_readl(reg);
280 __raw_writel(l, reg);
283 void omap_set_gpio_direction(int gpio, int is_input)
285 struct gpio_bank *bank;
287 if (check_gpio(gpio) < 0)
289 bank = get_gpio_bank(gpio);
290 spin_lock(&bank->lock);
291 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
292 spin_unlock(&bank->lock);
295 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
297 void __iomem *reg = bank->base;
300 switch (bank->method) {
302 reg += OMAP_MPUIO_OUTPUT;
303 l = __raw_readl(reg);
309 case METHOD_GPIO_1510:
310 reg += OMAP1510_GPIO_DATA_OUTPUT;
311 l = __raw_readl(reg);
317 case METHOD_GPIO_1610:
319 reg += OMAP1610_GPIO_SET_DATAOUT;
321 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
324 case METHOD_GPIO_730:
325 reg += OMAP730_GPIO_DATA_OUTPUT;
326 l = __raw_readl(reg);
332 case METHOD_GPIO_24XX:
334 reg += OMAP24XX_GPIO_SETDATAOUT;
336 reg += OMAP24XX_GPIO_CLEARDATAOUT;
343 __raw_writel(l, reg);
346 void omap_set_gpio_dataout(int gpio, int enable)
348 struct gpio_bank *bank;
350 if (check_gpio(gpio) < 0)
352 bank = get_gpio_bank(gpio);
353 spin_lock(&bank->lock);
354 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
355 spin_unlock(&bank->lock);
358 int omap_get_gpio_datain(int gpio)
360 struct gpio_bank *bank;
363 if (check_gpio(gpio) < 0)
365 bank = get_gpio_bank(gpio);
367 switch (bank->method) {
369 reg += OMAP_MPUIO_INPUT_LATCH;
371 case METHOD_GPIO_1510:
372 reg += OMAP1510_GPIO_DATA_INPUT;
374 case METHOD_GPIO_1610:
375 reg += OMAP1610_GPIO_DATAIN;
377 case METHOD_GPIO_730:
378 reg += OMAP730_GPIO_DATA_INPUT;
380 case METHOD_GPIO_24XX:
381 reg += OMAP24XX_GPIO_DATAIN;
387 return (__raw_readl(reg)
388 & (1 << get_gpio_index(gpio))) != 0;
391 #define MOD_REG_BIT(reg, bit_mask, set) \
393 int l = __raw_readl(base + reg); \
394 if (set) l |= bit_mask; \
395 else l &= ~bit_mask; \
396 __raw_writel(l, base + reg); \
399 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
401 u32 gpio_bit = 1 << gpio;
403 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
404 trigger & __IRQT_LOWLVL);
405 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
406 trigger & __IRQT_HIGHLVL);
407 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
408 trigger & __IRQT_RISEDGE);
409 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
410 trigger & __IRQT_FALEDGE);
411 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
412 * triggering requested. */
415 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
417 void __iomem *reg = bank->base;
420 switch (bank->method) {
422 reg += OMAP_MPUIO_GPIO_INT_EDGE;
423 l = __raw_readl(reg);
424 if (trigger & __IRQT_RISEDGE)
426 else if (trigger & __IRQT_FALEDGE)
431 case METHOD_GPIO_1510:
432 reg += OMAP1510_GPIO_INT_CONTROL;
433 l = __raw_readl(reg);
434 if (trigger & __IRQT_RISEDGE)
436 else if (trigger & __IRQT_FALEDGE)
441 case METHOD_GPIO_1610:
443 reg += OMAP1610_GPIO_EDGE_CTRL2;
445 reg += OMAP1610_GPIO_EDGE_CTRL1;
447 /* We allow only edge triggering, i.e. two lowest bits */
448 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
450 l = __raw_readl(reg);
451 l &= ~(3 << (gpio << 1));
452 if (trigger & __IRQT_RISEDGE)
453 l |= 2 << (gpio << 1);
454 if (trigger & __IRQT_FALEDGE)
455 l |= 1 << (gpio << 1);
457 case METHOD_GPIO_730:
458 reg += OMAP730_GPIO_INT_CONTROL;
459 l = __raw_readl(reg);
460 if (trigger & __IRQT_RISEDGE)
462 else if (trigger & __IRQT_FALEDGE)
467 case METHOD_GPIO_24XX:
468 set_24xx_gpio_triggering(reg, gpio, trigger);
474 __raw_writel(l, reg);
480 static int gpio_irq_type(unsigned irq, unsigned type)
482 struct gpio_bank *bank;
486 if (irq > IH_MPUIO_BASE)
487 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
489 gpio = irq - IH_GPIO_BASE;
491 if (check_gpio(gpio) < 0)
494 if (type & IRQT_PROBE)
496 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
499 bank = get_gpio_bank(gpio);
500 spin_lock(&bank->lock);
501 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
502 spin_unlock(&bank->lock);
506 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
508 void __iomem *reg = bank->base;
510 switch (bank->method) {
512 /* MPUIO irqstatus is reset by reading the status register,
513 * so do nothing here */
515 case METHOD_GPIO_1510:
516 reg += OMAP1510_GPIO_INT_STATUS;
518 case METHOD_GPIO_1610:
519 reg += OMAP1610_GPIO_IRQSTATUS1;
521 case METHOD_GPIO_730:
522 reg += OMAP730_GPIO_INT_STATUS;
524 case METHOD_GPIO_24XX:
525 reg += OMAP24XX_GPIO_IRQSTATUS1;
531 __raw_writel(gpio_mask, reg);
534 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
536 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
539 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
541 void __iomem *reg = bank->base;
546 switch (bank->method) {
548 reg += OMAP_MPUIO_GPIO_MASKIT;
552 case METHOD_GPIO_1510:
553 reg += OMAP1510_GPIO_INT_MASK;
557 case METHOD_GPIO_1610:
558 reg += OMAP1610_GPIO_IRQENABLE1;
561 case METHOD_GPIO_730:
562 reg += OMAP730_GPIO_INT_MASK;
566 case METHOD_GPIO_24XX:
567 reg += OMAP24XX_GPIO_IRQENABLE1;
575 l = __raw_readl(reg);
582 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
584 void __iomem *reg = bank->base;
587 switch (bank->method) {
589 reg += OMAP_MPUIO_GPIO_MASKIT;
590 l = __raw_readl(reg);
596 case METHOD_GPIO_1510:
597 reg += OMAP1510_GPIO_INT_MASK;
598 l = __raw_readl(reg);
604 case METHOD_GPIO_1610:
606 reg += OMAP1610_GPIO_SET_IRQENABLE1;
608 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
611 case METHOD_GPIO_730:
612 reg += OMAP730_GPIO_INT_MASK;
613 l = __raw_readl(reg);
619 case METHOD_GPIO_24XX:
621 reg += OMAP24XX_GPIO_SETIRQENABLE1;
623 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
630 __raw_writel(l, reg);
633 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
635 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
639 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
640 * 1510 does not seem to have a wake-up register. If JTAG is connected
641 * to the target, system will wake up always on GPIO events. While
642 * system is running all registered GPIO interrupts need to have wake-up
643 * enabled. When system is suspended, only selected GPIO interrupts need
644 * to have wake-up enabled.
646 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
648 switch (bank->method) {
649 case METHOD_GPIO_1610:
650 case METHOD_GPIO_24XX:
651 spin_lock(&bank->lock);
653 bank->suspend_wakeup |= (1 << gpio);
655 bank->suspend_wakeup &= ~(1 << gpio);
656 spin_unlock(&bank->lock);
659 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
665 static void _reset_gpio(struct gpio_bank *bank, int gpio)
667 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
668 _set_gpio_irqenable(bank, gpio, 0);
669 _clear_gpio_irqstatus(bank, gpio);
670 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
673 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
674 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
676 unsigned int gpio = irq - IH_GPIO_BASE;
677 struct gpio_bank *bank;
680 if (check_gpio(gpio) < 0)
682 bank = get_gpio_bank(gpio);
683 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
688 int omap_request_gpio(int gpio)
690 struct gpio_bank *bank;
692 if (check_gpio(gpio) < 0)
695 bank = get_gpio_bank(gpio);
696 spin_lock(&bank->lock);
697 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
698 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
700 spin_unlock(&bank->lock);
703 bank->reserved_map |= (1 << get_gpio_index(gpio));
705 /* Set trigger to none. You need to enable the desired trigger with
706 * request_irq() or set_irq_type().
708 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
710 #ifdef CONFIG_ARCH_OMAP15XX
711 if (bank->method == METHOD_GPIO_1510) {
714 /* Claim the pin for MPU */
715 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
716 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
719 #ifdef CONFIG_ARCH_OMAP16XX
720 if (bank->method == METHOD_GPIO_1610) {
721 /* Enable wake-up during idle for dynamic tick */
722 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
723 __raw_writel(1 << get_gpio_index(gpio), reg);
726 #ifdef CONFIG_ARCH_OMAP24XX
727 if (bank->method == METHOD_GPIO_24XX) {
728 /* Enable wake-up during idle for dynamic tick */
729 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
730 __raw_writel(1 << get_gpio_index(gpio), reg);
733 spin_unlock(&bank->lock);
738 void omap_free_gpio(int gpio)
740 struct gpio_bank *bank;
742 if (check_gpio(gpio) < 0)
744 bank = get_gpio_bank(gpio);
745 spin_lock(&bank->lock);
746 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
747 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
749 spin_unlock(&bank->lock);
752 #ifdef CONFIG_ARCH_OMAP16XX
753 if (bank->method == METHOD_GPIO_1610) {
754 /* Disable wake-up during idle for dynamic tick */
755 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
756 __raw_writel(1 << get_gpio_index(gpio), reg);
759 #ifdef CONFIG_ARCH_OMAP24XX
760 if (bank->method == METHOD_GPIO_24XX) {
761 /* Disable wake-up during idle for dynamic tick */
762 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
763 __raw_writel(1 << get_gpio_index(gpio), reg);
766 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
767 _reset_gpio(bank, gpio);
768 spin_unlock(&bank->lock);
772 * We need to unmask the GPIO bank interrupt as soon as possible to
773 * avoid missing GPIO interrupts for other lines in the bank.
774 * Then we need to mask-read-clear-unmask the triggered GPIO lines
775 * in the bank to avoid missing nested interrupts for a GPIO line.
776 * If we wait to unmask individual GPIO lines in the bank after the
777 * line's interrupt handler has been run, we may miss some nested
780 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
781 struct pt_regs *regs)
783 void __iomem *isr_reg = NULL;
785 unsigned int gpio_irq;
786 struct gpio_bank *bank;
790 desc->chip->ack(irq);
792 bank = get_irq_data(irq);
793 if (bank->method == METHOD_MPUIO)
794 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
795 #ifdef CONFIG_ARCH_OMAP15XX
796 if (bank->method == METHOD_GPIO_1510)
797 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
799 #if defined(CONFIG_ARCH_OMAP16XX)
800 if (bank->method == METHOD_GPIO_1610)
801 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
803 #ifdef CONFIG_ARCH_OMAP730
804 if (bank->method == METHOD_GPIO_730)
805 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
807 #ifdef CONFIG_ARCH_OMAP24XX
808 if (bank->method == METHOD_GPIO_24XX)
809 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
812 u32 isr_saved, level_mask = 0;
815 enabled = _get_gpio_irqbank_mask(bank);
816 isr_saved = isr = __raw_readl(isr_reg) & enabled;
818 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
821 if (cpu_is_omap24xx()) {
823 __raw_readl(bank->base +
824 OMAP24XX_GPIO_LEVELDETECT0) |
825 __raw_readl(bank->base +
826 OMAP24XX_GPIO_LEVELDETECT1);
827 level_mask &= enabled;
830 /* clear edge sensitive interrupts before handler(s) are
831 called so that we don't miss any interrupt occurred while
833 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
834 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
835 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
837 /* if there is only edge sensitive GPIO pin interrupts
838 configured, we could unmask GPIO bank interrupt immediately */
839 if (!level_mask && !unmasked) {
841 desc->chip->unmask(irq);
849 gpio_irq = bank->virtual_irq_start;
850 for (; isr != 0; isr >>= 1, gpio_irq++) {
855 d = irq_desc + gpio_irq;
856 /* Don't run the handler if it's already running
857 * or was disabled lazely.
859 if (unlikely((d->depth ||
860 (d->status & IRQ_INPROGRESS)))) {
862 (gpio_irq - bank->virtual_irq_start);
863 /* The unmasking will be done by
864 * enable_irq in case it is disabled or
865 * after returning from the handler if
866 * it's already running.
868 _enable_gpio_irqbank(bank, irq_mask, 0);
870 /* Level triggered interrupts
871 * won't ever be reentered
873 BUG_ON(level_mask & irq_mask);
874 d->status |= IRQ_PENDING;
879 desc_handle_irq(gpio_irq, d, regs);
881 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
883 (gpio_irq - bank->virtual_irq_start);
884 d->status &= ~IRQ_PENDING;
885 _enable_gpio_irqbank(bank, irq_mask, 1);
886 retrigger |= irq_mask;
890 if (cpu_is_omap24xx()) {
891 /* clear level sensitive interrupts after handler(s) */
892 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
893 _clear_gpio_irqbank(bank, isr_saved & level_mask);
894 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
898 /* if bank has any level sensitive GPIO pin interrupt
899 configured, we must unmask the bank interrupt only after
900 handler(s) are executed in order to avoid spurious bank
903 desc->chip->unmask(irq);
907 static void gpio_irq_shutdown(unsigned int irq)
909 unsigned int gpio = irq - IH_GPIO_BASE;
910 struct gpio_bank *bank = get_gpio_bank(gpio);
912 _reset_gpio(bank, gpio);
915 static void gpio_ack_irq(unsigned int irq)
917 unsigned int gpio = irq - IH_GPIO_BASE;
918 struct gpio_bank *bank = get_gpio_bank(gpio);
920 _clear_gpio_irqstatus(bank, gpio);
923 static void gpio_mask_irq(unsigned int irq)
925 unsigned int gpio = irq - IH_GPIO_BASE;
926 struct gpio_bank *bank = get_gpio_bank(gpio);
928 _set_gpio_irqenable(bank, gpio, 0);
931 static void gpio_unmask_irq(unsigned int irq)
933 unsigned int gpio = irq - IH_GPIO_BASE;
934 unsigned int gpio_idx = get_gpio_index(gpio);
935 struct gpio_bank *bank = get_gpio_bank(gpio);
937 _set_gpio_irqenable(bank, gpio_idx, 1);
940 static void mpuio_ack_irq(unsigned int irq)
942 /* The ISR is reset automatically, so do nothing here. */
945 static void mpuio_mask_irq(unsigned int irq)
947 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
948 struct gpio_bank *bank = get_gpio_bank(gpio);
950 _set_gpio_irqenable(bank, gpio, 0);
953 static void mpuio_unmask_irq(unsigned int irq)
955 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
956 struct gpio_bank *bank = get_gpio_bank(gpio);
958 _set_gpio_irqenable(bank, gpio, 1);
961 static struct irq_chip gpio_irq_chip = {
963 .shutdown = gpio_irq_shutdown,
965 .mask = gpio_mask_irq,
966 .unmask = gpio_unmask_irq,
967 .set_type = gpio_irq_type,
968 .set_wake = gpio_wake_enable,
971 static struct irq_chip mpuio_irq_chip = {
973 .ack = mpuio_ack_irq,
974 .mask = mpuio_mask_irq,
975 .unmask = mpuio_unmask_irq
978 static int initialized;
979 static struct clk * gpio_ick;
980 static struct clk * gpio_fck;
982 static int __init _omap_gpio_init(void)
985 struct gpio_bank *bank;
989 if (cpu_is_omap15xx()) {
990 gpio_ick = clk_get(NULL, "arm_gpio_ck");
991 if (IS_ERR(gpio_ick))
992 printk("Could not get arm_gpio_ck\n");
994 clk_enable(gpio_ick);
996 if (cpu_is_omap24xx()) {
997 gpio_ick = clk_get(NULL, "gpios_ick");
998 if (IS_ERR(gpio_ick))
999 printk("Could not get gpios_ick\n");
1001 clk_enable(gpio_ick);
1002 gpio_fck = clk_get(NULL, "gpios_fck");
1003 if (IS_ERR(gpio_ick))
1004 printk("Could not get gpios_fck\n");
1006 clk_enable(gpio_fck);
1009 #ifdef CONFIG_ARCH_OMAP15XX
1010 if (cpu_is_omap15xx()) {
1011 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1012 gpio_bank_count = 2;
1013 gpio_bank = gpio_bank_1510;
1016 #if defined(CONFIG_ARCH_OMAP16XX)
1017 if (cpu_is_omap16xx()) {
1020 gpio_bank_count = 5;
1021 gpio_bank = gpio_bank_1610;
1022 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1023 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1024 (rev >> 4) & 0x0f, rev & 0x0f);
1027 #ifdef CONFIG_ARCH_OMAP730
1028 if (cpu_is_omap730()) {
1029 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1030 gpio_bank_count = 7;
1031 gpio_bank = gpio_bank_730;
1034 #ifdef CONFIG_ARCH_OMAP24XX
1035 if (cpu_is_omap24xx()) {
1038 gpio_bank_count = 4;
1039 gpio_bank = gpio_bank_24xx;
1040 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1041 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1042 (rev >> 4) & 0x0f, rev & 0x0f);
1045 for (i = 0; i < gpio_bank_count; i++) {
1046 int j, gpio_count = 16;
1048 bank = &gpio_bank[i];
1049 bank->reserved_map = 0;
1050 bank->base = IO_ADDRESS(bank->base);
1051 spin_lock_init(&bank->lock);
1052 if (bank->method == METHOD_MPUIO) {
1053 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1055 #ifdef CONFIG_ARCH_OMAP15XX
1056 if (bank->method == METHOD_GPIO_1510) {
1057 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1058 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1061 #if defined(CONFIG_ARCH_OMAP16XX)
1062 if (bank->method == METHOD_GPIO_1610) {
1063 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1064 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1065 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1068 #ifdef CONFIG_ARCH_OMAP730
1069 if (bank->method == METHOD_GPIO_730) {
1070 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1071 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1073 gpio_count = 32; /* 730 has 32-bit GPIOs */
1076 #ifdef CONFIG_ARCH_OMAP24XX
1077 if (bank->method == METHOD_GPIO_24XX) {
1078 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1079 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1084 for (j = bank->virtual_irq_start;
1085 j < bank->virtual_irq_start + gpio_count; j++) {
1086 if (bank->method == METHOD_MPUIO)
1087 set_irq_chip(j, &mpuio_irq_chip);
1089 set_irq_chip(j, &gpio_irq_chip);
1090 set_irq_handler(j, do_simple_IRQ);
1091 set_irq_flags(j, IRQF_VALID);
1093 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1094 set_irq_data(bank->irq, bank);
1097 /* Enable system clock for GPIO module.
1098 * The CAM_CLK_CTRL *is* really the right place. */
1099 if (cpu_is_omap16xx())
1100 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1105 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1106 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1110 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1113 for (i = 0; i < gpio_bank_count; i++) {
1114 struct gpio_bank *bank = &gpio_bank[i];
1115 void __iomem *wake_status;
1116 void __iomem *wake_clear;
1117 void __iomem *wake_set;
1119 switch (bank->method) {
1120 case METHOD_GPIO_1610:
1121 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1122 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1123 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1125 case METHOD_GPIO_24XX:
1126 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1127 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1128 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1134 spin_lock(&bank->lock);
1135 bank->saved_wakeup = __raw_readl(wake_status);
1136 __raw_writel(0xffffffff, wake_clear);
1137 __raw_writel(bank->suspend_wakeup, wake_set);
1138 spin_unlock(&bank->lock);
1144 static int omap_gpio_resume(struct sys_device *dev)
1148 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1151 for (i = 0; i < gpio_bank_count; i++) {
1152 struct gpio_bank *bank = &gpio_bank[i];
1153 void __iomem *wake_clear;
1154 void __iomem *wake_set;
1156 switch (bank->method) {
1157 case METHOD_GPIO_1610:
1158 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1159 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1161 case METHOD_GPIO_24XX:
1162 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1163 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1169 spin_lock(&bank->lock);
1170 __raw_writel(0xffffffff, wake_clear);
1171 __raw_writel(bank->saved_wakeup, wake_set);
1172 spin_unlock(&bank->lock);
1178 static struct sysdev_class omap_gpio_sysclass = {
1179 set_kset_name("gpio"),
1180 .suspend = omap_gpio_suspend,
1181 .resume = omap_gpio_resume,
1184 static struct sys_device omap_gpio_device = {
1186 .cls = &omap_gpio_sysclass,
1191 * This may get called early from board specific init
1192 * for boards that have interrupts routed via FPGA.
1194 int omap_gpio_init(void)
1197 return _omap_gpio_init();
1202 static int __init omap_gpio_sysinit(void)
1207 ret = _omap_gpio_init();
1209 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1210 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1212 ret = sysdev_class_register(&omap_gpio_sysclass);
1214 ret = sysdev_register(&omap_gpio_device);
1222 EXPORT_SYMBOL(omap_request_gpio);
1223 EXPORT_SYMBOL(omap_free_gpio);
1224 EXPORT_SYMBOL(omap_set_gpio_direction);
1225 EXPORT_SYMBOL(omap_set_gpio_dataout);
1226 EXPORT_SYMBOL(omap_get_gpio_datain);
1228 arch_initcall(omap_gpio_sysinit);