arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/device.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32
  33 #include "common.h"
  34
  35 static unsigned long xtal;
  36
  37 static struct clksrc_clk clk_mout_apll = {
  38         .clk    = {
  39                 .name           = "mout_apll",
  40         },
  41         .sources        = &clk_src_apll,
  42         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  43 };
  44
  45 static struct clksrc_clk clk_mout_epll = {
  46         .clk    = {
  47                 .name           = "mout_epll",
  48         },
  49         .sources        = &clk_src_epll,
  50         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  51 };
  52
  53 static struct clksrc_clk clk_mout_mpll = {
  54         .clk = {
  55                 .name           = "mout_mpll",
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74         },
  75         .sources        = &clkset_armclk,
  76         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  77         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  78 };
  79
  80 static struct clksrc_clk clk_hclk_msys = {
  81         .clk    = {
  82                 .name           = "hclk_msys",
  83                 .parent         = &clk_armclk.clk,
  84         },
  85         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  86 };
  87
  88 static struct clksrc_clk clk_pclk_msys = {
  89         .clk    = {
  90                 .name           = "pclk_msys",
  91                 .parent         = &clk_hclk_msys.clk,
  92         },
  93         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  94 };
  95
  96 static struct clksrc_clk clk_sclk_a2m = {
  97         .clk    = {
  98                 .name           = "sclk_a2m",
  99                 .parent         = &clk_mout_apll.clk,
 100         },
 101         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 102 };
 103
 104 static struct clk *clkset_hclk_sys_list[] = {
 105         [0] = &clk_mout_mpll.clk,
 106         [1] = &clk_sclk_a2m.clk,
 107 };
 108
 109 static struct clksrc_sources clkset_hclk_sys = {
 110         .sources        = clkset_hclk_sys_list,
 111         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 112 };
 113
 114 static struct clksrc_clk clk_hclk_dsys = {
 115         .clk    = {
 116                 .name   = "hclk_dsys",
 117         },
 118         .sources        = &clkset_hclk_sys,
 119         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 120         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 121 };
 122
 123 static struct clksrc_clk clk_pclk_dsys = {
 124         .clk    = {
 125                 .name   = "pclk_dsys",
 126                 .parent = &clk_hclk_dsys.clk,
 127         },
 128         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 129 };
 130
 131 static struct clksrc_clk clk_hclk_psys = {
 132         .clk    = {
 133                 .name   = "hclk_psys",
 134         },
 135         .sources        = &clkset_hclk_sys,
 136         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 137         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 138 };
 139
 140 static struct clksrc_clk clk_pclk_psys = {
 141         .clk    = {
 142                 .name   = "pclk_psys",
 143                 .parent = &clk_hclk_psys.clk,
 144         },
 145         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 146 };
 147
 148 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 149 {
 150         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 151 }
 152
 153 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 154 {
 155         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 156 }
 157
 158 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 159 {
 160         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 161 }
 162
 163 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 164 {
 165         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 166 }
 167
 168 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 169 {
 170         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 171 }
 172
 173 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 174 {
 175         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 176 }
 177
 178 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 179 {
 180         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 181 }
 182
 183 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 184 {
 185         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 186 }
 187
 188 static struct clk clk_sclk_hdmi27m = {
 189         .name           = "sclk_hdmi27m",
 190         .rate           = 27000000,
 191 };
 192
 193 static struct clk clk_sclk_hdmiphy = {
 194         .name           = "sclk_hdmiphy",
 195 };
 196
 197 static struct clk clk_sclk_usbphy0 = {
 198         .name           = "sclk_usbphy0",
 199 };
 200
 201 static struct clk clk_sclk_usbphy1 = {
 202         .name           = "sclk_usbphy1",
 203 };
 204
 205 static struct clk clk_pcmcdclk0 = {
 206         .name           = "pcmcdclk",
 207 };
 208
 209 static struct clk clk_pcmcdclk1 = {
 210         .name           = "pcmcdclk",
 211 };
 212
 213 static struct clk clk_pcmcdclk2 = {
 214         .name           = "pcmcdclk",
 215 };
 216
 217 static struct clk dummy_apb_pclk = {
 218         .name           = "apb_pclk",
 219         .id             = -1,
 220 };
 221
 222 static struct clk *clkset_vpllsrc_list[] = {
 223         [0] = &clk_fin_vpll,
 224         [1] = &clk_sclk_hdmi27m,
 225 };
 226
 227 static struct clksrc_sources clkset_vpllsrc = {
 228         .sources        = clkset_vpllsrc_list,
 229         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 230 };
 231
 232 static struct clksrc_clk clk_vpllsrc = {
 233         .clk    = {
 234                 .name           = "vpll_src",
 235                 .enable         = s5pv210_clk_mask0_ctrl,
 236                 .ctrlbit        = (1 << 7),
 237         },
 238         .sources        = &clkset_vpllsrc,
 239         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 240 };
 241
 242 static struct clk *clkset_sclk_vpll_list[] = {
 243         [0] = &clk_vpllsrc.clk,
 244         [1] = &clk_fout_vpll,
 245 };
 246
 247 static struct clksrc_sources clkset_sclk_vpll = {
 248         .sources        = clkset_sclk_vpll_list,
 249         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 250 };
 251
 252 static struct clksrc_clk clk_sclk_vpll = {
 253         .clk    = {
 254                 .name           = "sclk_vpll",
 255         },
 256         .sources        = &clkset_sclk_vpll,
 257         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 258 };
 259
 260 static struct clk *clkset_moutdmc0src_list[] = {
 261         [0] = &clk_sclk_a2m.clk,
 262         [1] = &clk_mout_mpll.clk,
 263         [2] = NULL,
 264         [3] = NULL,
 265 };
 266
 267 static struct clksrc_sources clkset_moutdmc0src = {
 268         .sources        = clkset_moutdmc0src_list,
 269         .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
 270 };
 271
 272 static struct clksrc_clk clk_mout_dmc0 = {
 273         .clk    = {
 274                 .name           = "mout_dmc0",
 275         },
 276         .sources        = &clkset_moutdmc0src,
 277         .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 278 };
 279
 280 static struct clksrc_clk clk_sclk_dmc0 = {
 281         .clk    = {
 282                 .name           = "sclk_dmc0",
 283                 .parent         = &clk_mout_dmc0.clk,
 284         },
 285         .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 286 };
 287
 288 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 289 {
 290         return clk_get_rate(clk->parent) / 2;
 291 }
 292
 293 static struct clk_ops clk_hclk_imem_ops = {
 294         .get_rate       = s5pv210_clk_imem_get_rate,
 295 };
 296
 297 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
 298 {
 299         return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 300 }
 301
 302 static struct clk_ops clk_fout_apll_ops = {
 303         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 304 };
 305
 306 static struct clk init_clocks_off[] = {
 307         {
 308                 .name           = "dma",
 309                 .devname        = "dma-pl330.0",
 310                 .parent         = &clk_hclk_psys.clk,
 311                 .enable         = s5pv210_clk_ip0_ctrl,
 312                 .ctrlbit        = (1 << 3),
 313         }, {
 314                 .name           = "dma",
 315                 .devname        = "dma-pl330.1",
 316                 .parent         = &clk_hclk_psys.clk,
 317                 .enable         = s5pv210_clk_ip0_ctrl,
 318                 .ctrlbit        = (1 << 4),
 319         }, {
 320                 .name           = "rot",
 321                 .parent         = &clk_hclk_dsys.clk,
 322                 .enable         = s5pv210_clk_ip0_ctrl,
 323                 .ctrlbit        = (1<<29),
 324         }, {
 325                 .name           = "fimc",
 326                 .devname        = "s5pv210-fimc.0",
 327                 .parent         = &clk_hclk_dsys.clk,
 328                 .enable         = s5pv210_clk_ip0_ctrl,
 329                 .ctrlbit        = (1 << 24),
 330         }, {
 331                 .name           = "fimc",
 332                 .devname        = "s5pv210-fimc.1",
 333                 .parent         = &clk_hclk_dsys.clk,
 334                 .enable         = s5pv210_clk_ip0_ctrl,
 335                 .ctrlbit        = (1 << 25),
 336         }, {
 337                 .name           = "fimc",
 338                 .devname        = "s5pv210-fimc.2",
 339                 .parent         = &clk_hclk_dsys.clk,
 340                 .enable         = s5pv210_clk_ip0_ctrl,
 341                 .ctrlbit        = (1 << 26),
 342         }, {
 343                 .name           = "mfc",
 344                 .devname        = "s5p-mfc",
 345                 .parent         = &clk_pclk_psys.clk,
 346                 .enable         = s5pv210_clk_ip0_ctrl,
 347                 .ctrlbit        = (1 << 16),
 348         }, {
 349                 .name           = "dac",
 350                 .devname        = "s5p-sdo",
 351                 .parent         = &clk_hclk_dsys.clk,
 352                 .enable         = s5pv210_clk_ip1_ctrl,
 353                 .ctrlbit        = (1 << 10),
 354         }, {
 355                 .name           = "mixer",
 356                 .devname        = "s5p-mixer",
 357                 .parent         = &clk_hclk_dsys.clk,
 358                 .enable         = s5pv210_clk_ip1_ctrl,
 359                 .ctrlbit        = (1 << 9),
 360         }, {
 361                 .name           = "vp",
 362                 .devname        = "s5p-mixer",
 363                 .parent         = &clk_hclk_dsys.clk,
 364                 .enable         = s5pv210_clk_ip1_ctrl,
 365                 .ctrlbit        = (1 << 8),
 366         }, {
 367                 .name           = "hdmi",
 368                 .devname        = "s5pv210-hdmi",
 369                 .parent         = &clk_hclk_dsys.clk,
 370                 .enable         = s5pv210_clk_ip1_ctrl,
 371                 .ctrlbit        = (1 << 11),
 372         }, {
 373                 .name           = "hdmiphy",
 374                 .devname        = "s5pv210-hdmi",
 375                 .enable         = exynos4_clk_hdmiphy_ctrl,
 376                 .ctrlbit        = (1 << 0),
 377         }, {
 378                 .name           = "dacphy",
 379                 .devname        = "s5p-sdo",
 380                 .enable         = exynos4_clk_dac_ctrl,
 381                 .ctrlbit        = (1 << 0),
 382         }, {
 383                 .name           = "otg",
 384                 .parent         = &clk_hclk_psys.clk,
 385                 .enable         = s5pv210_clk_ip1_ctrl,
 386                 .ctrlbit        = (1<<16),
 387         }, {
 388                 .name           = "usb-host",
 389                 .parent         = &clk_hclk_psys.clk,
 390                 .enable         = s5pv210_clk_ip1_ctrl,
 391                 .ctrlbit        = (1<<17),
 392         }, {
 393                 .name           = "lcd",
 394                 .parent         = &clk_hclk_dsys.clk,
 395                 .enable         = s5pv210_clk_ip1_ctrl,
 396                 .ctrlbit        = (1<<0),
 397         }, {
 398                 .name           = "cfcon",
 399                 .parent         = &clk_hclk_psys.clk,
 400                 .enable         = s5pv210_clk_ip1_ctrl,
 401                 .ctrlbit        = (1<<25),
 402         }, {
 403                 .name           = "hsmmc",
 404                 .devname        = "s3c-sdhci.0",
 405                 .parent         = &clk_hclk_psys.clk,
 406                 .enable         = s5pv210_clk_ip2_ctrl,
 407                 .ctrlbit        = (1<<16),
 408         }, {
 409                 .name           = "hsmmc",
 410                 .devname        = "s3c-sdhci.1",
 411                 .parent         = &clk_hclk_psys.clk,
 412                 .enable         = s5pv210_clk_ip2_ctrl,
 413                 .ctrlbit        = (1<<17),
 414         }, {
 415                 .name           = "hsmmc",
 416                 .devname        = "s3c-sdhci.2",
 417                 .parent         = &clk_hclk_psys.clk,
 418                 .enable         = s5pv210_clk_ip2_ctrl,
 419                 .ctrlbit        = (1<<18),
 420         }, {
 421                 .name           = "hsmmc",
 422                 .devname        = "s3c-sdhci.3",
 423                 .parent         = &clk_hclk_psys.clk,
 424                 .enable         = s5pv210_clk_ip2_ctrl,
 425                 .ctrlbit        = (1<<19),
 426         }, {
 427                 .name           = "systimer",
 428                 .parent         = &clk_pclk_psys.clk,
 429                 .enable         = s5pv210_clk_ip3_ctrl,
 430                 .ctrlbit        = (1<<16),
 431         }, {
 432                 .name           = "watchdog",
 433                 .parent         = &clk_pclk_psys.clk,
 434                 .enable         = s5pv210_clk_ip3_ctrl,
 435                 .ctrlbit        = (1<<22),
 436         }, {
 437                 .name           = "rtc",
 438                 .parent         = &clk_pclk_psys.clk,
 439                 .enable         = s5pv210_clk_ip3_ctrl,
 440                 .ctrlbit        = (1<<15),
 441         }, {
 442                 .name           = "i2c",
 443                 .devname        = "s3c2440-i2c.0",
 444                 .parent         = &clk_pclk_psys.clk,
 445                 .enable         = s5pv210_clk_ip3_ctrl,
 446                 .ctrlbit        = (1<<7),
 447         }, {
 448                 .name           = "i2c",
 449                 .devname        = "s3c2440-i2c.1",
 450                 .parent         = &clk_pclk_psys.clk,
 451                 .enable         = s5pv210_clk_ip3_ctrl,
 452                 .ctrlbit        = (1 << 10),
 453         }, {
 454                 .name           = "i2c",
 455                 .devname        = "s3c2440-i2c.2",
 456                 .parent         = &clk_pclk_psys.clk,
 457                 .enable         = s5pv210_clk_ip3_ctrl,
 458                 .ctrlbit        = (1<<9),
 459         }, {
 460                 .name           = "i2c",
 461                 .devname        = "s3c2440-hdmiphy-i2c",
 462                 .parent         = &clk_pclk_psys.clk,
 463                 .enable         = s5pv210_clk_ip3_ctrl,
 464                 .ctrlbit        = (1 << 11),
 465         }, {
 466                 .name           = "spi",
 467                 .devname        = "s3c64xx-spi.0",
 468                 .parent         = &clk_pclk_psys.clk,
 469                 .enable         = s5pv210_clk_ip3_ctrl,
 470                 .ctrlbit        = (1<<12),
 471         }, {
 472                 .name           = "spi",
 473                 .devname        = "s3c64xx-spi.1",
 474                 .parent         = &clk_pclk_psys.clk,
 475                 .enable         = s5pv210_clk_ip3_ctrl,
 476                 .ctrlbit        = (1<<13),
 477         }, {
 478                 .name           = "spi",
 479                 .devname        = "s3c64xx-spi.2",
 480                 .parent         = &clk_pclk_psys.clk,
 481                 .enable         = s5pv210_clk_ip3_ctrl,
 482                 .ctrlbit        = (1<<14),
 483         }, {
 484                 .name           = "timers",
 485                 .parent         = &clk_pclk_psys.clk,
 486                 .enable         = s5pv210_clk_ip3_ctrl,
 487                 .ctrlbit        = (1<<23),
 488         }, {
 489                 .name           = "adc",
 490                 .parent         = &clk_pclk_psys.clk,
 491                 .enable         = s5pv210_clk_ip3_ctrl,
 492                 .ctrlbit        = (1<<24),
 493         }, {
 494                 .name           = "keypad",
 495                 .parent         = &clk_pclk_psys.clk,
 496                 .enable         = s5pv210_clk_ip3_ctrl,
 497                 .ctrlbit        = (1<<21),
 498         }, {
 499                 .name           = "iis",
 500                 .devname        = "samsung-i2s.0",
 501                 .parent         = &clk_p,
 502                 .enable         = s5pv210_clk_ip3_ctrl,
 503                 .ctrlbit        = (1<<4),
 504         }, {
 505                 .name           = "iis",
 506                 .devname        = "samsung-i2s.1",
 507                 .parent         = &clk_p,
 508                 .enable         = s5pv210_clk_ip3_ctrl,
 509                 .ctrlbit        = (1 << 5),
 510         }, {
 511                 .name           = "iis",
 512                 .devname        = "samsung-i2s.2",
 513                 .parent         = &clk_p,
 514                 .enable         = s5pv210_clk_ip3_ctrl,
 515                 .ctrlbit        = (1 << 6),
 516         }, {
 517                 .name           = "spdif",
 518                 .parent         = &clk_p,
 519                 .enable         = s5pv210_clk_ip3_ctrl,
 520                 .ctrlbit        = (1 << 0),
 521         },
 522 };
 523
 524 static struct clk init_clocks[] = {
 525         {
 526                 .name           = "hclk_imem",
 527                 .parent         = &clk_hclk_msys.clk,
 528                 .ctrlbit        = (1 << 5),
 529                 .enable         = s5pv210_clk_ip0_ctrl,
 530                 .ops            = &clk_hclk_imem_ops,
 531         }, {
 532                 .name           = "uart",
 533                 .devname        = "s5pv210-uart.0",
 534                 .parent         = &clk_pclk_psys.clk,
 535                 .enable         = s5pv210_clk_ip3_ctrl,
 536                 .ctrlbit        = (1 << 17),
 537         }, {
 538                 .name           = "uart",
 539                 .devname        = "s5pv210-uart.1",
 540                 .parent         = &clk_pclk_psys.clk,
 541                 .enable         = s5pv210_clk_ip3_ctrl,
 542                 .ctrlbit        = (1 << 18),
 543         }, {
 544                 .name           = "uart",
 545                 .devname        = "s5pv210-uart.2",
 546                 .parent         = &clk_pclk_psys.clk,
 547                 .enable         = s5pv210_clk_ip3_ctrl,
 548                 .ctrlbit        = (1 << 19),
 549         }, {
 550                 .name           = "uart",
 551                 .devname        = "s5pv210-uart.3",
 552                 .parent         = &clk_pclk_psys.clk,
 553                 .enable         = s5pv210_clk_ip3_ctrl,
 554                 .ctrlbit        = (1 << 20),
 555         }, {
 556                 .name           = "sromc",
 557                 .parent         = &clk_hclk_psys.clk,
 558                 .enable         = s5pv210_clk_ip1_ctrl,
 559                 .ctrlbit        = (1 << 26),
 560         },
 561 };
 562
 563 static struct clk *clkset_uart_list[] = {
 564         [6] = &clk_mout_mpll.clk,
 565         [7] = &clk_mout_epll.clk,
 566 };
 567
 568 static struct clksrc_sources clkset_uart = {
 569         .sources        = clkset_uart_list,
 570         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 571 };
 572
 573 static struct clk *clkset_group1_list[] = {
 574         [0] = &clk_sclk_a2m.clk,
 575         [1] = &clk_mout_mpll.clk,
 576         [2] = &clk_mout_epll.clk,
 577         [3] = &clk_sclk_vpll.clk,
 578 };
 579
 580 static struct clksrc_sources clkset_group1 = {
 581         .sources        = clkset_group1_list,
 582         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 583 };
 584
 585 static struct clk *clkset_sclk_onenand_list[] = {
 586         [0] = &clk_hclk_psys.clk,
 587         [1] = &clk_hclk_dsys.clk,
 588 };
 589
 590 static struct clksrc_sources clkset_sclk_onenand = {
 591         .sources        = clkset_sclk_onenand_list,
 592         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 593 };
 594
 595 static struct clk *clkset_sclk_dac_list[] = {
 596         [0] = &clk_sclk_vpll.clk,
 597         [1] = &clk_sclk_hdmiphy,
 598 };
 599
 600 static struct clksrc_sources clkset_sclk_dac = {
 601         .sources        = clkset_sclk_dac_list,
 602         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 603 };
 604
 605 static struct clksrc_clk clk_sclk_dac = {
 606         .clk            = {
 607                 .name           = "sclk_dac",
 608                 .enable         = s5pv210_clk_mask0_ctrl,
 609                 .ctrlbit        = (1 << 2),
 610         },
 611         .sources        = &clkset_sclk_dac,
 612         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 613 };
 614
 615 static struct clksrc_clk clk_sclk_pixel = {
 616         .clk            = {
 617                 .name           = "sclk_pixel",
 618                 .parent         = &clk_sclk_vpll.clk,
 619         },
 620         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 621 };
 622
 623 static struct clk *clkset_sclk_hdmi_list[] = {
 624         [0] = &clk_sclk_pixel.clk,
 625         [1] = &clk_sclk_hdmiphy,
 626 };
 627
 628 static struct clksrc_sources clkset_sclk_hdmi = {
 629         .sources        = clkset_sclk_hdmi_list,
 630         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 631 };
 632
 633 static struct clksrc_clk clk_sclk_hdmi = {
 634         .clk            = {
 635                 .name           = "sclk_hdmi",
 636                 .enable         = s5pv210_clk_mask0_ctrl,
 637                 .ctrlbit        = (1 << 0),
 638         },
 639         .sources        = &clkset_sclk_hdmi,
 640         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 641 };
 642
 643 static struct clk *clkset_sclk_mixer_list[] = {
 644         [0] = &clk_sclk_dac.clk,
 645         [1] = &clk_sclk_hdmi.clk,
 646 };
 647
 648 static struct clksrc_sources clkset_sclk_mixer = {
 649         .sources        = clkset_sclk_mixer_list,
 650         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 651 };
 652
 653 static struct clksrc_clk clk_sclk_mixer = {
 654         .clk            = {
 655                 .name           = "sclk_mixer",
 656                 .enable         = s5pv210_clk_mask0_ctrl,
 657                 .ctrlbit        = (1 << 1),
 658         },
 659         .sources = &clkset_sclk_mixer,
 660         .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 661 };
 662
 663 static struct clksrc_clk *sclk_tv[] = {
 664         &clk_sclk_dac,
 665         &clk_sclk_pixel,
 666         &clk_sclk_hdmi,
 667         &clk_sclk_mixer,
 668 };
 669
 670 static struct clk *clkset_sclk_audio0_list[] = {
 671         [0] = &clk_ext_xtal_mux,
 672         [1] = &clk_pcmcdclk0,
 673         [2] = &clk_sclk_hdmi27m,
 674         [3] = &clk_sclk_usbphy0,
 675         [4] = &clk_sclk_usbphy1,
 676         [5] = &clk_sclk_hdmiphy,
 677         [6] = &clk_mout_mpll.clk,
 678         [7] = &clk_mout_epll.clk,
 679         [8] = &clk_sclk_vpll.clk,
 680 };
 681
 682 static struct clksrc_sources clkset_sclk_audio0 = {
 683         .sources        = clkset_sclk_audio0_list,
 684         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 685 };
 686
 687 static struct clksrc_clk clk_sclk_audio0 = {
 688         .clk            = {
 689                 .name           = "sclk_audio",
 690                 .devname        = "soc-audio.0",
 691                 .enable         = s5pv210_clk_mask0_ctrl,
 692                 .ctrlbit        = (1 << 24),
 693         },
 694         .sources = &clkset_sclk_audio0,
 695         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 696         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 697 };
 698
 699 static struct clk *clkset_sclk_audio1_list[] = {
 700         [0] = &clk_ext_xtal_mux,
 701         [1] = &clk_pcmcdclk1,
 702         [2] = &clk_sclk_hdmi27m,
 703         [3] = &clk_sclk_usbphy0,
 704         [4] = &clk_sclk_usbphy1,
 705         [5] = &clk_sclk_hdmiphy,
 706         [6] = &clk_mout_mpll.clk,
 707         [7] = &clk_mout_epll.clk,
 708         [8] = &clk_sclk_vpll.clk,
 709 };
 710
 711 static struct clksrc_sources clkset_sclk_audio1 = {
 712         .sources        = clkset_sclk_audio1_list,
 713         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 714 };
 715
 716 static struct clksrc_clk clk_sclk_audio1 = {
 717         .clk            = {
 718                 .name           = "sclk_audio",
 719                 .devname        = "soc-audio.1",
 720                 .enable         = s5pv210_clk_mask0_ctrl,
 721                 .ctrlbit        = (1 << 25),
 722         },
 723         .sources = &clkset_sclk_audio1,
 724         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 725         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 726 };
 727
 728 static struct clk *clkset_sclk_audio2_list[] = {
 729         [0] = &clk_ext_xtal_mux,
 730         [1] = &clk_pcmcdclk0,
 731         [2] = &clk_sclk_hdmi27m,
 732         [3] = &clk_sclk_usbphy0,
 733         [4] = &clk_sclk_usbphy1,
 734         [5] = &clk_sclk_hdmiphy,
 735         [6] = &clk_mout_mpll.clk,
 736         [7] = &clk_mout_epll.clk,
 737         [8] = &clk_sclk_vpll.clk,
 738 };
 739
 740 static struct clksrc_sources clkset_sclk_audio2 = {
 741         .sources        = clkset_sclk_audio2_list,
 742         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 743 };
 744
 745 static struct clksrc_clk clk_sclk_audio2 = {
 746         .clk            = {
 747                 .name           = "sclk_audio",
 748                 .devname        = "soc-audio.2",
 749                 .enable         = s5pv210_clk_mask0_ctrl,
 750                 .ctrlbit        = (1 << 26),
 751         },
 752         .sources = &clkset_sclk_audio2,
 753         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 754         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 755 };
 756
 757 static struct clk *clkset_sclk_spdif_list[] = {
 758         [0] = &clk_sclk_audio0.clk,
 759         [1] = &clk_sclk_audio1.clk,
 760         [2] = &clk_sclk_audio2.clk,
 761 };
 762
 763 static struct clksrc_sources clkset_sclk_spdif = {
 764         .sources        = clkset_sclk_spdif_list,
 765         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 766 };
 767
 768 static struct clksrc_clk clk_sclk_spdif = {
 769         .clk            = {
 770                 .name           = "sclk_spdif",
 771                 .enable         = s5pv210_clk_mask0_ctrl,
 772                 .ctrlbit        = (1 << 27),
 773                 .ops            = &s5p_sclk_spdif_ops,
 774         },
 775         .sources = &clkset_sclk_spdif,
 776         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 777 };
 778
 779 static struct clk *clkset_group2_list[] = {
 780         [0] = &clk_ext_xtal_mux,
 781         [1] = &clk_xusbxti,
 782         [2] = &clk_sclk_hdmi27m,
 783         [3] = &clk_sclk_usbphy0,
 784         [4] = &clk_sclk_usbphy1,
 785         [5] = &clk_sclk_hdmiphy,
 786         [6] = &clk_mout_mpll.clk,
 787         [7] = &clk_mout_epll.clk,
 788         [8] = &clk_sclk_vpll.clk,
 789 };
 790
 791 static struct clksrc_sources clkset_group2 = {
 792         .sources        = clkset_group2_list,
 793         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 794 };
 795
 796 static struct clksrc_clk clksrcs[] = {
 797         {
 798                 .clk    = {
 799                         .name           = "sclk_dmc",
 800                 },
 801                 .sources = &clkset_group1,
 802                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 803                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 804         }, {
 805                 .clk    = {
 806                         .name           = "sclk_onenand",
 807                 },
 808                 .sources = &clkset_sclk_onenand,
 809                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 810                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 811         }, {
 812                 .clk    = {
 813                         .name           = "sclk_fimc",
 814                         .devname        = "s5pv210-fimc.0",
 815                         .enable         = s5pv210_clk_mask1_ctrl,
 816                         .ctrlbit        = (1 << 2),
 817                 },
 818                 .sources = &clkset_group2,
 819                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 820                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 821         }, {
 822                 .clk    = {
 823                         .name           = "sclk_fimc",
 824                         .devname        = "s5pv210-fimc.1",
 825                         .enable         = s5pv210_clk_mask1_ctrl,
 826                         .ctrlbit        = (1 << 3),
 827                 },
 828                 .sources = &clkset_group2,
 829                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 830                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 831         }, {
 832                 .clk    = {
 833                         .name           = "sclk_fimc",
 834                         .devname        = "s5pv210-fimc.2",
 835                         .enable         = s5pv210_clk_mask1_ctrl,
 836                         .ctrlbit        = (1 << 4),
 837                 },
 838                 .sources = &clkset_group2,
 839                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 840                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 841         }, {
 842                 .clk            = {
 843                         .name           = "sclk_cam0",
 844                         .enable         = s5pv210_clk_mask0_ctrl,
 845                         .ctrlbit        = (1 << 3),
 846                 },
 847                 .sources = &clkset_group2,
 848                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 849                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 850         }, {
 851                 .clk            = {
 852                         .name           = "sclk_cam1",
 853                         .enable         = s5pv210_clk_mask0_ctrl,
 854                         .ctrlbit        = (1 << 4),
 855                 },
 856                 .sources = &clkset_group2,
 857                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 858                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 859         }, {
 860                 .clk            = {
 861                         .name           = "sclk_fimd",
 862                         .enable         = s5pv210_clk_mask0_ctrl,
 863                         .ctrlbit        = (1 << 5),
 864                 },
 865                 .sources = &clkset_group2,
 866                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 867                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 868         }, {
 869                 .clk            = {
 870                         .name           = "sclk_mmc",
 871                         .devname        = "s3c-sdhci.0",
 872                         .enable         = s5pv210_clk_mask0_ctrl,
 873                         .ctrlbit        = (1 << 8),
 874                 },
 875                 .sources = &clkset_group2,
 876                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 877                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 878         }, {
 879                 .clk            = {
 880                         .name           = "sclk_mmc",
 881                         .devname        = "s3c-sdhci.1",
 882                         .enable         = s5pv210_clk_mask0_ctrl,
 883                         .ctrlbit        = (1 << 9),
 884                 },
 885                 .sources = &clkset_group2,
 886                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 887                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 888         }, {
 889                 .clk            = {
 890                         .name           = "sclk_mmc",
 891                         .devname        = "s3c-sdhci.2",
 892                         .enable         = s5pv210_clk_mask0_ctrl,
 893                         .ctrlbit        = (1 << 10),
 894                 },
 895                 .sources = &clkset_group2,
 896                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 897                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 898         }, {
 899                 .clk            = {
 900                         .name           = "sclk_mmc",
 901                         .devname        = "s3c-sdhci.3",
 902                         .enable         = s5pv210_clk_mask0_ctrl,
 903                         .ctrlbit        = (1 << 11),
 904                 },
 905                 .sources = &clkset_group2,
 906                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 907                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 908         }, {
 909                 .clk            = {
 910                         .name           = "sclk_mfc",
 911                         .devname        = "s5p-mfc",
 912                         .enable         = s5pv210_clk_ip0_ctrl,
 913                         .ctrlbit        = (1 << 16),
 914                 },
 915                 .sources = &clkset_group1,
 916                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 917                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 918         }, {
 919                 .clk            = {
 920                         .name           = "sclk_g2d",
 921                         .enable         = s5pv210_clk_ip0_ctrl,
 922                         .ctrlbit        = (1 << 12),
 923                 },
 924                 .sources = &clkset_group1,
 925                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 926                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 927         }, {
 928                 .clk            = {
 929                         .name           = "sclk_g3d",
 930                         .enable         = s5pv210_clk_ip0_ctrl,
 931                         .ctrlbit        = (1 << 8),
 932                 },
 933                 .sources = &clkset_group1,
 934                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 935                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 936         }, {
 937                 .clk            = {
 938                         .name           = "sclk_csis",
 939                         .enable         = s5pv210_clk_mask0_ctrl,
 940                         .ctrlbit        = (1 << 6),
 941                 },
 942                 .sources = &clkset_group2,
 943                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 944                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 945         }, {
 946                 .clk            = {
 947                         .name           = "sclk_spi",
 948                         .devname        = "s3c64xx-spi.0",
 949                         .enable         = s5pv210_clk_mask0_ctrl,
 950                         .ctrlbit        = (1 << 16),
 951                 },
 952                 .sources = &clkset_group2,
 953                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
 954                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
 955         }, {
 956                 .clk            = {
 957                         .name           = "sclk_spi",
 958                         .devname        = "s3c64xx-spi.1",
 959                         .enable         = s5pv210_clk_mask0_ctrl,
 960                         .ctrlbit        = (1 << 17),
 961                 },
 962                 .sources = &clkset_group2,
 963                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
 964                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
 965         }, {
 966                 .clk            = {
 967                         .name           = "sclk_pwi",
 968                         .enable         = s5pv210_clk_mask0_ctrl,
 969                         .ctrlbit        = (1 << 29),
 970                 },
 971                 .sources = &clkset_group2,
 972                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
 973                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
 974         }, {
 975                 .clk            = {
 976                         .name           = "sclk_pwm",
 977                         .enable         = s5pv210_clk_mask0_ctrl,
 978                         .ctrlbit        = (1 << 19),
 979                 },
 980                 .sources = &clkset_group2,
 981                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
 982                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
 983         },
 984 };
 985
 986 static struct clksrc_clk clk_sclk_uart0 = {
 987         .clk    = {
 988                 .name           = "uclk1",
 989                 .devname        = "s5pv210-uart.0",
 990                 .enable         = s5pv210_clk_mask0_ctrl,
 991                 .ctrlbit        = (1 << 12),
 992         },
 993         .sources = &clkset_uart,
 994         .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 995         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 996 };
 997
 998 static struct clksrc_clk clk_sclk_uart1 = {
 999         .clk            = {
1000                 .name           = "uclk1",
1001                 .devname        = "s5pv210-uart.1",
1002                 .enable         = s5pv210_clk_mask0_ctrl,
1003                 .ctrlbit        = (1 << 13),
1004         },
1005         .sources = &clkset_uart,
1006         .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
1007         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
1008 };
1009
1010 static struct clksrc_clk clk_sclk_uart2 = {
1011         .clk            = {
1012                 .name           = "uclk1",
1013                 .devname        = "s5pv210-uart.2",
1014                 .enable         = s5pv210_clk_mask0_ctrl,
1015                 .ctrlbit        = (1 << 14),
1016         },
1017         .sources = &clkset_uart,
1018         .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
1019         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
1020 };
1021
1022 static struct clksrc_clk clk_sclk_uart3 = {
1023         .clk            = {
1024                 .name           = "uclk1",
1025                 .devname        = "s5pv210-uart.3",
1026                 .enable         = s5pv210_clk_mask0_ctrl,
1027                 .ctrlbit        = (1 << 15),
1028         },
1029         .sources = &clkset_uart,
1030         .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
1031         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1032 };
1033
1034 static struct clksrc_clk *clksrc_cdev[] = {
1035         &clk_sclk_uart0,
1036         &clk_sclk_uart1,
1037         &clk_sclk_uart2,
1038         &clk_sclk_uart3,
1039 };
1040
1041 /* Clock initialisation code */
1042 static struct clksrc_clk *sysclks[] = {
1043         &clk_mout_apll,
1044         &clk_mout_epll,
1045         &clk_mout_mpll,
1046         &clk_armclk,
1047         &clk_hclk_msys,
1048         &clk_sclk_a2m,
1049         &clk_hclk_dsys,
1050         &clk_hclk_psys,
1051         &clk_pclk_msys,
1052         &clk_pclk_dsys,
1053         &clk_pclk_psys,
1054         &clk_vpllsrc,
1055         &clk_sclk_vpll,
1056         &clk_mout_dmc0,
1057         &clk_sclk_dmc0,
1058         &clk_sclk_audio0,
1059         &clk_sclk_audio1,
1060         &clk_sclk_audio2,
1061         &clk_sclk_spdif,
1062 };
1063
1064 static u32 epll_div[][6] = {
1065         {  48000000, 0, 48, 3, 3, 0 },
1066         {  96000000, 0, 48, 3, 2, 0 },
1067         { 144000000, 1, 72, 3, 2, 0 },
1068         { 192000000, 0, 48, 3, 1, 0 },
1069         { 288000000, 1, 72, 3, 1, 0 },
1070         {  32750000, 1, 65, 3, 4, 35127 },
1071         {  32768000, 1, 65, 3, 4, 35127 },
1072         {  45158400, 0, 45, 3, 3, 10355 },
1073         {  45000000, 0, 45, 3, 3, 10355 },
1074         {  45158000, 0, 45, 3, 3, 10355 },
1075         {  49125000, 0, 49, 3, 3, 9961 },
1076         {  49152000, 0, 49, 3, 3, 9961 },
1077         {  67737600, 1, 67, 3, 3, 48366 },
1078         {  67738000, 1, 67, 3, 3, 48366 },
1079         {  73800000, 1, 73, 3, 3, 47710 },
1080         {  73728000, 1, 73, 3, 3, 47710 },
1081         {  36000000, 1, 32, 3, 4, 0 },
1082         {  60000000, 1, 60, 3, 3, 0 },
1083         {  72000000, 1, 72, 3, 3, 0 },
1084         {  80000000, 1, 80, 3, 3, 0 },
1085         {  84000000, 0, 42, 3, 2, 0 },
1086         {  50000000, 0, 50, 3, 3, 0 },
1087 };
1088
1089 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1090 {
1091         unsigned int epll_con, epll_con_k;
1092         unsigned int i;
1093
1094         /* Return if nothing changed */
1095         if (clk->rate == rate)
1096                 return 0;
1097
1098         epll_con = __raw_readl(S5P_EPLL_CON);
1099         epll_con_k = __raw_readl(S5P_EPLL_CON1);
1100
1101         epll_con_k &= ~PLL46XX_KDIV_MASK;
1102         epll_con &= ~(1 << 27 |
1103                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1104                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1105                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1106
1107         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1108                 if (epll_div[i][0] == rate) {
1109                         epll_con_k |= epll_div[i][5] << 0;
1110                         epll_con |= (epll_div[i][1] << 27 |
1111                                         epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1112                                         epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1113                                         epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1114                         break;
1115                 }
1116         }
1117
1118         if (i == ARRAY_SIZE(epll_div)) {
1119                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1120                                 __func__);
1121                 return -EINVAL;
1122         }
1123
1124         __raw_writel(epll_con, S5P_EPLL_CON);
1125         __raw_writel(epll_con_k, S5P_EPLL_CON1);
1126
1127         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1128                         clk->rate, rate);
1129
1130         clk->rate = rate;
1131
1132         return 0;
1133 }
1134
1135 static struct clk_ops s5pv210_epll_ops = {
1136         .set_rate = s5pv210_epll_set_rate,
1137         .get_rate = s5p_epll_get_rate,
1138 };
1139
1140 static u32 vpll_div[][5] = {
1141         {  54000000, 3, 53, 3, 0 },
1142         { 108000000, 3, 53, 2, 0 },
1143 };
1144
1145 static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
1146 {
1147         return clk->rate;
1148 }
1149
1150 static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
1151 {
1152         unsigned int vpll_con;
1153         unsigned int i;
1154
1155         /* Return if nothing changed */
1156         if (clk->rate == rate)
1157                 return 0;
1158
1159         vpll_con = __raw_readl(S5P_VPLL_CON);
1160         vpll_con &= ~(0x1 << 27 |                                       \
1161                         PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT |       \
1162                         PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT |       \
1163                         PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
1164
1165         for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1166                 if (vpll_div[i][0] == rate) {
1167                         vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
1168                         vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
1169                         vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
1170                         vpll_con |= vpll_div[i][4] << 27;
1171                         break;
1172                 }
1173         }
1174
1175         if (i == ARRAY_SIZE(vpll_div)) {
1176                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1177                                 __func__);
1178                 return -EINVAL;
1179         }
1180
1181         __raw_writel(vpll_con, S5P_VPLL_CON);
1182
1183         /* Wait for VPLL lock */
1184         while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
1185                 continue;
1186
1187         clk->rate = rate;
1188         return 0;
1189 }
1190 static struct clk_ops s5pv210_vpll_ops = {
1191         .get_rate = s5pv210_vpll_get_rate,
1192         .set_rate = s5pv210_vpll_set_rate,
1193 };
1194
1195 void __init_or_cpufreq s5pv210_setup_clocks(void)
1196 {
1197         struct clk *xtal_clk;
1198         unsigned long vpllsrc;
1199         unsigned long armclk;
1200         unsigned long hclk_msys;
1201         unsigned long hclk_dsys;
1202         unsigned long hclk_psys;
1203         unsigned long pclk_msys;
1204         unsigned long pclk_dsys;
1205         unsigned long pclk_psys;
1206         unsigned long apll;
1207         unsigned long mpll;
1208         unsigned long epll;
1209         unsigned long vpll;
1210         unsigned int ptr;
1211         u32 clkdiv0, clkdiv1;
1212
1213         /* Set functions for clk_fout_epll */
1214         clk_fout_epll.enable = s5p_epll_enable;
1215         clk_fout_epll.ops = &s5pv210_epll_ops;
1216
1217         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1218
1219         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1220         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1221
1222         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1223                                 __func__, clkdiv0, clkdiv1);
1224
1225         xtal_clk = clk_get(NULL, "xtal");
1226         BUG_ON(IS_ERR(xtal_clk));
1227
1228         xtal = clk_get_rate(xtal_clk);
1229         clk_put(xtal_clk);
1230
1231         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1232
1233         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1234         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1235         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1236                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1237         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1238         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1239
1240         clk_fout_apll.ops = &clk_fout_apll_ops;
1241         clk_fout_mpll.rate = mpll;
1242         clk_fout_epll.rate = epll;
1243         clk_fout_vpll.ops = &s5pv210_vpll_ops;
1244         clk_fout_vpll.rate = vpll;
1245
1246         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1247                         apll, mpll, epll, vpll);
1248
1249         armclk = clk_get_rate(&clk_armclk.clk);
1250         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1251         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1252         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1253         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1254         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1255         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1256
1257         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1258                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1259                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1260                         pclk_msys, pclk_dsys, pclk_psys);
1261
1262         clk_f.rate = armclk;
1263         clk_h.rate = hclk_psys;
1264         clk_p.rate = pclk_psys;
1265
1266         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1267                 s3c_set_clksrc(&clksrcs[ptr], true);
1268 }
1269
1270 static struct clk *clks[] __initdata = {
1271         &clk_sclk_hdmi27m,
1272         &clk_sclk_hdmiphy,
1273         &clk_sclk_usbphy0,
1274         &clk_sclk_usbphy1,
1275         &clk_pcmcdclk0,
1276         &clk_pcmcdclk1,
1277         &clk_pcmcdclk2,
1278 };
1279
1280 static struct clk_lookup s5pv210_clk_lookup[] = {
1281         CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1282         CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1283         CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1284         CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1285         CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1286 };
1287
1288 void __init s5pv210_register_clocks(void)
1289 {
1290         int ptr;
1291
1292         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1293
1294         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1295                 s3c_register_clksrc(sysclks[ptr], 1);
1296
1297         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1298                 s3c_register_clksrc(sclk_tv[ptr], 1);
1299
1300         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1301                 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1302
1303         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1304         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1305
1306         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1307         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1308         clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1309
1310         s3c24xx_register_clock(&dummy_apb_pclk);
1311         s3c_pwmclk_init();
1312 }