Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-2.6.git] / arch / arm / mach-s3c64xx / clock.c
1 /* linux/arch/arm/plat-s3c64xx/clock.c
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *      Ben Dooks <ben@simtec.co.uk>
6  *      http://armlinux.simtec.co.uk/
7  *
8  * S3C64XX Base clock support
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22
23 #include <mach/hardware.h>
24 #include <mach/map.h>
25
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
28
29 #include <plat/cpu.h>
30 #include <plat/devs.h>
31 #include <plat/cpu-freq.h>
32 #include <plat/clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/pll.h>
35
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37  * ext_xtal_mux for want of an actual name from the manual.
38 */
39
40 static struct clk clk_ext_xtal_mux = {
41         .name           = "ext_xtal",
42 };
43
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
47
48 #define clk_fout_mpll   clk_mpll
49 #define clk_fout_epll   clk_epll
50
51 struct clk clk_h2 = {
52         .name           = "hclk2",
53         .rate           = 0,
54 };
55
56 struct clk clk_27m = {
57         .name           = "clk_27m",
58         .rate           = 27000000,
59 };
60
61 static int clk_48m_ctrl(struct clk *clk, int enable)
62 {
63         unsigned long flags;
64         u32 val;
65
66         /* can't rely on clock lock, this register has other usages */
67         local_irq_save(flags);
68
69         val = __raw_readl(S3C64XX_OTHERS);
70         if (enable)
71                 val |= S3C64XX_OTHERS_USBMASK;
72         else
73                 val &= ~S3C64XX_OTHERS_USBMASK;
74
75         __raw_writel(val, S3C64XX_OTHERS);
76         local_irq_restore(flags);
77
78         return 0;
79 }
80
81 struct clk clk_48m = {
82         .name           = "clk_48m",
83         .rate           = 48000000,
84         .enable         = clk_48m_ctrl,
85 };
86
87 struct clk clk_xusbxti = {
88         .name           = "xusbxti",
89         .rate           = 48000000,
90 };
91
92 static int inline s3c64xx_gate(void __iomem *reg,
93                                 struct clk *clk,
94                                 int enable)
95 {
96         unsigned int ctrlbit = clk->ctrlbit;
97         u32 con;
98
99         con = __raw_readl(reg);
100
101         if (enable)
102                 con |= ctrlbit;
103         else
104                 con &= ~ctrlbit;
105
106         __raw_writel(con, reg);
107         return 0;
108 }
109
110 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
111 {
112         return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
113 }
114
115 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
116 {
117         return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
118 }
119
120 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
121 {
122         return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
123 }
124
125 static struct clk init_clocks_off[] = {
126         {
127                 .name           = "nand",
128                 .parent         = &clk_h,
129         }, {
130                 .name           = "rtc",
131                 .parent         = &clk_p,
132                 .enable         = s3c64xx_pclk_ctrl,
133                 .ctrlbit        = S3C_CLKCON_PCLK_RTC,
134         }, {
135                 .name           = "adc",
136                 .parent         = &clk_p,
137                 .enable         = s3c64xx_pclk_ctrl,
138                 .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
139         }, {
140                 .name           = "i2c",
141                 .parent         = &clk_p,
142                 .enable         = s3c64xx_pclk_ctrl,
143                 .ctrlbit        = S3C_CLKCON_PCLK_IIC,
144         }, {
145                 .name           = "i2c",
146                 .devname        = "s3c2440-i2c.1",
147                 .parent         = &clk_p,
148                 .enable         = s3c64xx_pclk_ctrl,
149                 .ctrlbit        = S3C6410_CLKCON_PCLK_I2C1,
150         }, {
151                 .name           = "iis",
152                 .devname        = "samsung-i2s.0",
153                 .parent         = &clk_p,
154                 .enable         = s3c64xx_pclk_ctrl,
155                 .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
156         }, {
157                 .name           = "iis",
158                 .devname        = "samsung-i2s.1",
159                 .parent         = &clk_p,
160                 .enable         = s3c64xx_pclk_ctrl,
161                 .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
162         }, {
163 #ifdef CONFIG_CPU_S3C6410
164                 .name           = "iis",
165                 .parent         = &clk_p,
166                 .enable         = s3c64xx_pclk_ctrl,
167                 .ctrlbit        = S3C6410_CLKCON_PCLK_IIS2,
168         }, {
169 #endif
170                 .name           = "keypad",
171                 .parent         = &clk_p,
172                 .enable         = s3c64xx_pclk_ctrl,
173                 .ctrlbit        = S3C_CLKCON_PCLK_KEYPAD,
174         }, {
175                 .name           = "spi",
176                 .devname        = "s3c64xx-spi.0",
177                 .parent         = &clk_p,
178                 .enable         = s3c64xx_pclk_ctrl,
179                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
180         }, {
181                 .name           = "spi",
182                 .devname        = "s3c64xx-spi.1",
183                 .parent         = &clk_p,
184                 .enable         = s3c64xx_pclk_ctrl,
185                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
186         }, {
187                 .name           = "spi_48m",
188                 .devname        = "s3c64xx-spi.0",
189                 .parent         = &clk_48m,
190                 .enable         = s3c64xx_sclk_ctrl,
191                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
192         }, {
193                 .name           = "spi_48m",
194                 .devname        = "s3c64xx-spi.1",
195                 .parent         = &clk_48m,
196                 .enable         = s3c64xx_sclk_ctrl,
197                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
198         }, {
199                 .name           = "48m",
200                 .devname        = "s3c-sdhci.0",
201                 .parent         = &clk_48m,
202                 .enable         = s3c64xx_sclk_ctrl,
203                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
204         }, {
205                 .name           = "48m",
206                 .devname        = "s3c-sdhci.1",
207                 .parent         = &clk_48m,
208                 .enable         = s3c64xx_sclk_ctrl,
209                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
210         }, {
211                 .name           = "48m",
212                 .devname        = "s3c-sdhci.2",
213                 .parent         = &clk_48m,
214                 .enable         = s3c64xx_sclk_ctrl,
215                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
216         }, {
217                 .name           = "dma0",
218                 .parent         = &clk_h,
219                 .enable         = s3c64xx_hclk_ctrl,
220                 .ctrlbit        = S3C_CLKCON_HCLK_DMA0,
221         }, {
222                 .name           = "dma1",
223                 .parent         = &clk_h,
224                 .enable         = s3c64xx_hclk_ctrl,
225                 .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
226         },
227 };
228
229 static struct clk init_clocks[] = {
230         {
231                 .name           = "lcd",
232                 .parent         = &clk_h,
233                 .enable         = s3c64xx_hclk_ctrl,
234                 .ctrlbit        = S3C_CLKCON_HCLK_LCD,
235         }, {
236                 .name           = "gpio",
237                 .parent         = &clk_p,
238                 .enable         = s3c64xx_pclk_ctrl,
239                 .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
240         }, {
241                 .name           = "usb-host",
242                 .parent         = &clk_h,
243                 .enable         = s3c64xx_hclk_ctrl,
244                 .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
245         }, {
246                 .name           = "hsmmc",
247                 .devname        = "s3c-sdhci.0",
248                 .parent         = &clk_h,
249                 .enable         = s3c64xx_hclk_ctrl,
250                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
251         }, {
252                 .name           = "hsmmc",
253                 .devname        = "s3c-sdhci.1",
254                 .parent         = &clk_h,
255                 .enable         = s3c64xx_hclk_ctrl,
256                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
257         }, {
258                 .name           = "hsmmc",
259                 .devname        = "s3c-sdhci.2",
260                 .parent         = &clk_h,
261                 .enable         = s3c64xx_hclk_ctrl,
262                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
263         }, {
264                 .name           = "otg",
265                 .parent         = &clk_h,
266                 .enable         = s3c64xx_hclk_ctrl,
267                 .ctrlbit        = S3C_CLKCON_HCLK_USB,
268         }, {
269                 .name           = "timers",
270                 .parent         = &clk_p,
271                 .enable         = s3c64xx_pclk_ctrl,
272                 .ctrlbit        = S3C_CLKCON_PCLK_PWM,
273         }, {
274                 .name           = "uart",
275                 .devname        = "s3c6400-uart.0",
276                 .parent         = &clk_p,
277                 .enable         = s3c64xx_pclk_ctrl,
278                 .ctrlbit        = S3C_CLKCON_PCLK_UART0,
279         }, {
280                 .name           = "uart",
281                 .devname        = "s3c6400-uart.1",
282                 .parent         = &clk_p,
283                 .enable         = s3c64xx_pclk_ctrl,
284                 .ctrlbit        = S3C_CLKCON_PCLK_UART1,
285         }, {
286                 .name           = "uart",
287                 .devname        = "s3c6400-uart.2",
288                 .parent         = &clk_p,
289                 .enable         = s3c64xx_pclk_ctrl,
290                 .ctrlbit        = S3C_CLKCON_PCLK_UART2,
291         }, {
292                 .name           = "uart",
293                 .devname        = "s3c6400-uart.3",
294                 .parent         = &clk_p,
295                 .enable         = s3c64xx_pclk_ctrl,
296                 .ctrlbit        = S3C_CLKCON_PCLK_UART3,
297         }, {
298                 .name           = "watchdog",
299                 .parent         = &clk_p,
300                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
301         }, {
302                 .name           = "ac97",
303                 .parent         = &clk_p,
304                 .ctrlbit        = S3C_CLKCON_PCLK_AC97,
305         }, {
306                 .name           = "cfcon",
307                 .parent         = &clk_h,
308                 .enable         = s3c64xx_hclk_ctrl,
309                 .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
310         }
311 };
312
313
314 static struct clk clk_fout_apll = {
315         .name           = "fout_apll",
316 };
317
318 static struct clk *clk_src_apll_list[] = {
319         [0] = &clk_fin_apll,
320         [1] = &clk_fout_apll,
321 };
322
323 static struct clksrc_sources clk_src_apll = {
324         .sources        = clk_src_apll_list,
325         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
326 };
327
328 static struct clksrc_clk clk_mout_apll = {
329         .clk    = {
330                 .name           = "mout_apll",
331         },
332         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1  },
333         .sources        = &clk_src_apll,
334 };
335
336 static struct clk *clk_src_epll_list[] = {
337         [0] = &clk_fin_epll,
338         [1] = &clk_fout_epll,
339 };
340
341 static struct clksrc_sources clk_src_epll = {
342         .sources        = clk_src_epll_list,
343         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
344 };
345
346 static struct clksrc_clk clk_mout_epll = {
347         .clk    = {
348                 .name           = "mout_epll",
349         },
350         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1  },
351         .sources        = &clk_src_epll,
352 };
353
354 static struct clk *clk_src_mpll_list[] = {
355         [0] = &clk_fin_mpll,
356         [1] = &clk_fout_mpll,
357 };
358
359 static struct clksrc_sources clk_src_mpll = {
360         .sources        = clk_src_mpll_list,
361         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
362 };
363
364 static struct clksrc_clk clk_mout_mpll = {
365         .clk = {
366                 .name           = "mout_mpll",
367         },
368         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1  },
369         .sources        = &clk_src_mpll,
370 };
371
372 static unsigned int armclk_mask;
373
374 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
375 {
376         unsigned long rate = clk_get_rate(clk->parent);
377         u32 clkdiv;
378
379         /* divisor mask starts at bit0, so no need to shift */
380         clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
381
382         return rate / (clkdiv + 1);
383 }
384
385 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
386                                                 unsigned long rate)
387 {
388         unsigned long parent = clk_get_rate(clk->parent);
389         u32 div;
390
391         if (parent < rate)
392                 return parent;
393
394         div = (parent / rate) - 1;
395         if (div > armclk_mask)
396                 div = armclk_mask;
397
398         return parent / (div + 1);
399 }
400
401 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
402 {
403         unsigned long parent = clk_get_rate(clk->parent);
404         u32 div;
405         u32 val;
406
407         if (rate < parent / (armclk_mask + 1))
408                 return -EINVAL;
409
410         rate = clk_round_rate(clk, rate);
411         div = clk_get_rate(clk->parent) / rate;
412
413         val = __raw_readl(S3C_CLK_DIV0);
414         val &= ~armclk_mask;
415         val |= (div - 1);
416         __raw_writel(val, S3C_CLK_DIV0);
417
418         return 0;
419
420 }
421
422 static struct clk clk_arm = {
423         .name           = "armclk",
424         .parent         = &clk_mout_apll.clk,
425         .ops            = &(struct clk_ops) {
426                 .get_rate       = s3c64xx_clk_arm_get_rate,
427                 .set_rate       = s3c64xx_clk_arm_set_rate,
428                 .round_rate     = s3c64xx_clk_arm_round_rate,
429         },
430 };
431
432 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
433 {
434         unsigned long rate = clk_get_rate(clk->parent);
435
436         printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
437
438         if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
439                 rate /= 2;
440
441         return rate;
442 }
443
444 static struct clk_ops clk_dout_ops = {
445         .get_rate       = s3c64xx_clk_doutmpll_get_rate,
446 };
447
448 static struct clk clk_dout_mpll = {
449         .name           = "dout_mpll",
450         .parent         = &clk_mout_mpll.clk,
451         .ops            = &clk_dout_ops,
452 };
453
454 static struct clk *clkset_spi_mmc_list[] = {
455         &clk_mout_epll.clk,
456         &clk_dout_mpll,
457         &clk_fin_epll,
458         &clk_27m,
459 };
460
461 static struct clksrc_sources clkset_spi_mmc = {
462         .sources        = clkset_spi_mmc_list,
463         .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
464 };
465
466 static struct clk *clkset_irda_list[] = {
467         &clk_mout_epll.clk,
468         &clk_dout_mpll,
469         NULL,
470         &clk_27m,
471 };
472
473 static struct clksrc_sources clkset_irda = {
474         .sources        = clkset_irda_list,
475         .nr_sources     = ARRAY_SIZE(clkset_irda_list),
476 };
477
478 static struct clk *clkset_uart_list[] = {
479         &clk_mout_epll.clk,
480         &clk_dout_mpll,
481         NULL,
482         NULL
483 };
484
485 static struct clksrc_sources clkset_uart = {
486         .sources        = clkset_uart_list,
487         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
488 };
489
490 static struct clk *clkset_uhost_list[] = {
491         &clk_48m,
492         &clk_mout_epll.clk,
493         &clk_dout_mpll,
494         &clk_fin_epll,
495 };
496
497 static struct clksrc_sources clkset_uhost = {
498         .sources        = clkset_uhost_list,
499         .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
500 };
501
502 /* The peripheral clocks are all controlled via clocksource followed
503  * by an optional divider and gate stage. We currently roll this into
504  * one clock which hides the intermediate clock from the mux.
505  *
506  * Note, the JPEG clock can only be an even divider...
507  *
508  * The scaler and LCD clocks depend on the S3C64XX version, and also
509  * have a common parent divisor so are not included here.
510  */
511
512 /* clocks that feed other parts of the clock source tree */
513
514 static struct clk clk_iis_cd0 = {
515         .name           = "iis_cdclk0",
516 };
517
518 static struct clk clk_iis_cd1 = {
519         .name           = "iis_cdclk1",
520 };
521
522 static struct clk clk_iisv4_cd = {
523         .name           = "iis_cdclk_v4",
524 };
525
526 static struct clk clk_pcm_cd = {
527         .name           = "pcm_cdclk",
528 };
529
530 static struct clk *clkset_audio0_list[] = {
531         [0] = &clk_mout_epll.clk,
532         [1] = &clk_dout_mpll,
533         [2] = &clk_fin_epll,
534         [3] = &clk_iis_cd0,
535         [4] = &clk_pcm_cd,
536 };
537
538 static struct clksrc_sources clkset_audio0 = {
539         .sources        = clkset_audio0_list,
540         .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
541 };
542
543 static struct clk *clkset_audio1_list[] = {
544         [0] = &clk_mout_epll.clk,
545         [1] = &clk_dout_mpll,
546         [2] = &clk_fin_epll,
547         [3] = &clk_iis_cd1,
548         [4] = &clk_pcm_cd,
549 };
550
551 static struct clksrc_sources clkset_audio1 = {
552         .sources        = clkset_audio1_list,
553         .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
554 };
555
556 static struct clk *clkset_audio2_list[] = {
557         [0] = &clk_mout_epll.clk,
558         [1] = &clk_dout_mpll,
559         [2] = &clk_fin_epll,
560         [3] = &clk_iisv4_cd,
561         [4] = &clk_pcm_cd,
562 };
563
564 static struct clksrc_sources clkset_audio2 = {
565         .sources        = clkset_audio2_list,
566         .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
567 };
568
569 static struct clk *clkset_camif_list[] = {
570         &clk_h2,
571 };
572
573 static struct clksrc_sources clkset_camif = {
574         .sources        = clkset_camif_list,
575         .nr_sources     = ARRAY_SIZE(clkset_camif_list),
576 };
577
578 static struct clksrc_clk clksrcs[] = {
579         {
580                 .clk    = {
581                         .name           = "mmc_bus",
582                         .devname        = "s3c-sdhci.0",
583                         .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
584                         .enable         = s3c64xx_sclk_ctrl,
585                 },
586                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
587                 .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
588                 .sources        = &clkset_spi_mmc,
589         }, {
590                 .clk    = {
591                         .name           = "mmc_bus",
592                         .devname        = "s3c-sdhci.1",
593                         .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
594                         .enable         = s3c64xx_sclk_ctrl,
595                 },
596                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
597                 .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
598                 .sources        = &clkset_spi_mmc,
599         }, {
600                 .clk    = {
601                         .name           = "mmc_bus",
602                         .devname        = "s3c-sdhci.2",
603                         .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
604                         .enable         = s3c64xx_sclk_ctrl,
605                 },
606                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
607                 .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
608                 .sources        = &clkset_spi_mmc,
609         }, {
610                 .clk    = {
611                         .name           = "usb-bus-host",
612                         .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
613                         .enable         = s3c64xx_sclk_ctrl,
614                 },
615                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },
616                 .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
617                 .sources        = &clkset_uhost,
618         }, {
619                 .clk    = {
620                         .name           = "spi-bus",
621                         .devname        = "s3c64xx-spi.0",
622                         .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
623                         .enable         = s3c64xx_sclk_ctrl,
624                 },
625                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },
626                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },
627                 .sources        = &clkset_spi_mmc,
628         }, {
629                 .clk    = {
630                         .name           = "spi-bus",
631                         .devname        = "s3c64xx-spi.1",
632                         .enable         = s3c64xx_sclk_ctrl,
633                 },
634                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },
635                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },
636                 .sources        = &clkset_spi_mmc,
637         }, {
638                 .clk    = {
639                         .name           = "audio-bus",
640                         .devname        = "samsung-i2s.0",
641                         .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
642                         .enable         = s3c64xx_sclk_ctrl,
643                 },
644                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3  },
645                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4  },
646                 .sources        = &clkset_audio0,
647         }, {
648                 .clk    = {
649                         .name           = "audio-bus",
650                         .devname        = "samsung-i2s.1",
651                         .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
652                         .enable         = s3c64xx_sclk_ctrl,
653                 },
654                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3  },
655                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4  },
656                 .sources        = &clkset_audio1,
657         }, {
658                 .clk    = {
659                         .name           = "audio-bus",
660                         .devname        = "samsung-i2s.2",
661                         .ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
662                         .enable         = s3c64xx_sclk_ctrl,
663                 },
664                 .reg_src        = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3  },
665                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4  },
666                 .sources        = &clkset_audio2,
667         }, {
668                 .clk    = {
669                         .name           = "irda-bus",
670                         .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
671                         .enable         = s3c64xx_sclk_ctrl,
672                 },
673                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2  },
674                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4  },
675                 .sources        = &clkset_irda,
676         }, {
677                 .clk    = {
678                         .name           = "camera",
679                         .ctrlbit        = S3C_CLKCON_SCLK_CAM,
680                         .enable         = s3c64xx_sclk_ctrl,
681                 },
682                 .reg_div        = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
683                 .reg_src        = { .reg = NULL, .shift = 0, .size = 0  },
684                 .sources        = &clkset_camif,
685         },
686 };
687
688 /* Where does UCLK0 come from? */
689 static struct clksrc_clk clk_sclk_uclk = {
690         .clk    = {
691                 .name           = "uclk1",
692                 .ctrlbit        = S3C_CLKCON_SCLK_UART,
693                 .enable         = s3c64xx_sclk_ctrl,
694         },
695         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
696         .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
697         .sources        = &clkset_uart,
698 };
699
700 /* Clock initialisation code */
701
702 static struct clksrc_clk *init_parents[] = {
703         &clk_mout_apll,
704         &clk_mout_epll,
705         &clk_mout_mpll,
706 };
707
708 static struct clksrc_clk *clksrc_cdev[] = {
709         &clk_sclk_uclk,
710 };
711
712 static struct clk_lookup s3c64xx_clk_lookup[] = {
713         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
714         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
715 };
716
717 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
718
719 void __init_or_cpufreq s3c64xx_setup_clocks(void)
720 {
721         struct clk *xtal_clk;
722         unsigned long xtal;
723         unsigned long fclk;
724         unsigned long hclk;
725         unsigned long hclk2;
726         unsigned long pclk;
727         unsigned long epll;
728         unsigned long apll;
729         unsigned long mpll;
730         unsigned int ptr;
731         u32 clkdiv0;
732
733         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
734
735         clkdiv0 = __raw_readl(S3C_CLK_DIV0);
736         printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
737
738         xtal_clk = clk_get(NULL, "xtal");
739         BUG_ON(IS_ERR(xtal_clk));
740
741         xtal = clk_get_rate(xtal_clk);
742         clk_put(xtal_clk);
743
744         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
745
746         /* For now assume the mux always selects the crystal */
747         clk_ext_xtal_mux.parent = xtal_clk;
748
749         epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
750                                 __raw_readl(S3C_EPLL_CON1));
751         mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
752         apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
753
754         fclk = mpll;
755
756         printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
757                apll, mpll, epll);
758
759         if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
760                 /* Synchronous mode */
761                 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
762         else
763                 /* Asynchronous mode */
764                 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
765
766         hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
767         pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
768
769         printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
770                hclk2, hclk, pclk);
771
772         clk_fout_mpll.rate = mpll;
773         clk_fout_epll.rate = epll;
774         clk_fout_apll.rate = apll;
775
776         clk_h2.rate = hclk2;
777         clk_h.rate = hclk;
778         clk_p.rate = pclk;
779         clk_f.rate = fclk;
780
781         for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
782                 s3c_set_clksrc(init_parents[ptr], true);
783
784         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
785                 s3c_set_clksrc(&clksrcs[ptr], true);
786 }
787
788 static struct clk *clks1[] __initdata = {
789         &clk_ext_xtal_mux,
790         &clk_iis_cd0,
791         &clk_iis_cd1,
792         &clk_iisv4_cd,
793         &clk_pcm_cd,
794         &clk_mout_epll.clk,
795         &clk_mout_mpll.clk,
796         &clk_dout_mpll,
797         &clk_arm,
798 };
799
800 static struct clk *clks[] __initdata = {
801         &clk_ext,
802         &clk_epll,
803         &clk_27m,
804         &clk_48m,
805         &clk_h2,
806         &clk_xusbxti,
807 };
808
809 /**
810  * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
811  * @xtal: The rate for the clock crystal feeding the PLLs.
812  * @armclk_divlimit: Divisor mask for ARMCLK.
813  *
814  * Register the clocks for the S3C6400 and S3C6410 SoC range, such
815  * as ARMCLK as well as the necessary parent clocks.
816  *
817  * This call does not setup the clocks, which is left to the
818  * s3c64xx_setup_clocks() call which may be needed by the cpufreq
819  * or resume code to re-set the clocks if the bootloader has changed
820  * them.
821  */
822 void __init s3c64xx_register_clocks(unsigned long xtal, 
823                                     unsigned armclk_divlimit)
824 {
825         unsigned int cnt;
826
827         armclk_mask = armclk_divlimit;
828
829         s3c24xx_register_baseclocks(xtal);
830         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
831
832         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
833
834         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
835         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
836
837         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
838         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
839         for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
840                 s3c_register_clksrc(clksrc_cdev[cnt], 1);
841         clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
842
843         s3c_pwmclk_init();
844 }