Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-2.6.git] / arch / arm / mach-s3c64xx / clock.c
1 /* linux/arch/arm/plat-s3c64xx/clock.c
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *      Ben Dooks <ben@simtec.co.uk>
6  *      http://armlinux.simtec.co.uk/
7  *
8  * S3C64XX Base clock support
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22
23 #include <mach/hardware.h>
24 #include <mach/map.h>
25
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
28
29 #include <plat/cpu.h>
30 #include <plat/devs.h>
31 #include <plat/cpu-freq.h>
32 #include <plat/clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/pll.h>
35
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37  * ext_xtal_mux for want of an actual name from the manual.
38 */
39
40 static struct clk clk_ext_xtal_mux = {
41         .name           = "ext_xtal",
42 };
43
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
47
48 #define clk_fout_mpll   clk_mpll
49 #define clk_fout_epll   clk_epll
50
51 struct clk clk_h2 = {
52         .name           = "hclk2",
53         .rate           = 0,
54 };
55
56 struct clk clk_27m = {
57         .name           = "clk_27m",
58         .rate           = 27000000,
59 };
60
61 static int clk_48m_ctrl(struct clk *clk, int enable)
62 {
63         unsigned long flags;
64         u32 val;
65
66         /* can't rely on clock lock, this register has other usages */
67         local_irq_save(flags);
68
69         val = __raw_readl(S3C64XX_OTHERS);
70         if (enable)
71                 val |= S3C64XX_OTHERS_USBMASK;
72         else
73                 val &= ~S3C64XX_OTHERS_USBMASK;
74
75         __raw_writel(val, S3C64XX_OTHERS);
76         local_irq_restore(flags);
77
78         return 0;
79 }
80
81 struct clk clk_48m = {
82         .name           = "clk_48m",
83         .rate           = 48000000,
84         .enable         = clk_48m_ctrl,
85 };
86
87 struct clk clk_xusbxti = {
88         .name           = "xusbxti",
89         .rate           = 48000000,
90 };
91
92 static int inline s3c64xx_gate(void __iomem *reg,
93                                 struct clk *clk,
94                                 int enable)
95 {
96         unsigned int ctrlbit = clk->ctrlbit;
97         u32 con;
98
99         con = __raw_readl(reg);
100
101         if (enable)
102                 con |= ctrlbit;
103         else
104                 con &= ~ctrlbit;
105
106         __raw_writel(con, reg);
107         return 0;
108 }
109
110 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
111 {
112         return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
113 }
114
115 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
116 {
117         return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
118 }
119
120 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
121 {
122         return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
123 }
124
125 static struct clk init_clocks_off[] = {
126         {
127                 .name           = "nand",
128                 .parent         = &clk_h,
129         }, {
130                 .name           = "rtc",
131                 .parent         = &clk_p,
132                 .enable         = s3c64xx_pclk_ctrl,
133                 .ctrlbit        = S3C_CLKCON_PCLK_RTC,
134         }, {
135                 .name           = "adc",
136                 .parent         = &clk_p,
137                 .enable         = s3c64xx_pclk_ctrl,
138                 .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
139         }, {
140                 .name           = "i2c",
141                 .parent         = &clk_p,
142                 .enable         = s3c64xx_pclk_ctrl,
143                 .ctrlbit        = S3C_CLKCON_PCLK_IIC,
144         }, {
145                 .name           = "i2c",
146                 .devname        = "s3c2440-i2c.1",
147                 .parent         = &clk_p,
148                 .enable         = s3c64xx_pclk_ctrl,
149                 .ctrlbit        = S3C6410_CLKCON_PCLK_I2C1,
150         }, {
151                 .name           = "iis",
152                 .devname        = "samsung-i2s.0",
153                 .parent         = &clk_p,
154                 .enable         = s3c64xx_pclk_ctrl,
155                 .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
156         }, {
157                 .name           = "iis",
158                 .devname        = "samsung-i2s.1",
159                 .parent         = &clk_p,
160                 .enable         = s3c64xx_pclk_ctrl,
161                 .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
162         }, {
163 #ifdef CONFIG_CPU_S3C6410
164                 .name           = "iis",
165                 .parent         = &clk_p,
166                 .enable         = s3c64xx_pclk_ctrl,
167                 .ctrlbit        = S3C6410_CLKCON_PCLK_IIS2,
168         }, {
169 #endif
170                 .name           = "keypad",
171                 .parent         = &clk_p,
172                 .enable         = s3c64xx_pclk_ctrl,
173                 .ctrlbit        = S3C_CLKCON_PCLK_KEYPAD,
174         }, {
175                 .name           = "spi",
176                 .devname        = "s3c64xx-spi.0",
177                 .parent         = &clk_p,
178                 .enable         = s3c64xx_pclk_ctrl,
179                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
180         }, {
181                 .name           = "spi",
182                 .devname        = "s3c64xx-spi.1",
183                 .parent         = &clk_p,
184                 .enable         = s3c64xx_pclk_ctrl,
185                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
186         }, {
187                 .name           = "48m",
188                 .devname        = "s3c-sdhci.0",
189                 .parent         = &clk_48m,
190                 .enable         = s3c64xx_sclk_ctrl,
191                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
192         }, {
193                 .name           = "48m",
194                 .devname        = "s3c-sdhci.1",
195                 .parent         = &clk_48m,
196                 .enable         = s3c64xx_sclk_ctrl,
197                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
198         }, {
199                 .name           = "48m",
200                 .devname        = "s3c-sdhci.2",
201                 .parent         = &clk_48m,
202                 .enable         = s3c64xx_sclk_ctrl,
203                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
204         }, {
205                 .name           = "dma0",
206                 .parent         = &clk_h,
207                 .enable         = s3c64xx_hclk_ctrl,
208                 .ctrlbit        = S3C_CLKCON_HCLK_DMA0,
209         }, {
210                 .name           = "dma1",
211                 .parent         = &clk_h,
212                 .enable         = s3c64xx_hclk_ctrl,
213                 .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
214         },
215 };
216
217 static struct clk clk_48m_spi0 = {
218         .name           = "spi_48m",
219         .devname        = "s3c64xx-spi.0",
220         .parent         = &clk_48m,
221         .enable         = s3c64xx_sclk_ctrl,
222         .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
223 };
224
225 static struct clk clk_48m_spi1 = {
226         .name           = "spi_48m",
227         .devname        = "s3c64xx-spi.1",
228         .parent         = &clk_48m,
229         .enable         = s3c64xx_sclk_ctrl,
230         .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
231 };
232
233 static struct clk init_clocks[] = {
234         {
235                 .name           = "lcd",
236                 .parent         = &clk_h,
237                 .enable         = s3c64xx_hclk_ctrl,
238                 .ctrlbit        = S3C_CLKCON_HCLK_LCD,
239         }, {
240                 .name           = "gpio",
241                 .parent         = &clk_p,
242                 .enable         = s3c64xx_pclk_ctrl,
243                 .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
244         }, {
245                 .name           = "usb-host",
246                 .parent         = &clk_h,
247                 .enable         = s3c64xx_hclk_ctrl,
248                 .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
249         }, {
250                 .name           = "otg",
251                 .parent         = &clk_h,
252                 .enable         = s3c64xx_hclk_ctrl,
253                 .ctrlbit        = S3C_CLKCON_HCLK_USB,
254         }, {
255                 .name           = "timers",
256                 .parent         = &clk_p,
257                 .enable         = s3c64xx_pclk_ctrl,
258                 .ctrlbit        = S3C_CLKCON_PCLK_PWM,
259         }, {
260                 .name           = "uart",
261                 .devname        = "s3c6400-uart.0",
262                 .parent         = &clk_p,
263                 .enable         = s3c64xx_pclk_ctrl,
264                 .ctrlbit        = S3C_CLKCON_PCLK_UART0,
265         }, {
266                 .name           = "uart",
267                 .devname        = "s3c6400-uart.1",
268                 .parent         = &clk_p,
269                 .enable         = s3c64xx_pclk_ctrl,
270                 .ctrlbit        = S3C_CLKCON_PCLK_UART1,
271         }, {
272                 .name           = "uart",
273                 .devname        = "s3c6400-uart.2",
274                 .parent         = &clk_p,
275                 .enable         = s3c64xx_pclk_ctrl,
276                 .ctrlbit        = S3C_CLKCON_PCLK_UART2,
277         }, {
278                 .name           = "uart",
279                 .devname        = "s3c6400-uart.3",
280                 .parent         = &clk_p,
281                 .enable         = s3c64xx_pclk_ctrl,
282                 .ctrlbit        = S3C_CLKCON_PCLK_UART3,
283         }, {
284                 .name           = "watchdog",
285                 .parent         = &clk_p,
286                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
287         }, {
288                 .name           = "ac97",
289                 .parent         = &clk_p,
290                 .ctrlbit        = S3C_CLKCON_PCLK_AC97,
291         }, {
292                 .name           = "cfcon",
293                 .parent         = &clk_h,
294                 .enable         = s3c64xx_hclk_ctrl,
295                 .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
296         }
297 };
298
299 static struct clk clk_hsmmc0 = {
300         .name           = "hsmmc",
301         .devname        = "s3c-sdhci.0",
302         .parent         = &clk_h,
303         .enable         = s3c64xx_hclk_ctrl,
304         .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
305 };
306
307 static struct clk clk_hsmmc1 = {
308         .name           = "hsmmc",
309         .devname        = "s3c-sdhci.1",
310         .parent         = &clk_h,
311         .enable         = s3c64xx_hclk_ctrl,
312         .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
313 };
314
315 static struct clk clk_hsmmc2 = {
316         .name           = "hsmmc",
317         .devname        = "s3c-sdhci.2",
318         .parent         = &clk_h,
319         .enable         = s3c64xx_hclk_ctrl,
320         .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
321 };
322
323 static struct clk clk_fout_apll = {
324         .name           = "fout_apll",
325 };
326
327 static struct clk *clk_src_apll_list[] = {
328         [0] = &clk_fin_apll,
329         [1] = &clk_fout_apll,
330 };
331
332 static struct clksrc_sources clk_src_apll = {
333         .sources        = clk_src_apll_list,
334         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
335 };
336
337 static struct clksrc_clk clk_mout_apll = {
338         .clk    = {
339                 .name           = "mout_apll",
340         },
341         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1  },
342         .sources        = &clk_src_apll,
343 };
344
345 static struct clk *clk_src_epll_list[] = {
346         [0] = &clk_fin_epll,
347         [1] = &clk_fout_epll,
348 };
349
350 static struct clksrc_sources clk_src_epll = {
351         .sources        = clk_src_epll_list,
352         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
353 };
354
355 static struct clksrc_clk clk_mout_epll = {
356         .clk    = {
357                 .name           = "mout_epll",
358         },
359         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1  },
360         .sources        = &clk_src_epll,
361 };
362
363 static struct clk *clk_src_mpll_list[] = {
364         [0] = &clk_fin_mpll,
365         [1] = &clk_fout_mpll,
366 };
367
368 static struct clksrc_sources clk_src_mpll = {
369         .sources        = clk_src_mpll_list,
370         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
371 };
372
373 static struct clksrc_clk clk_mout_mpll = {
374         .clk = {
375                 .name           = "mout_mpll",
376         },
377         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1  },
378         .sources        = &clk_src_mpll,
379 };
380
381 static unsigned int armclk_mask;
382
383 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
384 {
385         unsigned long rate = clk_get_rate(clk->parent);
386         u32 clkdiv;
387
388         /* divisor mask starts at bit0, so no need to shift */
389         clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
390
391         return rate / (clkdiv + 1);
392 }
393
394 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
395                                                 unsigned long rate)
396 {
397         unsigned long parent = clk_get_rate(clk->parent);
398         u32 div;
399
400         if (parent < rate)
401                 return parent;
402
403         div = (parent / rate) - 1;
404         if (div > armclk_mask)
405                 div = armclk_mask;
406
407         return parent / (div + 1);
408 }
409
410 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
411 {
412         unsigned long parent = clk_get_rate(clk->parent);
413         u32 div;
414         u32 val;
415
416         if (rate < parent / (armclk_mask + 1))
417                 return -EINVAL;
418
419         rate = clk_round_rate(clk, rate);
420         div = clk_get_rate(clk->parent) / rate;
421
422         val = __raw_readl(S3C_CLK_DIV0);
423         val &= ~armclk_mask;
424         val |= (div - 1);
425         __raw_writel(val, S3C_CLK_DIV0);
426
427         return 0;
428
429 }
430
431 static struct clk clk_arm = {
432         .name           = "armclk",
433         .parent         = &clk_mout_apll.clk,
434         .ops            = &(struct clk_ops) {
435                 .get_rate       = s3c64xx_clk_arm_get_rate,
436                 .set_rate       = s3c64xx_clk_arm_set_rate,
437                 .round_rate     = s3c64xx_clk_arm_round_rate,
438         },
439 };
440
441 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
442 {
443         unsigned long rate = clk_get_rate(clk->parent);
444
445         printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
446
447         if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
448                 rate /= 2;
449
450         return rate;
451 }
452
453 static struct clk_ops clk_dout_ops = {
454         .get_rate       = s3c64xx_clk_doutmpll_get_rate,
455 };
456
457 static struct clk clk_dout_mpll = {
458         .name           = "dout_mpll",
459         .parent         = &clk_mout_mpll.clk,
460         .ops            = &clk_dout_ops,
461 };
462
463 static struct clk *clkset_spi_mmc_list[] = {
464         &clk_mout_epll.clk,
465         &clk_dout_mpll,
466         &clk_fin_epll,
467         &clk_27m,
468 };
469
470 static struct clksrc_sources clkset_spi_mmc = {
471         .sources        = clkset_spi_mmc_list,
472         .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
473 };
474
475 static struct clk *clkset_irda_list[] = {
476         &clk_mout_epll.clk,
477         &clk_dout_mpll,
478         NULL,
479         &clk_27m,
480 };
481
482 static struct clksrc_sources clkset_irda = {
483         .sources        = clkset_irda_list,
484         .nr_sources     = ARRAY_SIZE(clkset_irda_list),
485 };
486
487 static struct clk *clkset_uart_list[] = {
488         &clk_mout_epll.clk,
489         &clk_dout_mpll,
490         NULL,
491         NULL
492 };
493
494 static struct clksrc_sources clkset_uart = {
495         .sources        = clkset_uart_list,
496         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
497 };
498
499 static struct clk *clkset_uhost_list[] = {
500         &clk_48m,
501         &clk_mout_epll.clk,
502         &clk_dout_mpll,
503         &clk_fin_epll,
504 };
505
506 static struct clksrc_sources clkset_uhost = {
507         .sources        = clkset_uhost_list,
508         .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
509 };
510
511 /* The peripheral clocks are all controlled via clocksource followed
512  * by an optional divider and gate stage. We currently roll this into
513  * one clock which hides the intermediate clock from the mux.
514  *
515  * Note, the JPEG clock can only be an even divider...
516  *
517  * The scaler and LCD clocks depend on the S3C64XX version, and also
518  * have a common parent divisor so are not included here.
519  */
520
521 /* clocks that feed other parts of the clock source tree */
522
523 static struct clk clk_iis_cd0 = {
524         .name           = "iis_cdclk0",
525 };
526
527 static struct clk clk_iis_cd1 = {
528         .name           = "iis_cdclk1",
529 };
530
531 static struct clk clk_iisv4_cd = {
532         .name           = "iis_cdclk_v4",
533 };
534
535 static struct clk clk_pcm_cd = {
536         .name           = "pcm_cdclk",
537 };
538
539 static struct clk *clkset_audio0_list[] = {
540         [0] = &clk_mout_epll.clk,
541         [1] = &clk_dout_mpll,
542         [2] = &clk_fin_epll,
543         [3] = &clk_iis_cd0,
544         [4] = &clk_pcm_cd,
545 };
546
547 static struct clksrc_sources clkset_audio0 = {
548         .sources        = clkset_audio0_list,
549         .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
550 };
551
552 static struct clk *clkset_audio1_list[] = {
553         [0] = &clk_mout_epll.clk,
554         [1] = &clk_dout_mpll,
555         [2] = &clk_fin_epll,
556         [3] = &clk_iis_cd1,
557         [4] = &clk_pcm_cd,
558 };
559
560 static struct clksrc_sources clkset_audio1 = {
561         .sources        = clkset_audio1_list,
562         .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
563 };
564
565 static struct clk *clkset_audio2_list[] = {
566         [0] = &clk_mout_epll.clk,
567         [1] = &clk_dout_mpll,
568         [2] = &clk_fin_epll,
569         [3] = &clk_iisv4_cd,
570         [4] = &clk_pcm_cd,
571 };
572
573 static struct clksrc_sources clkset_audio2 = {
574         .sources        = clkset_audio2_list,
575         .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
576 };
577
578 static struct clk *clkset_camif_list[] = {
579         &clk_h2,
580 };
581
582 static struct clksrc_sources clkset_camif = {
583         .sources        = clkset_camif_list,
584         .nr_sources     = ARRAY_SIZE(clkset_camif_list),
585 };
586
587 static struct clksrc_clk clksrcs[] = {
588         {
589                 .clk    = {
590                         .name           = "usb-bus-host",
591                         .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
592                         .enable         = s3c64xx_sclk_ctrl,
593                 },
594                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },
595                 .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
596                 .sources        = &clkset_uhost,
597         }, {
598                 .clk    = {
599                         .name           = "audio-bus",
600                         .devname        = "samsung-i2s.0",
601                         .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
602                         .enable         = s3c64xx_sclk_ctrl,
603                 },
604                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3  },
605                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4  },
606                 .sources        = &clkset_audio0,
607         }, {
608                 .clk    = {
609                         .name           = "audio-bus",
610                         .devname        = "samsung-i2s.1",
611                         .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
612                         .enable         = s3c64xx_sclk_ctrl,
613                 },
614                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3  },
615                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4  },
616                 .sources        = &clkset_audio1,
617         }, {
618                 .clk    = {
619                         .name           = "audio-bus",
620                         .devname        = "samsung-i2s.2",
621                         .ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
622                         .enable         = s3c64xx_sclk_ctrl,
623                 },
624                 .reg_src        = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3  },
625                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4  },
626                 .sources        = &clkset_audio2,
627         }, {
628                 .clk    = {
629                         .name           = "irda-bus",
630                         .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
631                         .enable         = s3c64xx_sclk_ctrl,
632                 },
633                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2  },
634                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4  },
635                 .sources        = &clkset_irda,
636         }, {
637                 .clk    = {
638                         .name           = "camera",
639                         .ctrlbit        = S3C_CLKCON_SCLK_CAM,
640                         .enable         = s3c64xx_sclk_ctrl,
641                 },
642                 .reg_div        = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
643                 .reg_src        = { .reg = NULL, .shift = 0, .size = 0  },
644                 .sources        = &clkset_camif,
645         },
646 };
647
648 /* Where does UCLK0 come from? */
649 static struct clksrc_clk clk_sclk_uclk = {
650         .clk    = {
651                 .name           = "uclk1",
652                 .ctrlbit        = S3C_CLKCON_SCLK_UART,
653                 .enable         = s3c64xx_sclk_ctrl,
654         },
655         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
656         .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
657         .sources        = &clkset_uart,
658 };
659
660 static struct clksrc_clk clk_sclk_mmc0 = {
661         .clk    = {
662                 .name           = "mmc_bus",
663                 .devname        = "s3c-sdhci.0",
664                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
665                 .enable         = s3c64xx_sclk_ctrl,
666         },
667         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
668         .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
669         .sources        = &clkset_spi_mmc,
670 };
671
672 static struct clksrc_clk clk_sclk_mmc1 = {
673         .clk    = {
674                 .name           = "mmc_bus",
675                 .devname        = "s3c-sdhci.1",
676                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
677                 .enable         = s3c64xx_sclk_ctrl,
678         },
679         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
680         .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
681         .sources        = &clkset_spi_mmc,
682 };
683
684 static struct clksrc_clk clk_sclk_mmc2 = {
685         .clk    = {
686                 .name           = "mmc_bus",
687                 .devname        = "s3c-sdhci.2",
688                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
689                 .enable         = s3c64xx_sclk_ctrl,
690         },
691         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
692         .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
693         .sources        = &clkset_spi_mmc,
694 };
695
696 static struct clksrc_clk clk_sclk_spi0 = {
697         .clk    = {
698                 .name           = "spi-bus",
699                 .devname        = "s3c64xx-spi.0",
700                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
701                 .enable         = s3c64xx_sclk_ctrl,
702         },
703         .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704         .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705         .sources = &clkset_spi_mmc,
706 };
707
708 static struct clksrc_clk clk_sclk_spi1 = {
709         .clk    = {
710                 .name           = "spi-bus",
711                 .devname        = "s3c64xx-spi.1",
712                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
713                 .enable         = s3c64xx_sclk_ctrl,
714         },
715         .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716         .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717         .sources = &clkset_spi_mmc,
718 };
719
720 /* Clock initialisation code */
721
722 static struct clksrc_clk *init_parents[] = {
723         &clk_mout_apll,
724         &clk_mout_epll,
725         &clk_mout_mpll,
726 };
727
728 static struct clksrc_clk *clksrc_cdev[] = {
729         &clk_sclk_uclk,
730         &clk_sclk_mmc0,
731         &clk_sclk_mmc1,
732         &clk_sclk_mmc2,
733         &clk_sclk_spi0,
734         &clk_sclk_spi1,
735 };
736
737 static struct clk *clk_cdev[] = {
738         &clk_hsmmc0,
739         &clk_hsmmc1,
740         &clk_hsmmc2,
741         &clk_48m_spi0,
742         &clk_48m_spi1,
743 };
744
745 static struct clk_lookup s3c64xx_clk_lookup[] = {
746         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
747         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
748         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
749         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
750         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
751         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
752         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
753         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
759 };
760
761 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
762
763 void __init_or_cpufreq s3c64xx_setup_clocks(void)
764 {
765         struct clk *xtal_clk;
766         unsigned long xtal;
767         unsigned long fclk;
768         unsigned long hclk;
769         unsigned long hclk2;
770         unsigned long pclk;
771         unsigned long epll;
772         unsigned long apll;
773         unsigned long mpll;
774         unsigned int ptr;
775         u32 clkdiv0;
776
777         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
778
779         clkdiv0 = __raw_readl(S3C_CLK_DIV0);
780         printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
781
782         xtal_clk = clk_get(NULL, "xtal");
783         BUG_ON(IS_ERR(xtal_clk));
784
785         xtal = clk_get_rate(xtal_clk);
786         clk_put(xtal_clk);
787
788         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
789
790         /* For now assume the mux always selects the crystal */
791         clk_ext_xtal_mux.parent = xtal_clk;
792
793         epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
794                                 __raw_readl(S3C_EPLL_CON1));
795         mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
796         apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
797
798         fclk = mpll;
799
800         printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
801                apll, mpll, epll);
802
803         if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
804                 /* Synchronous mode */
805                 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
806         else
807                 /* Asynchronous mode */
808                 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
809
810         hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
811         pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
812
813         printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
814                hclk2, hclk, pclk);
815
816         clk_fout_mpll.rate = mpll;
817         clk_fout_epll.rate = epll;
818         clk_fout_apll.rate = apll;
819
820         clk_h2.rate = hclk2;
821         clk_h.rate = hclk;
822         clk_p.rate = pclk;
823         clk_f.rate = fclk;
824
825         for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
826                 s3c_set_clksrc(init_parents[ptr], true);
827
828         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
829                 s3c_set_clksrc(&clksrcs[ptr], true);
830 }
831
832 static struct clk *clks1[] __initdata = {
833         &clk_ext_xtal_mux,
834         &clk_iis_cd0,
835         &clk_iis_cd1,
836         &clk_iisv4_cd,
837         &clk_pcm_cd,
838         &clk_mout_epll.clk,
839         &clk_mout_mpll.clk,
840         &clk_dout_mpll,
841         &clk_arm,
842 };
843
844 static struct clk *clks[] __initdata = {
845         &clk_ext,
846         &clk_epll,
847         &clk_27m,
848         &clk_48m,
849         &clk_h2,
850         &clk_xusbxti,
851 };
852
853 /**
854  * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
855  * @xtal: The rate for the clock crystal feeding the PLLs.
856  * @armclk_divlimit: Divisor mask for ARMCLK.
857  *
858  * Register the clocks for the S3C6400 and S3C6410 SoC range, such
859  * as ARMCLK as well as the necessary parent clocks.
860  *
861  * This call does not setup the clocks, which is left to the
862  * s3c64xx_setup_clocks() call which may be needed by the cpufreq
863  * or resume code to re-set the clocks if the bootloader has changed
864  * them.
865  */
866 void __init s3c64xx_register_clocks(unsigned long xtal, 
867                                     unsigned armclk_divlimit)
868 {
869         unsigned int cnt;
870
871         armclk_mask = armclk_divlimit;
872
873         s3c24xx_register_baseclocks(xtal);
874         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
875
876         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
877
878         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
879         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
880
881         s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
882         for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
883                 s3c_disable_clocks(clk_cdev[cnt], 1);
884
885         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
886         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
887         for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
888                 s3c_register_clksrc(clksrc_cdev[cnt], 1);
889         clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
890
891         s3c_pwmclk_init();
892 }