Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
[linux-2.6.git] / arch / arm / mach-s3c2440 / mach-osiris.c
1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
2  *
3  * Copyright (c) 2005 Simtec Electronics
4  *      http://armlinux.simtec.co.uk/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19 #include <linux/sysdev.h>
20 #include <linux/serial_core.h>
21
22 #include <asm/mach/arch.h>
23 #include <asm/mach/map.h>
24 #include <asm/mach/irq.h>
25
26 #include <asm/arch/osiris-map.h>
27 #include <asm/arch/osiris-cpld.h>
28
29 #include <asm/hardware.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/mach-types.h>
33
34 #include <asm/plat-s3c/regs-serial.h>
35 #include <asm/arch/regs-gpio.h>
36 #include <asm/arch/regs-mem.h>
37 #include <asm/arch/regs-lcd.h>
38 #include <asm/plat-s3c/nand.h>
39
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/partitions.h>
44
45 #include <asm/plat-s3c24xx/clock.h>
46 #include <asm/plat-s3c24xx/devs.h>
47 #include <asm/plat-s3c24xx/cpu.h>
48
49 /* onboard perihperal map */
50
51 static struct map_desc osiris_iodesc[] __initdata = {
52   /* ISA IO areas (may be over-written later) */
53
54   {
55           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
56           .pfn          = __phys_to_pfn(S3C2410_CS5),
57           .length       = SZ_16M,
58           .type         = MT_DEVICE,
59   }, {
60           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
61           .pfn          = __phys_to_pfn(S3C2410_CS5),
62           .length       = SZ_16M,
63           .type         = MT_DEVICE,
64   },
65
66   /* CPLD control registers */
67
68   {
69           .virtual      = (u32)OSIRIS_VA_CTRL0,
70           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
71           .length       = SZ_16K,
72           .type         = MT_DEVICE,
73   }, {
74           .virtual      = (u32)OSIRIS_VA_CTRL1,
75           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
76           .length       = SZ_16K,
77           .type         = MT_DEVICE,
78   }, {
79           .virtual      = (u32)OSIRIS_VA_CTRL2,
80           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
81           .length       = SZ_16K,
82           .type         = MT_DEVICE,
83   }, {
84           .virtual      = (u32)OSIRIS_VA_IDREG,
85           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
86           .length       = SZ_16K,
87           .type         = MT_DEVICE,
88   },
89 };
90
91 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
92 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
93 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
94
95 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
96         [0] = {
97                 .name           = "uclk",
98                 .divisor        = 1,
99                 .min_baud       = 0,
100                 .max_baud       = 0,
101         },
102         [1] = {
103                 .name           = "pclk",
104                 .divisor        = 1,
105                 .min_baud       = 0,
106                 .max_baud       = 0,
107         }
108 };
109
110 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
111         [0] = {
112                 .hwport      = 0,
113                 .flags       = 0,
114                 .ucon        = UCON,
115                 .ulcon       = ULCON,
116                 .ufcon       = UFCON,
117                 .clocks      = osiris_serial_clocks,
118                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
119         },
120         [1] = {
121                 .hwport      = 1,
122                 .flags       = 0,
123                 .ucon        = UCON,
124                 .ulcon       = ULCON,
125                 .ufcon       = UFCON,
126                 .clocks      = osiris_serial_clocks,
127                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
128         },
129         [2] = {
130                 .hwport      = 2,
131                 .flags       = 0,
132                 .ucon        = UCON,
133                 .ulcon       = ULCON,
134                 .ufcon       = UFCON,
135                 .clocks      = osiris_serial_clocks,
136                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
137         }
138 };
139
140 /* NAND Flash on Osiris board */
141
142 static int external_map[]   = { 2 };
143 static int chip0_map[]      = { 0 };
144 static int chip1_map[]      = { 1 };
145
146 static struct mtd_partition osiris_default_nand_part[] = {
147         [0] = {
148                 .name   = "Boot Agent",
149                 .size   = SZ_16K,
150                 .offset = 0,
151         },
152         [1] = {
153                 .name   = "/boot",
154                 .size   = SZ_4M - SZ_16K,
155                 .offset = SZ_16K,
156         },
157         [2] = {
158                 .name   = "user1",
159                 .offset = SZ_4M,
160                 .size   = SZ_32M - SZ_4M,
161         },
162         [3] = {
163                 .name   = "user2",
164                 .offset = SZ_32M,
165                 .size   = MTDPART_SIZ_FULL,
166         }
167 };
168
169 static struct mtd_partition osiris_default_nand_part_large[] = {
170         [0] = {
171                 .name   = "Boot Agent",
172                 .size   = SZ_128K,
173                 .offset = 0,
174         },
175         [1] = {
176                 .name   = "/boot",
177                 .size   = SZ_4M - SZ_128K,
178                 .offset = SZ_128K,
179         },
180         [2] = {
181                 .name   = "user1",
182                 .offset = SZ_4M,
183                 .size   = SZ_32M - SZ_4M,
184         },
185         [3] = {
186                 .name   = "user2",
187                 .offset = SZ_32M,
188                 .size   = MTDPART_SIZ_FULL,
189         }
190 };
191
192 /* the Osiris has 3 selectable slots for nand-flash, the two
193  * on-board chip areas, as well as the external slot.
194  *
195  * Note, there is no current hot-plug support for the External
196  * socket.
197 */
198
199 static struct s3c2410_nand_set osiris_nand_sets[] = {
200         [1] = {
201                 .name           = "External",
202                 .nr_chips       = 1,
203                 .nr_map         = external_map,
204                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
205                 .partitions     = osiris_default_nand_part,
206         },
207         [0] = {
208                 .name           = "chip0",
209                 .nr_chips       = 1,
210                 .nr_map         = chip0_map,
211                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
212                 .partitions     = osiris_default_nand_part,
213         },
214         [2] = {
215                 .name           = "chip1",
216                 .nr_chips       = 1,
217                 .nr_map         = chip1_map,
218                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
219                 .partitions     = osiris_default_nand_part,
220         },
221 };
222
223 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
224 {
225         unsigned int tmp;
226
227         slot = set->nr_map[slot] & 3;
228
229         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
230                  slot, set, set->nr_map);
231
232         tmp = __raw_readb(OSIRIS_VA_CTRL0);
233         tmp &= ~OSIRIS_CTRL0_NANDSEL;
234         tmp |= slot;
235
236         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
237
238         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
239 }
240
241 static struct s3c2410_platform_nand osiris_nand_info = {
242         .tacls          = 25,
243         .twrph0         = 60,
244         .twrph1         = 60,
245         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
246         .sets           = osiris_nand_sets,
247         .select_chip    = osiris_nand_select,
248 };
249
250 /* PCMCIA control and configuration */
251
252 static struct resource osiris_pcmcia_resource[] = {
253         [0] = {
254                 .start  = 0x0f000000,
255                 .end    = 0x0f100000,
256                 .flags  = IORESOURCE_MEM,
257         },
258         [1] = {
259                 .start  = 0x0c000000,
260                 .end    = 0x0c100000,
261                 .flags  = IORESOURCE_MEM,
262         }
263 };
264
265 static struct platform_device osiris_pcmcia = {
266         .name           = "osiris-pcmcia",
267         .id             = -1,
268         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
269         .resource       = osiris_pcmcia_resource,
270 };
271
272 /* Osiris power management device */
273
274 #ifdef CONFIG_PM
275 static unsigned char pm_osiris_ctrl0;
276
277 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
278 {
279         unsigned int tmp;
280
281         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
282         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
283
284         /* ensure correct NAND slot is selected on resume */
285         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
286                 tmp |= 2;
287
288         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
289
290         /* ensure that an nRESET is not generated on resume. */
291         s3c2410_gpio_setpin(S3C2410_GPA21, 1);
292         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
293
294         return 0;
295 }
296
297 static int osiris_pm_resume(struct sys_device *sd)
298 {
299         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
300                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
301
302         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
303
304         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
305
306         return 0;
307 }
308
309 #else
310 #define osiris_pm_suspend NULL
311 #define osiris_pm_resume NULL
312 #endif
313
314 static struct sysdev_class osiris_pm_sysclass = {
315         set_kset_name("mach-osiris"),
316         .suspend        = osiris_pm_suspend,
317         .resume         = osiris_pm_resume,
318 };
319
320 static struct sys_device osiris_pm_sysdev = {
321         .cls            = &osiris_pm_sysclass,
322 };
323
324 /* Standard Osiris devices */
325
326 static struct platform_device *osiris_devices[] __initdata = {
327         &s3c_device_i2c,
328         &s3c_device_wdt,
329         &s3c_device_nand,
330         &osiris_pcmcia,
331 };
332
333 static struct clk *osiris_clocks[] = {
334         &s3c24xx_dclk0,
335         &s3c24xx_dclk1,
336         &s3c24xx_clkout0,
337         &s3c24xx_clkout1,
338         &s3c24xx_uclk,
339 };
340
341 static void __init osiris_map_io(void)
342 {
343         unsigned long flags;
344
345         /* initialise the clocks */
346
347         s3c24xx_dclk0.parent = NULL;
348         s3c24xx_dclk0.rate   = 12*1000*1000;
349
350         s3c24xx_dclk1.parent = NULL;
351         s3c24xx_dclk1.rate   = 24*1000*1000;
352
353         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
354         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
355
356         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
357
358         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
359
360         s3c_device_nand.dev.platform_data = &osiris_nand_info;
361
362         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
363         s3c24xx_init_clocks(0);
364         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
365
366         /* check for the newer revision boards with large page nand */
367
368         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
369                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
370                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
371                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
372                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
373         } else {
374                 /* write-protect line to the NAND */
375                 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
376         }
377
378         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
379
380         local_irq_save(flags);
381         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
382         local_irq_restore(flags);
383 }
384
385 static void __init osiris_init(void)
386 {
387         sysdev_class_register(&osiris_pm_sysclass);
388         sysdev_register(&osiris_pm_sysdev);
389
390         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
391 };
392
393 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
394         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
395         .phys_io        = S3C2410_PA_UART,
396         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
397         .boot_params    = S3C2410_SDRAM_PA + 0x100,
398         .map_io         = osiris_map_io,
399         .init_machine   = osiris_init,
400         .init_irq       = s3c24xx_init_irq,
401         .init_machine   = osiris_init,
402         .timer          = &s3c24xx_timer,
403 MACHINE_END