[ARM] 5396/1: RealView: Use PATA_PLATFORM to access the CompactFlash
[linux-2.6.git] / arch / arm / mach-realview / include / mach / board-pba8.h
1 /*
2  * include/asm-arm/arch-realview/board-pba8.h
3  *
4  * Copyright (C) 2008 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18  * MA 02110-1301, USA.
19  */
20
21 #ifndef __ASM_ARCH_BOARD_PBA8_H
22 #define __ASM_ARCH_BOARD_PBA8_H
23
24 #include <mach/platform.h>
25
26 /*
27  * Peripheral addresses
28  */
29 #define REALVIEW_PBA8_UART0_BASE                0x10009000      /* UART 0 */
30 #define REALVIEW_PBA8_UART1_BASE                0x1000A000      /* UART 1 */
31 #define REALVIEW_PBA8_UART2_BASE                0x1000B000      /* UART 2 */
32 #define REALVIEW_PBA8_UART3_BASE                0x1000C000      /* UART 3 */
33 #define REALVIEW_PBA8_SSP_BASE                  0x1000D000      /* Synchronous Serial Port */
34 #define REALVIEW_PBA8_WATCHDOG0_BASE            0x1000F000      /* Watchdog 0 */
35 #define REALVIEW_PBA8_WATCHDOG_BASE             0x10010000      /* watchdog interface */
36 #define REALVIEW_PBA8_TIMER0_1_BASE             0x10011000      /* Timer 0 and 1 */
37 #define REALVIEW_PBA8_TIMER2_3_BASE             0x10012000      /* Timer 2 and 3 */
38 #define REALVIEW_PBA8_GPIO0_BASE                0x10013000      /* GPIO port 0 */
39 #define REALVIEW_PBA8_RTC_BASE                  0x10017000      /* Real Time Clock */
40 #define REALVIEW_PBA8_TIMER4_5_BASE             0x10018000      /* Timer 4/5 */
41 #define REALVIEW_PBA8_TIMER6_7_BASE             0x10019000      /* Timer 6/7 */
42 #define REALVIEW_PBA8_SCTL_BASE                 0x1001A000      /* System Controller */
43 #define REALVIEW_PBA8_CLCD_BASE                 0x10020000      /* CLCD */
44 #define REALVIEW_PBA8_ONB_SRAM_BASE             0x10060000      /* On-board SRAM */
45 #define REALVIEW_PBA8_DMC_BASE                  0x100E0000      /* DMC configuration */
46 #define REALVIEW_PBA8_SMC_BASE                  0x100E1000      /* SMC configuration */
47 #define REALVIEW_PBA8_CAN_BASE                  0x100E2000      /* CAN bus */
48 #define REALVIEW_PBA8_GIC_CPU_BASE              0x1E000000      /* Generic interrupt controller CPU interface */
49 #define REALVIEW_PBA8_FLASH0_BASE               0x40000000
50 #define REALVIEW_PBA8_FLASH0_SIZE               SZ_64M
51 #define REALVIEW_PBA8_FLASH1_BASE               0x44000000
52 #define REALVIEW_PBA8_FLASH1_SIZE               SZ_64M
53 #define REALVIEW_PBA8_ETH_BASE                  0x4E000000      /* Ethernet */
54 #define REALVIEW_PBA8_USB_BASE                  0x4F000000      /* USB */
55 #define REALVIEW_PBA8_GIC_DIST_BASE             0x1E001000      /* Generic interrupt controller distributor */
56 #define REALVIEW_PBA8_LT_BASE                   0xC0000000      /* Logic Tile expansion */
57 #define REALVIEW_PBA8_SDRAM6_BASE               0x70000000      /* SDRAM bank 6 256MB */
58 #define REALVIEW_PBA8_SDRAM7_BASE               0x80000000      /* SDRAM bank 7 256MB */
59
60 #define REALVIEW_PBA8_SYS_PLD_CTRL1             0x74
61
62 /*
63  * PBA8 PCI regions
64  */
65 #define REALVIEW_PBA8_PCI_BASE                  0x90040000      /* PCI-X Unit base */
66 #define REALVIEW_PBA8_PCI_IO_BASE               0x90050000      /* IO Region on AHB */
67 #define REALVIEW_PBA8_PCI_MEM_BASE              0xA0000000      /* MEM Region on AHB */
68
69 #define REALVIEW_PBA8_PCI_BASE_SIZE             0x10000         /* 16 Kb */
70 #define REALVIEW_PBA8_PCI_IO_SIZE               0x1000          /* 4 Kb */
71 #define REALVIEW_PBA8_PCI_MEM_SIZE              0x20000000      /* 512 MB */
72
73 /*
74  * Irqs
75  */
76 #define IRQ_PBA8_GIC_START                      32
77
78 /* L220
79 #define IRQ_PBA8_L220_EVENT     (IRQ_PBA8_GIC_START + 29)
80 #define IRQ_PBA8_L220_SLAVE     (IRQ_PBA8_GIC_START + 30)
81 #define IRQ_PBA8_L220_DECODE    (IRQ_PBA8_GIC_START + 31)
82 */
83
84 /*
85  * PB-A8 on-board gic irq sources
86  */
87 #define IRQ_PBA8_WATCHDOG       (IRQ_PBA8_GIC_START + 0)        /* Watchdog timer */
88 #define IRQ_PBA8_SOFT           (IRQ_PBA8_GIC_START + 1)        /* Software interrupt */
89 #define IRQ_PBA8_COMMRx         (IRQ_PBA8_GIC_START + 2)        /* Debug Comm Rx interrupt */
90 #define IRQ_PBA8_COMMTx         (IRQ_PBA8_GIC_START + 3)        /* Debug Comm Tx interrupt */
91 #define IRQ_PBA8_TIMER0_1       (IRQ_PBA8_GIC_START + 4)        /* Timer 0/1 (default timer) */
92 #define IRQ_PBA8_TIMER2_3       (IRQ_PBA8_GIC_START + 5)        /* Timer 2/3 */
93 #define IRQ_PBA8_GPIO0          (IRQ_PBA8_GIC_START + 6)        /* GPIO 0 */
94 #define IRQ_PBA8_GPIO1          (IRQ_PBA8_GIC_START + 7)        /* GPIO 1 */
95 #define IRQ_PBA8_GPIO2          (IRQ_PBA8_GIC_START + 8)        /* GPIO 2 */
96                                                                 /* 9 reserved */
97 #define IRQ_PBA8_RTC            (IRQ_PBA8_GIC_START + 10)       /* Real Time Clock */
98 #define IRQ_PBA8_SSP            (IRQ_PBA8_GIC_START + 11)       /* Synchronous Serial Port */
99 #define IRQ_PBA8_UART0          (IRQ_PBA8_GIC_START + 12)       /* UART 0 on development chip */
100 #define IRQ_PBA8_UART1          (IRQ_PBA8_GIC_START + 13)       /* UART 1 on development chip */
101 #define IRQ_PBA8_UART2          (IRQ_PBA8_GIC_START + 14)       /* UART 2 on development chip */
102 #define IRQ_PBA8_UART3          (IRQ_PBA8_GIC_START + 15)       /* UART 3 on development chip */
103 #define IRQ_PBA8_SCI            (IRQ_PBA8_GIC_START + 16)       /* Smart Card Interface */
104 #define IRQ_PBA8_MMCI0A         (IRQ_PBA8_GIC_START + 17)       /* Multimedia Card 0A */
105 #define IRQ_PBA8_MMCI0B         (IRQ_PBA8_GIC_START + 18)       /* Multimedia Card 0B */
106 #define IRQ_PBA8_AACI           (IRQ_PBA8_GIC_START + 19)       /* Audio Codec */
107 #define IRQ_PBA8_KMI0           (IRQ_PBA8_GIC_START + 20)       /* Keyboard/Mouse port 0 */
108 #define IRQ_PBA8_KMI1           (IRQ_PBA8_GIC_START + 21)       /* Keyboard/Mouse port 1 */
109 #define IRQ_PBA8_CHARLCD        (IRQ_PBA8_GIC_START + 22)       /* Character LCD */
110 #define IRQ_PBA8_CLCD           (IRQ_PBA8_GIC_START + 23)       /* CLCD controller */
111 #define IRQ_PBA8_DMAC           (IRQ_PBA8_GIC_START + 24)       /* DMA controller */
112 #define IRQ_PBA8_PWRFAIL        (IRQ_PBA8_GIC_START + 25)       /* Power failure */
113 #define IRQ_PBA8_PISMO          (IRQ_PBA8_GIC_START + 26)       /* PISMO interface */
114 #define IRQ_PBA8_DoC            (IRQ_PBA8_GIC_START + 27)       /* Disk on Chip memory controller */
115 #define IRQ_PBA8_ETH            (IRQ_PBA8_GIC_START + 28)       /* Ethernet controller */
116 #define IRQ_PBA8_USB            (IRQ_PBA8_GIC_START + 29)       /* USB controller */
117 #define IRQ_PBA8_TSPEN          (IRQ_PBA8_GIC_START + 30)       /* Touchscreen pen */
118 #define IRQ_PBA8_TSKPAD         (IRQ_PBA8_GIC_START + 31)       /* Touchscreen keypad */
119
120 /* ... */
121 #define IRQ_PBA8_PCI0           (IRQ_PBA8_GIC_START + 50)
122 #define IRQ_PBA8_PCI1           (IRQ_PBA8_GIC_START + 51)
123 #define IRQ_PBA8_PCI2           (IRQ_PBA8_GIC_START + 52)
124 #define IRQ_PBA8_PCI3           (IRQ_PBA8_GIC_START + 53)
125
126 #define IRQ_PBA8_SMC            -1
127 #define IRQ_PBA8_SCTL           -1
128
129 #define NR_GIC_PBA8             1
130
131 /*
132  * Only define NR_IRQS if less than NR_IRQS_PBA8
133  */
134 #define NR_IRQS_PBA8            (IRQ_PBA8_GIC_START + 64)
135
136 #if defined(CONFIG_MACH_REALVIEW_PBA8)
137
138 #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8)
139 #undef NR_IRQS
140 #define NR_IRQS                 NR_IRQS_PBA8
141 #endif
142
143 #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8)
144 #undef MAX_GIC_NR
145 #define MAX_GIC_NR              NR_GIC_PBA8
146 #endif
147
148 #endif  /* CONFIG_MACH_REALVIEW_PBA8 */
149
150 #endif  /* __ASM_ARCH_BOARD_PBA8_H */