ARM: 5720/1: Move MMCI header to amba include dir
[linux-2.6.git] / arch / arm / mach-realview / core.c
1 /*
2  *  linux/arch/arm/mach-realview/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
30 #include <linux/io.h>
31 #include <linux/smsc911x.h>
32 #include <linux/ata_platform.h>
33 #include <linux/amba/mmci.h>
34
35 #include <asm/clkdev.h>
36 #include <asm/system.h>
37 #include <mach/hardware.h>
38 #include <asm/irq.h>
39 #include <asm/leds.h>
40 #include <asm/mach-types.h>
41 #include <asm/hardware/arm_timer.h>
42 #include <asm/hardware/icst307.h>
43
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/map.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include <mach/platform.h>
52 #include <mach/irqs.h>
53
54 #include "core.h"
55 #include "clock.h"
56
57 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
58
59 /* used by entry-macro.S and platsmp.c */
60 void __iomem *gic_cpu_base_addr;
61
62 /*
63  * This is the RealView sched_clock implementation.  This has
64  * a resolution of 41.7ns, and a maximum value of about 179s.
65  */
66 unsigned long long sched_clock(void)
67 {
68         unsigned long long v;
69
70         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
71         do_div(v, 3);
72
73         return v;
74 }
75
76
77 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
78
79 static int realview_flash_init(void)
80 {
81         u32 val;
82
83         val = __raw_readl(REALVIEW_FLASHCTRL);
84         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
85         __raw_writel(val, REALVIEW_FLASHCTRL);
86
87         return 0;
88 }
89
90 static void realview_flash_exit(void)
91 {
92         u32 val;
93
94         val = __raw_readl(REALVIEW_FLASHCTRL);
95         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
96         __raw_writel(val, REALVIEW_FLASHCTRL);
97 }
98
99 static void realview_flash_set_vpp(int on)
100 {
101         u32 val;
102
103         val = __raw_readl(REALVIEW_FLASHCTRL);
104         if (on)
105                 val |= REALVIEW_FLASHPROG_FLVPPEN;
106         else
107                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
108         __raw_writel(val, REALVIEW_FLASHCTRL);
109 }
110
111 static struct flash_platform_data realview_flash_data = {
112         .map_name               = "cfi_probe",
113         .width                  = 4,
114         .init                   = realview_flash_init,
115         .exit                   = realview_flash_exit,
116         .set_vpp                = realview_flash_set_vpp,
117 };
118
119 struct platform_device realview_flash_device = {
120         .name                   = "armflash",
121         .id                     = 0,
122         .dev                    = {
123                 .platform_data  = &realview_flash_data,
124         },
125 };
126
127 int realview_flash_register(struct resource *res, u32 num)
128 {
129         realview_flash_device.resource = res;
130         realview_flash_device.num_resources = num;
131         return platform_device_register(&realview_flash_device);
132 }
133
134 static struct smsc911x_platform_config smsc911x_config = {
135         .flags          = SMSC911X_USE_32BIT,
136         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
137         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
138         .phy_interface  = PHY_INTERFACE_MODE_MII,
139 };
140
141 static struct platform_device realview_eth_device = {
142         .name           = "smsc911x",
143         .id             = 0,
144         .num_resources  = 2,
145 };
146
147 int realview_eth_register(const char *name, struct resource *res)
148 {
149         if (name)
150                 realview_eth_device.name = name;
151         realview_eth_device.resource = res;
152         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
153                 realview_eth_device.dev.platform_data = &smsc911x_config;
154
155         return platform_device_register(&realview_eth_device);
156 }
157
158 struct platform_device realview_usb_device = {
159         .name                   = "isp1760",
160         .num_resources          = 2,
161 };
162
163 int realview_usb_register(struct resource *res)
164 {
165         realview_usb_device.resource = res;
166         return platform_device_register(&realview_usb_device);
167 }
168
169 static struct pata_platform_info pata_platform_data = {
170         .ioport_shift           = 1,
171 };
172
173 static struct resource pata_resources[] = {
174         [0] = {
175                 .start          = REALVIEW_CF_BASE,
176                 .end            = REALVIEW_CF_BASE + 0xff,
177                 .flags          = IORESOURCE_MEM,
178         },
179         [1] = {
180                 .start          = REALVIEW_CF_BASE + 0x100,
181                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
182                 .flags          = IORESOURCE_MEM,
183         },
184 };
185
186 struct platform_device realview_cf_device = {
187         .name                   = "pata_platform",
188         .id                     = -1,
189         .num_resources          = ARRAY_SIZE(pata_resources),
190         .resource               = pata_resources,
191         .dev                    = {
192                 .platform_data  = &pata_platform_data,
193         },
194 };
195
196 static struct resource realview_i2c_resource = {
197         .start          = REALVIEW_I2C_BASE,
198         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
199         .flags          = IORESOURCE_MEM,
200 };
201
202 struct platform_device realview_i2c_device = {
203         .name           = "versatile-i2c",
204         .id             = 0,
205         .num_resources  = 1,
206         .resource       = &realview_i2c_resource,
207 };
208
209 static struct i2c_board_info realview_i2c_board_info[] = {
210         {
211                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
212         },
213 };
214
215 static int __init realview_i2c_init(void)
216 {
217         return i2c_register_board_info(0, realview_i2c_board_info,
218                                        ARRAY_SIZE(realview_i2c_board_info));
219 }
220 arch_initcall(realview_i2c_init);
221
222 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
223
224 /*
225  * This is only used if GPIOLIB support is disabled
226  */
227 static unsigned int realview_mmc_status(struct device *dev)
228 {
229         struct amba_device *adev = container_of(dev, struct amba_device, dev);
230         u32 mask;
231
232         if (adev->res.start == REALVIEW_MMCI0_BASE)
233                 mask = 1;
234         else
235                 mask = 2;
236
237         return readl(REALVIEW_SYSMCI) & mask;
238 }
239
240 struct mmci_platform_data realview_mmc0_plat_data = {
241         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
242         .status         = realview_mmc_status,
243         .gpio_wp        = 17,
244         .gpio_cd        = 16,
245 };
246
247 struct mmci_platform_data realview_mmc1_plat_data = {
248         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
249         .status         = realview_mmc_status,
250         .gpio_wp        = 19,
251         .gpio_cd        = 18,
252 };
253
254 /*
255  * Clock handling
256  */
257 static const struct icst307_params realview_oscvco_params = {
258         .ref            = 24000,
259         .vco_max        = 200000,
260         .vd_min         = 4 + 8,
261         .vd_max         = 511 + 8,
262         .rd_min         = 1 + 2,
263         .rd_max         = 127 + 2,
264 };
265
266 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
267 {
268         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
269         void __iomem *sys_osc;
270         u32 val;
271
272         if (machine_is_realview_pb1176())
273                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
274         else
275                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
276
277         val = readl(sys_osc) & ~0x7ffff;
278         val |= vco.v | (vco.r << 9) | (vco.s << 16);
279
280         writel(0xa05f, sys_lock);
281         writel(val, sys_osc);
282         writel(0, sys_lock);
283 }
284
285 static struct clk oscvco_clk = {
286         .params = &realview_oscvco_params,
287         .setvco = realview_oscvco_set,
288 };
289
290 /*
291  * These are fixed clocks.
292  */
293 static struct clk ref24_clk = {
294         .rate   = 24000000,
295 };
296
297 static struct clk_lookup lookups[] = {
298         {       /* UART0 */
299                 .dev_id         = "dev:uart0",
300                 .clk            = &ref24_clk,
301         }, {    /* UART1 */
302                 .dev_id         = "dev:uart1",
303                 .clk            = &ref24_clk,
304         }, {    /* UART2 */
305                 .dev_id         = "dev:uart2",
306                 .clk            = &ref24_clk,
307         }, {    /* UART3 */
308                 .dev_id         = "fpga:uart3",
309                 .clk            = &ref24_clk,
310         }, {    /* KMI0 */
311                 .dev_id         = "fpga:kmi0",
312                 .clk            = &ref24_clk,
313         }, {    /* KMI1 */
314                 .dev_id         = "fpga:kmi1",
315                 .clk            = &ref24_clk,
316         }, {    /* MMC0 */
317                 .dev_id         = "fpga:mmc0",
318                 .clk            = &ref24_clk,
319         }, {    /* EB:CLCD */
320                 .dev_id         = "dev:clcd",
321                 .clk            = &oscvco_clk,
322         }, {    /* PB:CLCD */
323                 .dev_id         = "issp:clcd",
324                 .clk            = &oscvco_clk,
325         }
326 };
327
328 static int __init clk_init(void)
329 {
330         int i;
331
332         for (i = 0; i < ARRAY_SIZE(lookups); i++)
333                 clkdev_add(&lookups[i]);
334         return 0;
335 }
336 arch_initcall(clk_init);
337
338 /*
339  * CLCD support.
340  */
341 #define SYS_CLCD_NLCDIOON       (1 << 2)
342 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
343 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
344 #define SYS_CLCD_ID_MASK        (0x1f << 8)
345 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
346 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
347 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
348 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
349 #define SYS_CLCD_ID_VGA         (0x1f << 8)
350
351 static struct clcd_panel vga = {
352         .mode           = {
353                 .name           = "VGA",
354                 .refresh        = 60,
355                 .xres           = 640,
356                 .yres           = 480,
357                 .pixclock       = 39721,
358                 .left_margin    = 40,
359                 .right_margin   = 24,
360                 .upper_margin   = 32,
361                 .lower_margin   = 11,
362                 .hsync_len      = 96,
363                 .vsync_len      = 2,
364                 .sync           = 0,
365                 .vmode          = FB_VMODE_NONINTERLACED,
366         },
367         .width          = -1,
368         .height         = -1,
369         .tim2           = TIM2_BCD | TIM2_IPC,
370         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
371         .bpp            = 16,
372 };
373
374 static struct clcd_panel xvga = {
375         .mode           = {
376                 .name           = "XVGA",
377                 .refresh        = 60,
378                 .xres           = 1024,
379                 .yres           = 768,
380                 .pixclock       = 15748,
381                 .left_margin    = 152,
382                 .right_margin   = 48,
383                 .upper_margin   = 23,
384                 .lower_margin   = 3,
385                 .hsync_len      = 104,
386                 .vsync_len      = 4,
387                 .sync           = 0,
388                 .vmode          = FB_VMODE_NONINTERLACED,
389         },
390         .width          = -1,
391         .height         = -1,
392         .tim2           = TIM2_BCD | TIM2_IPC,
393         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
394         .bpp            = 16,
395 };
396
397 static struct clcd_panel sanyo_3_8_in = {
398         .mode           = {
399                 .name           = "Sanyo QVGA",
400                 .refresh        = 116,
401                 .xres           = 320,
402                 .yres           = 240,
403                 .pixclock       = 100000,
404                 .left_margin    = 6,
405                 .right_margin   = 6,
406                 .upper_margin   = 5,
407                 .lower_margin   = 5,
408                 .hsync_len      = 6,
409                 .vsync_len      = 6,
410                 .sync           = 0,
411                 .vmode          = FB_VMODE_NONINTERLACED,
412         },
413         .width          = -1,
414         .height         = -1,
415         .tim2           = TIM2_BCD,
416         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
417         .bpp            = 16,
418 };
419
420 static struct clcd_panel sanyo_2_5_in = {
421         .mode           = {
422                 .name           = "Sanyo QVGA Portrait",
423                 .refresh        = 116,
424                 .xres           = 240,
425                 .yres           = 320,
426                 .pixclock       = 100000,
427                 .left_margin    = 20,
428                 .right_margin   = 10,
429                 .upper_margin   = 2,
430                 .lower_margin   = 2,
431                 .hsync_len      = 10,
432                 .vsync_len      = 2,
433                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
434                 .vmode          = FB_VMODE_NONINTERLACED,
435         },
436         .width          = -1,
437         .height         = -1,
438         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
439         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
440         .bpp            = 16,
441 };
442
443 static struct clcd_panel epson_2_2_in = {
444         .mode           = {
445                 .name           = "Epson QCIF",
446                 .refresh        = 390,
447                 .xres           = 176,
448                 .yres           = 220,
449                 .pixclock       = 62500,
450                 .left_margin    = 3,
451                 .right_margin   = 2,
452                 .upper_margin   = 1,
453                 .lower_margin   = 0,
454                 .hsync_len      = 3,
455                 .vsync_len      = 2,
456                 .sync           = 0,
457                 .vmode          = FB_VMODE_NONINTERLACED,
458         },
459         .width          = -1,
460         .height         = -1,
461         .tim2           = TIM2_BCD | TIM2_IPC,
462         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
463         .bpp            = 16,
464 };
465
466 /*
467  * Detect which LCD panel is connected, and return the appropriate
468  * clcd_panel structure.  Note: we do not have any information on
469  * the required timings for the 8.4in panel, so we presently assume
470  * VGA timings.
471  */
472 static struct clcd_panel *realview_clcd_panel(void)
473 {
474         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
475         struct clcd_panel *vga_panel;
476         struct clcd_panel *panel;
477         u32 val;
478
479         if (machine_is_realview_eb())
480                 vga_panel = &vga;
481         else
482                 vga_panel = &xvga;
483
484         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
485         if (val == SYS_CLCD_ID_SANYO_3_8)
486                 panel = &sanyo_3_8_in;
487         else if (val == SYS_CLCD_ID_SANYO_2_5)
488                 panel = &sanyo_2_5_in;
489         else if (val == SYS_CLCD_ID_EPSON_2_2)
490                 panel = &epson_2_2_in;
491         else if (val == SYS_CLCD_ID_VGA)
492                 panel = vga_panel;
493         else {
494                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
495                         val);
496                 panel = vga_panel;
497         }
498
499         return panel;
500 }
501
502 /*
503  * Disable all display connectors on the interface module.
504  */
505 static void realview_clcd_disable(struct clcd_fb *fb)
506 {
507         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
508         u32 val;
509
510         val = readl(sys_clcd);
511         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
512         writel(val, sys_clcd);
513 }
514
515 /*
516  * Enable the relevant connector on the interface module.
517  */
518 static void realview_clcd_enable(struct clcd_fb *fb)
519 {
520         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
521         u32 val;
522
523         /*
524          * Enable the PSUs
525          */
526         val = readl(sys_clcd);
527         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
528         writel(val, sys_clcd);
529 }
530
531 static int realview_clcd_setup(struct clcd_fb *fb)
532 {
533         unsigned long framesize;
534         dma_addr_t dma;
535
536         if (machine_is_realview_eb())
537                 /* VGA, 16bpp */
538                 framesize = 640 * 480 * 2;
539         else
540                 /* XVGA, 16bpp */
541                 framesize = 1024 * 768 * 2;
542
543         fb->panel               = realview_clcd_panel();
544
545         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
546                                                     &dma, GFP_KERNEL);
547         if (!fb->fb.screen_base) {
548                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
549                 return -ENOMEM;
550         }
551
552         fb->fb.fix.smem_start   = dma;
553         fb->fb.fix.smem_len     = framesize;
554
555         return 0;
556 }
557
558 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
559 {
560         return dma_mmap_writecombine(&fb->dev->dev, vma,
561                                      fb->fb.screen_base,
562                                      fb->fb.fix.smem_start,
563                                      fb->fb.fix.smem_len);
564 }
565
566 static void realview_clcd_remove(struct clcd_fb *fb)
567 {
568         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
569                               fb->fb.screen_base, fb->fb.fix.smem_start);
570 }
571
572 struct clcd_board clcd_plat_data = {
573         .name           = "RealView",
574         .check          = clcdfb_check,
575         .decode         = clcdfb_decode,
576         .disable        = realview_clcd_disable,
577         .enable         = realview_clcd_enable,
578         .setup          = realview_clcd_setup,
579         .mmap           = realview_clcd_mmap,
580         .remove         = realview_clcd_remove,
581 };
582
583 #ifdef CONFIG_LEDS
584 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
585
586 void realview_leds_event(led_event_t ledevt)
587 {
588         unsigned long flags;
589         u32 val;
590         u32 led = 1 << smp_processor_id();
591
592         local_irq_save(flags);
593         val = readl(VA_LEDS_BASE);
594
595         switch (ledevt) {
596         case led_idle_start:
597                 val = val & ~led;
598                 break;
599
600         case led_idle_end:
601                 val = val | led;
602                 break;
603
604         case led_timer:
605                 val = val ^ REALVIEW_SYS_LED7;
606                 break;
607
608         case led_halted:
609                 val = 0;
610                 break;
611
612         default:
613                 break;
614         }
615
616         writel(val, VA_LEDS_BASE);
617         local_irq_restore(flags);
618 }
619 #endif  /* CONFIG_LEDS */
620
621 /*
622  * Where is the timer (VA)?
623  */
624 void __iomem *timer0_va_base;
625 void __iomem *timer1_va_base;
626 void __iomem *timer2_va_base;
627 void __iomem *timer3_va_base;
628
629 /*
630  * How long is the timer interval?
631  */
632 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
633 #if TIMER_INTERVAL >= 0x100000
634 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
635 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
636 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
637 #elif TIMER_INTERVAL >= 0x10000
638 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
639 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
640 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
641 #else
642 #define TIMER_RELOAD    (TIMER_INTERVAL)
643 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
644 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
645 #endif
646
647 static void timer_set_mode(enum clock_event_mode mode,
648                            struct clock_event_device *clk)
649 {
650         unsigned long ctrl;
651
652         switch(mode) {
653         case CLOCK_EVT_MODE_PERIODIC:
654                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
655
656                 ctrl = TIMER_CTRL_PERIODIC;
657                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
658                 break;
659         case CLOCK_EVT_MODE_ONESHOT:
660                 /* period set, and timer enabled in 'next_event' hook */
661                 ctrl = TIMER_CTRL_ONESHOT;
662                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
663                 break;
664         case CLOCK_EVT_MODE_UNUSED:
665         case CLOCK_EVT_MODE_SHUTDOWN:
666         default:
667                 ctrl = 0;
668         }
669
670         writel(ctrl, timer0_va_base + TIMER_CTRL);
671 }
672
673 static int timer_set_next_event(unsigned long evt,
674                                 struct clock_event_device *unused)
675 {
676         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
677
678         writel(evt, timer0_va_base + TIMER_LOAD);
679         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
680
681         return 0;
682 }
683
684 static struct clock_event_device timer0_clockevent =     {
685         .name           = "timer0",
686         .shift          = 32,
687         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
688         .set_mode       = timer_set_mode,
689         .set_next_event = timer_set_next_event,
690         .rating         = 300,
691         .cpumask        = cpu_all_mask,
692 };
693
694 static void __init realview_clockevents_init(unsigned int timer_irq)
695 {
696         timer0_clockevent.irq = timer_irq;
697         timer0_clockevent.mult =
698                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
699         timer0_clockevent.max_delta_ns =
700                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
701         timer0_clockevent.min_delta_ns =
702                 clockevent_delta2ns(0xf, &timer0_clockevent);
703
704         clockevents_register_device(&timer0_clockevent);
705 }
706
707 /*
708  * IRQ handler for the timer
709  */
710 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
711 {
712         struct clock_event_device *evt = &timer0_clockevent;
713
714         /* clear the interrupt */
715         writel(1, timer0_va_base + TIMER_INTCLR);
716
717         evt->event_handler(evt);
718
719         return IRQ_HANDLED;
720 }
721
722 static struct irqaction realview_timer_irq = {
723         .name           = "RealView Timer Tick",
724         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
725         .handler        = realview_timer_interrupt,
726 };
727
728 static cycle_t realview_get_cycles(struct clocksource *cs)
729 {
730         return ~readl(timer3_va_base + TIMER_VALUE);
731 }
732
733 static struct clocksource clocksource_realview = {
734         .name   = "timer3",
735         .rating = 200,
736         .read   = realview_get_cycles,
737         .mask   = CLOCKSOURCE_MASK(32),
738         .shift  = 20,
739         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
740 };
741
742 static void __init realview_clocksource_init(void)
743 {
744         /* setup timer 0 as free-running clocksource */
745         writel(0, timer3_va_base + TIMER_CTRL);
746         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
747         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
748         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
749                 timer3_va_base + TIMER_CTRL);
750
751         clocksource_realview.mult =
752                 clocksource_khz2mult(1000, clocksource_realview.shift);
753         clocksource_register(&clocksource_realview);
754 }
755
756 /*
757  * Set up the clock source and clock events devices
758  */
759 void __init realview_timer_init(unsigned int timer_irq)
760 {
761         u32 val;
762
763         /* 
764          * set clock frequency: 
765          *      REALVIEW_REFCLK is 32KHz
766          *      REALVIEW_TIMCLK is 1MHz
767          */
768         val = readl(__io_address(REALVIEW_SCTL_BASE));
769         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
770                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
771                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
772                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
773                __io_address(REALVIEW_SCTL_BASE));
774
775         /*
776          * Initialise to a known state (all timers off)
777          */
778         writel(0, timer0_va_base + TIMER_CTRL);
779         writel(0, timer1_va_base + TIMER_CTRL);
780         writel(0, timer2_va_base + TIMER_CTRL);
781         writel(0, timer3_va_base + TIMER_CTRL);
782
783         /* 
784          * Make irqs happen for the system timer
785          */
786         setup_irq(timer_irq, &realview_timer_irq);
787
788         realview_clocksource_init();
789         realview_clockevents_init(timer_irq);
790 }