[ARM] 5396/1: RealView: Use PATA_PLATFORM to access the CompactFlash
[linux-2.6.git] / arch / arm / mach-realview / core.c
1 /*
2  *  linux/arch/arm/mach-realview/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
30 #include <linux/io.h>
31 #include <linux/smc911x.h>
32 #include <linux/ata_platform.h>
33
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst307.h>
42
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/mmc.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include "core.h"
52 #include "clock.h"
53
54 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
55
56 /* used by entry-macro.S and platsmp.c */
57 void __iomem *gic_cpu_base_addr;
58
59 /*
60  * This is the RealView sched_clock implementation.  This has
61  * a resolution of 41.7ns, and a maximum value of about 179s.
62  */
63 unsigned long long sched_clock(void)
64 {
65         unsigned long long v;
66
67         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
68         do_div(v, 3);
69
70         return v;
71 }
72
73
74 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
75
76 static int realview_flash_init(void)
77 {
78         u32 val;
79
80         val = __raw_readl(REALVIEW_FLASHCTRL);
81         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
82         __raw_writel(val, REALVIEW_FLASHCTRL);
83
84         return 0;
85 }
86
87 static void realview_flash_exit(void)
88 {
89         u32 val;
90
91         val = __raw_readl(REALVIEW_FLASHCTRL);
92         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
93         __raw_writel(val, REALVIEW_FLASHCTRL);
94 }
95
96 static void realview_flash_set_vpp(int on)
97 {
98         u32 val;
99
100         val = __raw_readl(REALVIEW_FLASHCTRL);
101         if (on)
102                 val |= REALVIEW_FLASHPROG_FLVPPEN;
103         else
104                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
105         __raw_writel(val, REALVIEW_FLASHCTRL);
106 }
107
108 static struct flash_platform_data realview_flash_data = {
109         .map_name               = "cfi_probe",
110         .width                  = 4,
111         .init                   = realview_flash_init,
112         .exit                   = realview_flash_exit,
113         .set_vpp                = realview_flash_set_vpp,
114 };
115
116 struct platform_device realview_flash_device = {
117         .name                   = "armflash",
118         .id                     = 0,
119         .dev                    = {
120                 .platform_data  = &realview_flash_data,
121         },
122 };
123
124 int realview_flash_register(struct resource *res, u32 num)
125 {
126         realview_flash_device.resource = res;
127         realview_flash_device.num_resources = num;
128         return platform_device_register(&realview_flash_device);
129 }
130
131 static struct smc911x_platdata realview_smc911x_platdata = {
132         .flags          = SMC911X_USE_32BIT,
133         .irq_flags      = IRQF_SHARED,
134         .irq_polarity   = 1,
135 };
136
137 static struct platform_device realview_eth_device = {
138         .name           = "smc911x",
139         .id             = 0,
140         .num_resources  = 2,
141 };
142
143 int realview_eth_register(const char *name, struct resource *res)
144 {
145         if (name)
146                 realview_eth_device.name = name;
147         realview_eth_device.resource = res;
148         if (strcmp(realview_eth_device.name, "smc911x") == 0)
149                 realview_eth_device.dev.platform_data = &realview_smc911x_platdata;
150
151         return platform_device_register(&realview_eth_device);
152 }
153
154 static struct pata_platform_info pata_platform_data = {
155         .ioport_shift           = 1,
156 };
157
158 static struct resource pata_resources[] = {
159         [0] = {
160                 .start          = REALVIEW_CF_BASE,
161                 .end            = REALVIEW_CF_BASE + 0xff,
162                 .flags          = IORESOURCE_MEM,
163         },
164         [1] = {
165                 .start          = REALVIEW_CF_BASE + 0x100,
166                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
167                 .flags          = IORESOURCE_MEM,
168         },
169 };
170
171 struct platform_device realview_cf_device = {
172         .name                   = "pata_platform",
173         .id                     = -1,
174         .num_resources          = ARRAY_SIZE(pata_resources),
175         .resource               = pata_resources,
176         .dev                    = {
177                 .platform_data  = &pata_platform_data,
178         },
179 };
180
181 static struct resource realview_i2c_resource = {
182         .start          = REALVIEW_I2C_BASE,
183         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
184         .flags          = IORESOURCE_MEM,
185 };
186
187 struct platform_device realview_i2c_device = {
188         .name           = "versatile-i2c",
189         .id             = 0,
190         .num_resources  = 1,
191         .resource       = &realview_i2c_resource,
192 };
193
194 static struct i2c_board_info realview_i2c_board_info[] = {
195         {
196                 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
197                 .type = "ds1338",
198         },
199 };
200
201 static int __init realview_i2c_init(void)
202 {
203         return i2c_register_board_info(0, realview_i2c_board_info,
204                                        ARRAY_SIZE(realview_i2c_board_info));
205 }
206 arch_initcall(realview_i2c_init);
207
208 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
209
210 static unsigned int realview_mmc_status(struct device *dev)
211 {
212         struct amba_device *adev = container_of(dev, struct amba_device, dev);
213         u32 mask;
214
215         if (adev->res.start == REALVIEW_MMCI0_BASE)
216                 mask = 1;
217         else
218                 mask = 2;
219
220         return readl(REALVIEW_SYSMCI) & mask;
221 }
222
223 struct mmc_platform_data realview_mmc0_plat_data = {
224         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
225         .status         = realview_mmc_status,
226 };
227
228 struct mmc_platform_data realview_mmc1_plat_data = {
229         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
230         .status         = realview_mmc_status,
231 };
232
233 /*
234  * Clock handling
235  */
236 static const struct icst307_params realview_oscvco_params = {
237         .ref            = 24000,
238         .vco_max        = 200000,
239         .vd_min         = 4 + 8,
240         .vd_max         = 511 + 8,
241         .rd_min         = 1 + 2,
242         .rd_max         = 127 + 2,
243 };
244
245 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
246 {
247         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
248         void __iomem *sys_osc;
249         u32 val;
250
251         if (machine_is_realview_pb1176())
252                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
253         else
254                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
255
256         val = readl(sys_osc) & ~0x7ffff;
257         val |= vco.v | (vco.r << 9) | (vco.s << 16);
258
259         writel(0xa05f, sys_lock);
260         writel(val, sys_osc);
261         writel(0, sys_lock);
262 }
263
264 static struct clk oscvco_clk = {
265         .params = &realview_oscvco_params,
266         .setvco = realview_oscvco_set,
267 };
268
269 /*
270  * These are fixed clocks.
271  */
272 static struct clk ref24_clk = {
273         .rate   = 24000000,
274 };
275
276 static struct clk_lookup lookups[] = {
277         {       /* UART0 */
278                 .dev_id         = "dev:f1",
279                 .clk            = &ref24_clk,
280         }, {    /* UART1 */
281                 .dev_id         = "dev:f2",
282                 .clk            = &ref24_clk,
283         }, {    /* UART2 */
284                 .dev_id         = "dev:f3",
285                 .clk            = &ref24_clk,
286         }, {    /* UART3 */
287                 .dev_id         = "fpga:09",
288                 .clk            = &ref24_clk,
289         }, {    /* KMI0 */
290                 .dev_id         = "fpga:06",
291                 .clk            = &ref24_clk,
292         }, {    /* KMI1 */
293                 .dev_id         = "fpga:07",
294                 .clk            = &ref24_clk,
295         }, {    /* MMC0 */
296                 .dev_id         = "fpga:05",
297                 .clk            = &ref24_clk,
298         }, {    /* EB:CLCD */
299                 .dev_id         = "dev:20",
300                 .clk            = &oscvco_clk,
301         }, {    /* PB:CLCD */
302                 .dev_id         = "issp:20",
303                 .clk            = &oscvco_clk,
304         }
305 };
306
307 static int __init clk_init(void)
308 {
309         int i;
310
311         for (i = 0; i < ARRAY_SIZE(lookups); i++)
312                 clkdev_add(&lookups[i]);
313         return 0;
314 }
315 arch_initcall(clk_init);
316
317 /*
318  * CLCD support.
319  */
320 #define SYS_CLCD_NLCDIOON       (1 << 2)
321 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
322 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
323 #define SYS_CLCD_ID_MASK        (0x1f << 8)
324 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
325 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
326 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
327 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
328 #define SYS_CLCD_ID_VGA         (0x1f << 8)
329
330 static struct clcd_panel vga = {
331         .mode           = {
332                 .name           = "VGA",
333                 .refresh        = 60,
334                 .xres           = 640,
335                 .yres           = 480,
336                 .pixclock       = 39721,
337                 .left_margin    = 40,
338                 .right_margin   = 24,
339                 .upper_margin   = 32,
340                 .lower_margin   = 11,
341                 .hsync_len      = 96,
342                 .vsync_len      = 2,
343                 .sync           = 0,
344                 .vmode          = FB_VMODE_NONINTERLACED,
345         },
346         .width          = -1,
347         .height         = -1,
348         .tim2           = TIM2_BCD | TIM2_IPC,
349         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
350         .bpp            = 16,
351 };
352
353 static struct clcd_panel xvga = {
354         .mode           = {
355                 .name           = "XVGA",
356                 .refresh        = 60,
357                 .xres           = 1024,
358                 .yres           = 768,
359                 .pixclock       = 15748,
360                 .left_margin    = 152,
361                 .right_margin   = 48,
362                 .upper_margin   = 23,
363                 .lower_margin   = 3,
364                 .hsync_len      = 104,
365                 .vsync_len      = 4,
366                 .sync           = 0,
367                 .vmode          = FB_VMODE_NONINTERLACED,
368         },
369         .width          = -1,
370         .height         = -1,
371         .tim2           = TIM2_BCD | TIM2_IPC,
372         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
373         .bpp            = 16,
374 };
375
376 static struct clcd_panel sanyo_3_8_in = {
377         .mode           = {
378                 .name           = "Sanyo QVGA",
379                 .refresh        = 116,
380                 .xres           = 320,
381                 .yres           = 240,
382                 .pixclock       = 100000,
383                 .left_margin    = 6,
384                 .right_margin   = 6,
385                 .upper_margin   = 5,
386                 .lower_margin   = 5,
387                 .hsync_len      = 6,
388                 .vsync_len      = 6,
389                 .sync           = 0,
390                 .vmode          = FB_VMODE_NONINTERLACED,
391         },
392         .width          = -1,
393         .height         = -1,
394         .tim2           = TIM2_BCD,
395         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
396         .bpp            = 16,
397 };
398
399 static struct clcd_panel sanyo_2_5_in = {
400         .mode           = {
401                 .name           = "Sanyo QVGA Portrait",
402                 .refresh        = 116,
403                 .xres           = 240,
404                 .yres           = 320,
405                 .pixclock       = 100000,
406                 .left_margin    = 20,
407                 .right_margin   = 10,
408                 .upper_margin   = 2,
409                 .lower_margin   = 2,
410                 .hsync_len      = 10,
411                 .vsync_len      = 2,
412                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
413                 .vmode          = FB_VMODE_NONINTERLACED,
414         },
415         .width          = -1,
416         .height         = -1,
417         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
418         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
419         .bpp            = 16,
420 };
421
422 static struct clcd_panel epson_2_2_in = {
423         .mode           = {
424                 .name           = "Epson QCIF",
425                 .refresh        = 390,
426                 .xres           = 176,
427                 .yres           = 220,
428                 .pixclock       = 62500,
429                 .left_margin    = 3,
430                 .right_margin   = 2,
431                 .upper_margin   = 1,
432                 .lower_margin   = 0,
433                 .hsync_len      = 3,
434                 .vsync_len      = 2,
435                 .sync           = 0,
436                 .vmode          = FB_VMODE_NONINTERLACED,
437         },
438         .width          = -1,
439         .height         = -1,
440         .tim2           = TIM2_BCD | TIM2_IPC,
441         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
442         .bpp            = 16,
443 };
444
445 /*
446  * Detect which LCD panel is connected, and return the appropriate
447  * clcd_panel structure.  Note: we do not have any information on
448  * the required timings for the 8.4in panel, so we presently assume
449  * VGA timings.
450  */
451 static struct clcd_panel *realview_clcd_panel(void)
452 {
453         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
454         struct clcd_panel *vga_panel;
455         struct clcd_panel *panel;
456         u32 val;
457
458         if (machine_is_realview_eb())
459                 vga_panel = &vga;
460         else
461                 vga_panel = &xvga;
462
463         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
464         if (val == SYS_CLCD_ID_SANYO_3_8)
465                 panel = &sanyo_3_8_in;
466         else if (val == SYS_CLCD_ID_SANYO_2_5)
467                 panel = &sanyo_2_5_in;
468         else if (val == SYS_CLCD_ID_EPSON_2_2)
469                 panel = &epson_2_2_in;
470         else if (val == SYS_CLCD_ID_VGA)
471                 panel = vga_panel;
472         else {
473                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
474                         val);
475                 panel = vga_panel;
476         }
477
478         return panel;
479 }
480
481 /*
482  * Disable all display connectors on the interface module.
483  */
484 static void realview_clcd_disable(struct clcd_fb *fb)
485 {
486         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
487         u32 val;
488
489         val = readl(sys_clcd);
490         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
491         writel(val, sys_clcd);
492 }
493
494 /*
495  * Enable the relevant connector on the interface module.
496  */
497 static void realview_clcd_enable(struct clcd_fb *fb)
498 {
499         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
500         u32 val;
501
502         /*
503          * Enable the PSUs
504          */
505         val = readl(sys_clcd);
506         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
507         writel(val, sys_clcd);
508 }
509
510 static int realview_clcd_setup(struct clcd_fb *fb)
511 {
512         unsigned long framesize;
513         dma_addr_t dma;
514
515         if (machine_is_realview_eb())
516                 /* VGA, 16bpp */
517                 framesize = 640 * 480 * 2;
518         else
519                 /* XVGA, 16bpp */
520                 framesize = 1024 * 768 * 2;
521
522         fb->panel               = realview_clcd_panel();
523
524         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
525                                                     &dma, GFP_KERNEL);
526         if (!fb->fb.screen_base) {
527                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
528                 return -ENOMEM;
529         }
530
531         fb->fb.fix.smem_start   = dma;
532         fb->fb.fix.smem_len     = framesize;
533
534         return 0;
535 }
536
537 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
538 {
539         return dma_mmap_writecombine(&fb->dev->dev, vma,
540                                      fb->fb.screen_base,
541                                      fb->fb.fix.smem_start,
542                                      fb->fb.fix.smem_len);
543 }
544
545 static void realview_clcd_remove(struct clcd_fb *fb)
546 {
547         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
548                               fb->fb.screen_base, fb->fb.fix.smem_start);
549 }
550
551 struct clcd_board clcd_plat_data = {
552         .name           = "RealView",
553         .check          = clcdfb_check,
554         .decode         = clcdfb_decode,
555         .disable        = realview_clcd_disable,
556         .enable         = realview_clcd_enable,
557         .setup          = realview_clcd_setup,
558         .mmap           = realview_clcd_mmap,
559         .remove         = realview_clcd_remove,
560 };
561
562 #ifdef CONFIG_LEDS
563 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
564
565 void realview_leds_event(led_event_t ledevt)
566 {
567         unsigned long flags;
568         u32 val;
569
570         local_irq_save(flags);
571         val = readl(VA_LEDS_BASE);
572
573         switch (ledevt) {
574         case led_idle_start:
575                 val = val & ~REALVIEW_SYS_LED0;
576                 break;
577
578         case led_idle_end:
579                 val = val | REALVIEW_SYS_LED0;
580                 break;
581
582         case led_timer:
583                 val = val ^ REALVIEW_SYS_LED1;
584                 break;
585
586         case led_halted:
587                 val = 0;
588                 break;
589
590         default:
591                 break;
592         }
593
594         writel(val, VA_LEDS_BASE);
595         local_irq_restore(flags);
596 }
597 #endif  /* CONFIG_LEDS */
598
599 /*
600  * Where is the timer (VA)?
601  */
602 void __iomem *timer0_va_base;
603 void __iomem *timer1_va_base;
604 void __iomem *timer2_va_base;
605 void __iomem *timer3_va_base;
606
607 /*
608  * How long is the timer interval?
609  */
610 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
611 #if TIMER_INTERVAL >= 0x100000
612 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
613 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
614 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
615 #elif TIMER_INTERVAL >= 0x10000
616 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
617 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
618 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
619 #else
620 #define TIMER_RELOAD    (TIMER_INTERVAL)
621 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
622 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
623 #endif
624
625 static void timer_set_mode(enum clock_event_mode mode,
626                            struct clock_event_device *clk)
627 {
628         unsigned long ctrl;
629
630         switch(mode) {
631         case CLOCK_EVT_MODE_PERIODIC:
632                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
633
634                 ctrl = TIMER_CTRL_PERIODIC;
635                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
636                 break;
637         case CLOCK_EVT_MODE_ONESHOT:
638                 /* period set, and timer enabled in 'next_event' hook */
639                 ctrl = TIMER_CTRL_ONESHOT;
640                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
641                 break;
642         case CLOCK_EVT_MODE_UNUSED:
643         case CLOCK_EVT_MODE_SHUTDOWN:
644         default:
645                 ctrl = 0;
646         }
647
648         writel(ctrl, timer0_va_base + TIMER_CTRL);
649 }
650
651 static int timer_set_next_event(unsigned long evt,
652                                 struct clock_event_device *unused)
653 {
654         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
655
656         writel(evt, timer0_va_base + TIMER_LOAD);
657         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
658
659         return 0;
660 }
661
662 static struct clock_event_device timer0_clockevent =     {
663         .name           = "timer0",
664         .shift          = 32,
665         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
666         .set_mode       = timer_set_mode,
667         .set_next_event = timer_set_next_event,
668         .rating         = 300,
669         .cpumask        = cpu_all_mask,
670 };
671
672 static void __init realview_clockevents_init(unsigned int timer_irq)
673 {
674         timer0_clockevent.irq = timer_irq;
675         timer0_clockevent.mult =
676                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
677         timer0_clockevent.max_delta_ns =
678                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
679         timer0_clockevent.min_delta_ns =
680                 clockevent_delta2ns(0xf, &timer0_clockevent);
681
682         clockevents_register_device(&timer0_clockevent);
683 }
684
685 /*
686  * IRQ handler for the timer
687  */
688 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
689 {
690         struct clock_event_device *evt = &timer0_clockevent;
691
692         /* clear the interrupt */
693         writel(1, timer0_va_base + TIMER_INTCLR);
694
695         evt->event_handler(evt);
696
697         return IRQ_HANDLED;
698 }
699
700 static struct irqaction realview_timer_irq = {
701         .name           = "RealView Timer Tick",
702         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
703         .handler        = realview_timer_interrupt,
704 };
705
706 static cycle_t realview_get_cycles(void)
707 {
708         return ~readl(timer3_va_base + TIMER_VALUE);
709 }
710
711 static struct clocksource clocksource_realview = {
712         .name   = "timer3",
713         .rating = 200,
714         .read   = realview_get_cycles,
715         .mask   = CLOCKSOURCE_MASK(32),
716         .shift  = 20,
717         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
718 };
719
720 static void __init realview_clocksource_init(void)
721 {
722         /* setup timer 0 as free-running clocksource */
723         writel(0, timer3_va_base + TIMER_CTRL);
724         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
725         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
726         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
727                 timer3_va_base + TIMER_CTRL);
728
729         clocksource_realview.mult =
730                 clocksource_khz2mult(1000, clocksource_realview.shift);
731         clocksource_register(&clocksource_realview);
732 }
733
734 /*
735  * Set up the clock source and clock events devices
736  */
737 void __init realview_timer_init(unsigned int timer_irq)
738 {
739         u32 val;
740
741 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
742         /*
743          * The dummy clock device has to be registered before the main device
744          * so that the latter will broadcast the clock events
745          */
746         local_timer_setup();
747 #endif
748
749         /* 
750          * set clock frequency: 
751          *      REALVIEW_REFCLK is 32KHz
752          *      REALVIEW_TIMCLK is 1MHz
753          */
754         val = readl(__io_address(REALVIEW_SCTL_BASE));
755         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
756                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
757                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
758                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
759                __io_address(REALVIEW_SCTL_BASE));
760
761         /*
762          * Initialise to a known state (all timers off)
763          */
764         writel(0, timer0_va_base + TIMER_CTRL);
765         writel(0, timer1_va_base + TIMER_CTRL);
766         writel(0, timer2_va_base + TIMER_CTRL);
767         writel(0, timer3_va_base + TIMER_CTRL);
768
769         /* 
770          * Make irqs happen for the system timer
771          */
772         setup_irq(timer_irq, &realview_timer_irq);
773
774         realview_clocksource_init();
775         realview_clockevents_init(timer_irq);
776 }