OMAP: control: move plat-omap/control.h to mach-omap2/control.h
[linux-2.6.git] / arch / arm / mach-omap2 / serial.c
1 /*
2  * arch/arm/mach-omap2/serial.c
3  *
4  * OMAP2 serial support.
5  *
6  * Copyright (C) 2005-2008 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * Major rework for PM support by Kevin Hilman
10  *
11  * Based off of arch/arm/mach-omap/omap1/serial.c
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License. See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/serial_8250.h>
29 #include <linux/pm_runtime.h>
30
31 #ifdef CONFIG_SERIAL_OMAP
32 #include <plat/omap-serial.h>
33 #endif
34
35 #include <plat/common.h>
36 #include <plat/board.h>
37 #include <plat/clock.h>
38 #include <plat/dma.h>
39 #include <plat/omap_hwmod.h>
40 #include <plat/omap_device.h>
41
42 #include "prm.h"
43 #include "pm.h"
44 #include "cm.h"
45 #include "prm-regbits-34xx.h"
46 #include "control.h"
47
48 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
49 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
50
51 #define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
52 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
53
54 /*
55  * NOTE: By default the serial timeout is disabled as it causes lost characters
56  * over the serial ports. This means that the UART clocks will stay on until
57  * disabled via sysfs. This also causes that any deeper omap sleep states are
58  * blocked. 
59  */
60 #define DEFAULT_TIMEOUT 0
61
62 #define MAX_UART_HWMOD_NAME_LEN         16
63
64 struct omap_uart_state {
65         int num;
66         int can_sleep;
67         struct timer_list timer;
68         u32 timeout;
69
70         void __iomem *wk_st;
71         void __iomem *wk_en;
72         u32 wk_mask;
73         u32 padconf;
74         u32 dma_enabled;
75
76         struct clk *ick;
77         struct clk *fck;
78         int clocked;
79
80         int irq;
81         int regshift;
82         int irqflags;
83         void __iomem *membase;
84         resource_size_t mapbase;
85
86         struct list_head node;
87         struct omap_hwmod *oh;
88         struct platform_device *pdev;
89
90         u32 errata;
91 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
92         int context_valid;
93
94         /* Registers to be saved/restored for OFF-mode */
95         u16 dll;
96         u16 dlh;
97         u16 ier;
98         u16 sysc;
99         u16 scr;
100         u16 wer;
101         u16 mcr;
102 #endif
103 };
104
105 static LIST_HEAD(uart_list);
106 static u8 num_uarts;
107
108 /*
109  * Since these idle/enable hooks are used in the idle path itself
110  * which has interrupts disabled, use the non-locking versions of
111  * the hwmod enable/disable functions.
112  */
113 static int uart_idle_hwmod(struct omap_device *od)
114 {
115         _omap_hwmod_idle(od->hwmods[0]);
116
117         return 0;
118 }
119
120 static int uart_enable_hwmod(struct omap_device *od)
121 {
122         _omap_hwmod_enable(od->hwmods[0]);
123
124         return 0;
125 }
126
127 static struct omap_device_pm_latency omap_uart_latency[] = {
128         {
129                 .deactivate_func = uart_idle_hwmod,
130                 .activate_func   = uart_enable_hwmod,
131                 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
132         },
133 };
134
135 static inline unsigned int __serial_read_reg(struct uart_port *up,
136                                              int offset)
137 {
138         offset <<= up->regshift;
139         return (unsigned int)__raw_readb(up->membase + offset);
140 }
141
142 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
143                                            int offset)
144 {
145         offset <<= uart->regshift;
146         return (unsigned int)__raw_readb(uart->membase + offset);
147 }
148
149 static inline void __serial_write_reg(struct uart_port *up, int offset,
150                 int value)
151 {
152         offset <<= up->regshift;
153         __raw_writeb(value, up->membase + offset);
154 }
155
156 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
157                                     int value)
158 {
159         offset <<= uart->regshift;
160         __raw_writeb(value, uart->membase + offset);
161 }
162
163 /*
164  * Internal UARTs need to be initialized for the 8250 autoconfig to work
165  * properly. Note that the TX watermark initialization may not be needed
166  * once the 8250.c watermark handling code is merged.
167  */
168
169 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
170 {
171         serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
172         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
173         serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
174 }
175
176 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
177
178 /*
179  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
180  * The access to uart register after MDR1 Access
181  * causes UART to corrupt data.
182  *
183  * Need a delay =
184  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
185  * give 10 times as much
186  */
187 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
188                 u8 fcr_val)
189 {
190         u8 timeout = 255;
191
192         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
193         udelay(2);
194         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
195                         UART_FCR_CLEAR_RCVR);
196         /*
197          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
198          * TX_FIFO_E bit is 1.
199          */
200         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
201                                 (UART_LSR_THRE | UART_LSR_DR))) {
202                 timeout--;
203                 if (!timeout) {
204                         /* Should *never* happen. we warn and carry on */
205                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
206                         serial_read_reg(uart, UART_LSR));
207                         break;
208                 }
209                 udelay(1);
210         }
211 }
212
213 static void omap_uart_save_context(struct omap_uart_state *uart)
214 {
215         u16 lcr = 0;
216
217         if (!enable_off_mode)
218                 return;
219
220         lcr = serial_read_reg(uart, UART_LCR);
221         serial_write_reg(uart, UART_LCR, 0xBF);
222         uart->dll = serial_read_reg(uart, UART_DLL);
223         uart->dlh = serial_read_reg(uart, UART_DLM);
224         serial_write_reg(uart, UART_LCR, lcr);
225         uart->ier = serial_read_reg(uart, UART_IER);
226         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
227         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
228         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
229         serial_write_reg(uart, UART_LCR, 0x80);
230         uart->mcr = serial_read_reg(uart, UART_MCR);
231         serial_write_reg(uart, UART_LCR, lcr);
232
233         uart->context_valid = 1;
234 }
235
236 static void omap_uart_restore_context(struct omap_uart_state *uart)
237 {
238         u16 efr = 0;
239
240         if (!enable_off_mode)
241                 return;
242
243         if (!uart->context_valid)
244                 return;
245
246         uart->context_valid = 0;
247
248         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
249                 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
250         else
251                 serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
252         serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
253         efr = serial_read_reg(uart, UART_EFR);
254         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
255         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
256         serial_write_reg(uart, UART_IER, 0x0);
257         serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
258         serial_write_reg(uart, UART_DLL, uart->dll);
259         serial_write_reg(uart, UART_DLM, uart->dlh);
260         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
261         serial_write_reg(uart, UART_IER, uart->ier);
262         serial_write_reg(uart, UART_LCR, 0x80);
263         serial_write_reg(uart, UART_MCR, uart->mcr);
264         serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
265         serial_write_reg(uart, UART_EFR, efr);
266         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
267         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
268         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
269         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
270         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
271                 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
272         else
273                 /* UART 16x mode */
274                 serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
275 }
276 #else
277 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
278 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
279 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
280
281 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
282 {
283         if (uart->clocked)
284                 return;
285
286         omap_device_enable(uart->pdev);
287         uart->clocked = 1;
288         omap_uart_restore_context(uart);
289 }
290
291 #ifdef CONFIG_PM
292
293 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
294 {
295         if (!uart->clocked)
296                 return;
297
298         omap_uart_save_context(uart);
299         uart->clocked = 0;
300         omap_device_idle(uart->pdev);
301 }
302
303 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
304 {
305         /* Set wake-enable bit */
306         if (uart->wk_en && uart->wk_mask) {
307                 u32 v = __raw_readl(uart->wk_en);
308                 v |= uart->wk_mask;
309                 __raw_writel(v, uart->wk_en);
310         }
311
312         /* Ensure IOPAD wake-enables are set */
313         if (cpu_is_omap34xx() && uart->padconf) {
314                 u16 v = omap_ctrl_readw(uart->padconf);
315                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
316                 omap_ctrl_writew(v, uart->padconf);
317         }
318 }
319
320 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
321 {
322         /* Clear wake-enable bit */
323         if (uart->wk_en && uart->wk_mask) {
324                 u32 v = __raw_readl(uart->wk_en);
325                 v &= ~uart->wk_mask;
326                 __raw_writel(v, uart->wk_en);
327         }
328
329         /* Ensure IOPAD wake-enables are cleared */
330         if (cpu_is_omap34xx() && uart->padconf) {
331                 u16 v = omap_ctrl_readw(uart->padconf);
332                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
333                 omap_ctrl_writew(v, uart->padconf);
334         }
335 }
336
337 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
338                                                int enable)
339 {
340         u8 idlemode;
341
342         if (enable) {
343                 /**
344                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
345                  * in Smartidle Mode When Configured for DMA Operations.
346                  */
347                 if (uart->dma_enabled)
348                         idlemode = HWMOD_IDLEMODE_FORCE;
349                 else
350                         idlemode = HWMOD_IDLEMODE_SMART;
351         } else {
352                 idlemode = HWMOD_IDLEMODE_NO;
353         }
354
355         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
356 }
357
358 static void omap_uart_block_sleep(struct omap_uart_state *uart)
359 {
360         omap_uart_enable_clocks(uart);
361
362         omap_uart_smart_idle_enable(uart, 0);
363         uart->can_sleep = 0;
364         if (uart->timeout)
365                 mod_timer(&uart->timer, jiffies + uart->timeout);
366         else
367                 del_timer(&uart->timer);
368 }
369
370 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
371 {
372         if (device_may_wakeup(&uart->pdev->dev))
373                 omap_uart_enable_wakeup(uart);
374         else
375                 omap_uart_disable_wakeup(uart);
376
377         if (!uart->clocked)
378                 return;
379
380         omap_uart_smart_idle_enable(uart, 1);
381         uart->can_sleep = 1;
382         del_timer(&uart->timer);
383 }
384
385 static void omap_uart_idle_timer(unsigned long data)
386 {
387         struct omap_uart_state *uart = (struct omap_uart_state *)data;
388
389         omap_uart_allow_sleep(uart);
390 }
391
392 void omap_uart_prepare_idle(int num)
393 {
394         struct omap_uart_state *uart;
395
396         list_for_each_entry(uart, &uart_list, node) {
397                 if (num == uart->num && uart->can_sleep) {
398                         omap_uart_disable_clocks(uart);
399                         return;
400                 }
401         }
402 }
403
404 void omap_uart_resume_idle(int num)
405 {
406         struct omap_uart_state *uart;
407
408         list_for_each_entry(uart, &uart_list, node) {
409                 if (num == uart->num) {
410                         omap_uart_enable_clocks(uart);
411
412                         /* Check for IO pad wakeup */
413                         if (cpu_is_omap34xx() && uart->padconf) {
414                                 u16 p = omap_ctrl_readw(uart->padconf);
415
416                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
417                                         omap_uart_block_sleep(uart);
418                         }
419
420                         /* Check for normal UART wakeup */
421                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
422                                 omap_uart_block_sleep(uart);
423                         return;
424                 }
425         }
426 }
427
428 void omap_uart_prepare_suspend(void)
429 {
430         struct omap_uart_state *uart;
431
432         list_for_each_entry(uart, &uart_list, node) {
433                 omap_uart_allow_sleep(uart);
434         }
435 }
436
437 int omap_uart_can_sleep(void)
438 {
439         struct omap_uart_state *uart;
440         int can_sleep = 1;
441
442         list_for_each_entry(uart, &uart_list, node) {
443                 if (!uart->clocked)
444                         continue;
445
446                 if (!uart->can_sleep) {
447                         can_sleep = 0;
448                         continue;
449                 }
450
451                 /* This UART can now safely sleep. */
452                 omap_uart_allow_sleep(uart);
453         }
454
455         return can_sleep;
456 }
457
458 /**
459  * omap_uart_interrupt()
460  *
461  * This handler is used only to detect that *any* UART interrupt has
462  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
463  * any UART interrupt will trigger the inactivity timer so the
464  * UART will not idle or sleep for its timeout period.
465  *
466  **/
467 /* static int first_interrupt; */
468 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
469 {
470         struct omap_uart_state *uart = dev_id;
471
472         omap_uart_block_sleep(uart);
473
474         return IRQ_NONE;
475 }
476
477 static void omap_uart_idle_init(struct omap_uart_state *uart)
478 {
479         int ret;
480
481         uart->can_sleep = 0;
482         uart->timeout = DEFAULT_TIMEOUT;
483         setup_timer(&uart->timer, omap_uart_idle_timer,
484                     (unsigned long) uart);
485         if (uart->timeout)
486                 mod_timer(&uart->timer, jiffies + uart->timeout);
487         omap_uart_smart_idle_enable(uart, 0);
488
489         if (cpu_is_omap34xx()) {
490                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
491                 u32 wk_mask = 0;
492                 u32 padconf = 0;
493
494                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
495                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
496                 switch (uart->num) {
497                 case 0:
498                         wk_mask = OMAP3430_ST_UART1_MASK;
499                         padconf = 0x182;
500                         break;
501                 case 1:
502                         wk_mask = OMAP3430_ST_UART2_MASK;
503                         padconf = 0x17a;
504                         break;
505                 case 2:
506                         wk_mask = OMAP3430_ST_UART3_MASK;
507                         padconf = 0x19e;
508                         break;
509                 case 3:
510                         wk_mask = OMAP3630_ST_UART4_MASK;
511                         padconf = 0x0d2;
512                         break;
513                 }
514                 uart->wk_mask = wk_mask;
515                 uart->padconf = padconf;
516         } else if (cpu_is_omap24xx()) {
517                 u32 wk_mask = 0;
518
519                 if (cpu_is_omap2430()) {
520                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
521                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
522                 } else if (cpu_is_omap2420()) {
523                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
524                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
525                 }
526                 switch (uart->num) {
527                 case 0:
528                         wk_mask = OMAP24XX_ST_UART1_MASK;
529                         break;
530                 case 1:
531                         wk_mask = OMAP24XX_ST_UART2_MASK;
532                         break;
533                 case 2:
534                         wk_mask = OMAP24XX_ST_UART3_MASK;
535                         break;
536                 }
537                 uart->wk_mask = wk_mask;
538         } else {
539                 uart->wk_en = NULL;
540                 uart->wk_st = NULL;
541                 uart->wk_mask = 0;
542                 uart->padconf = 0;
543         }
544
545         uart->irqflags |= IRQF_SHARED;
546         ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
547                                    IRQF_SHARED, "serial idle", (void *)uart);
548         WARN_ON(ret);
549 }
550
551 void omap_uart_enable_irqs(int enable)
552 {
553         int ret;
554         struct omap_uart_state *uart;
555
556         list_for_each_entry(uart, &uart_list, node) {
557                 if (enable) {
558                         pm_runtime_put_sync(&uart->pdev->dev);
559                         ret = request_threaded_irq(uart->irq, NULL,
560                                                    omap_uart_interrupt,
561                                                    IRQF_SHARED,
562                                                    "serial idle",
563                                                    (void *)uart);
564                 } else {
565                         pm_runtime_get_noresume(&uart->pdev->dev);
566                         free_irq(uart->irq, (void *)uart);
567                 }
568         }
569 }
570
571 static ssize_t sleep_timeout_show(struct device *dev,
572                                   struct device_attribute *attr,
573                                   char *buf)
574 {
575         struct platform_device *pdev = to_platform_device(dev);
576         struct omap_device *odev = to_omap_device(pdev);
577         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
578
579         return sprintf(buf, "%u\n", uart->timeout / HZ);
580 }
581
582 static ssize_t sleep_timeout_store(struct device *dev,
583                                    struct device_attribute *attr,
584                                    const char *buf, size_t n)
585 {
586         struct platform_device *pdev = to_platform_device(dev);
587         struct omap_device *odev = to_omap_device(pdev);
588         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
589         unsigned int value;
590
591         if (sscanf(buf, "%u", &value) != 1) {
592                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
593                 return -EINVAL;
594         }
595
596         uart->timeout = value * HZ;
597         if (uart->timeout)
598                 mod_timer(&uart->timer, jiffies + uart->timeout);
599         else
600                 /* A zero value means disable timeout feature */
601                 omap_uart_block_sleep(uart);
602
603         return n;
604 }
605
606 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
607                 sleep_timeout_store);
608 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
609 #else
610 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
611 static void omap_uart_block_sleep(struct omap_uart_state *uart) {}
612 #define DEV_CREATE_FILE(dev, attr)
613 #endif /* CONFIG_PM */
614
615 #ifndef CONFIG_SERIAL_OMAP
616 /*
617  * Override the default 8250 read handler: mem_serial_in()
618  * Empty RX fifo read causes an abort on omap3630 and omap4
619  * This function makes sure that an empty rx fifo is not read on these silicons
620  * (OMAP1/2/3430 are not affected)
621  */
622 static unsigned int serial_in_override(struct uart_port *up, int offset)
623 {
624         if (UART_RX == offset) {
625                 unsigned int lsr;
626                 lsr = __serial_read_reg(up, UART_LSR);
627                 if (!(lsr & UART_LSR_DR))
628                         return -EPERM;
629         }
630
631         return __serial_read_reg(up, offset);
632 }
633
634 static void serial_out_override(struct uart_port *up, int offset, int value)
635 {
636         unsigned int status, tmout = 10000;
637
638         status = __serial_read_reg(up, UART_LSR);
639         while (!(status & UART_LSR_THRE)) {
640                 /* Wait up to 10ms for the character(s) to be sent. */
641                 if (--tmout == 0)
642                         break;
643                 udelay(1);
644                 status = __serial_read_reg(up, UART_LSR);
645         }
646         __serial_write_reg(up, offset, value);
647 }
648 #endif
649
650 void __init omap_serial_early_init(void)
651 {
652         int i = 0;
653
654         do {
655                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
656                 struct omap_hwmod *oh;
657                 struct omap_uart_state *uart;
658
659                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
660                          "uart%d", i + 1);
661                 oh = omap_hwmod_lookup(oh_name);
662                 if (!oh)
663                         break;
664
665                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
666                 if (WARN_ON(!uart))
667                         return;
668
669                 uart->oh = oh;
670                 uart->num = i++;
671                 list_add_tail(&uart->node, &uart_list);
672                 num_uarts++;
673
674                 /*
675                  * NOTE: omap_hwmod_init() has not yet been called,
676                  *       so no hwmod functions will work yet.
677                  */
678
679                 /*
680                  * During UART early init, device need to be probed
681                  * to determine SoC specific init before omap_device
682                  * is ready.  Therefore, don't allow idle here
683                  */
684                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
685         } while (1);
686 }
687
688 /**
689  * omap_serial_init_port() - initialize single serial port
690  * @port: serial port number (0-3)
691  *
692  * This function initialies serial driver for given @port only.
693  * Platforms can call this function instead of omap_serial_init()
694  * if they don't plan to use all available UARTs as serial ports.
695  *
696  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
697  * use only one of the two.
698  */
699 void __init omap_serial_init_port(int port)
700 {
701         struct omap_uart_state *uart;
702         struct omap_hwmod *oh;
703         struct omap_device *od;
704         void *pdata = NULL;
705         u32 pdata_size = 0;
706         char *name;
707 #ifndef CONFIG_SERIAL_OMAP
708         struct plat_serial8250_port ports[2] = {
709                 {},
710                 {.flags = 0},
711         };
712         struct plat_serial8250_port *p = &ports[0];
713 #else
714         struct omap_uart_port_info omap_up;
715 #endif
716
717         if (WARN_ON(port < 0))
718                 return;
719         if (WARN_ON(port >= num_uarts))
720                 return;
721
722         list_for_each_entry(uart, &uart_list, node)
723                 if (port == uart->num)
724                         break;
725
726         oh = uart->oh;
727         uart->dma_enabled = 0;
728 #ifndef CONFIG_SERIAL_OMAP
729         name = "serial8250";
730
731         /*
732          * !! 8250 driver does not use standard IORESOURCE* It
733          * has it's own custom pdata that can be taken from
734          * the hwmod resource data.  But, this needs to be
735          * done after the build.
736          *
737          * ?? does it have to be done before the register ??
738          * YES, because platform_device_data_add() copies
739          * pdata, it does not use a pointer.
740          */
741         p->flags = UPF_BOOT_AUTOCONF;
742         p->iotype = UPIO_MEM;
743         p->regshift = 2;
744         p->uartclk = OMAP24XX_BASE_BAUD * 16;
745         p->irq = oh->mpu_irqs[0].irq;
746         p->mapbase = oh->slaves[0]->addr->pa_start;
747         p->membase = omap_hwmod_get_mpu_rt_va(oh);
748         p->irqflags = IRQF_SHARED;
749         p->private_data = uart;
750
751         /*
752          * omap44xx: Never read empty UART fifo
753          * omap3xxx: Never read empty UART fifo on UARTs
754          * with IP rev >=0x52
755          */
756         uart->regshift = p->regshift;
757         uart->membase = p->membase;
758         if (cpu_is_omap44xx())
759                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
760         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
761                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
762                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
763
764         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
765                 p->serial_in = serial_in_override;
766                 p->serial_out = serial_out_override;
767         }
768
769         pdata = &ports[0];
770         pdata_size = 2 * sizeof(struct plat_serial8250_port);
771 #else
772
773         name = DRIVER_NAME;
774
775         omap_up.dma_enabled = uart->dma_enabled;
776         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
777         omap_up.mapbase = oh->slaves[0]->addr->pa_start;
778         omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
779         omap_up.irqflags = IRQF_SHARED;
780         omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
781
782         pdata = &omap_up;
783         pdata_size = sizeof(struct omap_uart_port_info);
784 #endif
785
786         if (WARN_ON(!oh))
787                 return;
788
789         od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
790                                omap_uart_latency,
791                                ARRAY_SIZE(omap_uart_latency), false);
792         WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
793              name, oh->name);
794
795         uart->irq = oh->mpu_irqs[0].irq;
796         uart->regshift = 2;
797         uart->mapbase = oh->slaves[0]->addr->pa_start;
798         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
799         uart->pdev = &od->pdev;
800
801         oh->dev_attr = uart;
802
803         /*
804          * Because of early UART probing, UART did not get idled
805          * on init.  Now that omap_device is ready, ensure full idle
806          * before doing omap_device_enable().
807          */
808         omap_hwmod_idle(uart->oh);
809
810         omap_device_enable(uart->pdev);
811         omap_uart_idle_init(uart);
812         omap_uart_reset(uart);
813         omap_hwmod_enable_wakeup(uart->oh);
814         omap_device_idle(uart->pdev);
815
816         /*
817          * Need to block sleep long enough for interrupt driven
818          * driver to start.  Console driver is in polling mode
819          * so device needs to be kept enabled while polling driver
820          * is in use.
821          */
822         if (uart->timeout)
823                 uart->timeout = (30 * HZ);
824         omap_uart_block_sleep(uart);
825         uart->timeout = DEFAULT_TIMEOUT;
826
827         if ((cpu_is_omap34xx() && uart->padconf) ||
828             (uart->wk_en && uart->wk_mask)) {
829                 device_init_wakeup(&od->pdev.dev, true);
830                 DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
831         }
832
833         /* Enable the MDR1 errata for OMAP3 */
834         if (cpu_is_omap34xx())
835                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
836 }
837
838 /**
839  * omap_serial_init() - intialize all supported serial ports
840  *
841  * Initializes all available UARTs as serial ports. Platforms
842  * can call this function when they want to have default behaviour
843  * for serial ports (e.g initialize them all as serial ports).
844  */
845 void __init omap_serial_init(void)
846 {
847         struct omap_uart_state *uart;
848
849         list_for_each_entry(uart, &uart_list, node)
850                 omap_serial_init_port(uart->num);
851 }