OMAP: control: move plat-omap/control.h to mach-omap2/control.h
[linux-2.6.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/map.h>
23 #include <asm/pmu.h>
24
25 #include <plat/tc.h>
26 #include <plat/board.h>
27 #include <mach/gpio.h>
28 #include <plat/mmc.h>
29 #include <plat/dma.h>
30 #include <plat/omap_hwmod.h>
31 #include <plat/omap_device.h>
32
33 #include "mux.h"
34 #include "control.h"
35
36 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
37
38 static struct resource cam_resources[] = {
39         {
40                 .start          = OMAP24XX_CAMERA_BASE,
41                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
42                 .flags          = IORESOURCE_MEM,
43         },
44         {
45                 .start          = INT_24XX_CAM_IRQ,
46                 .flags          = IORESOURCE_IRQ,
47         }
48 };
49
50 static struct platform_device omap_cam_device = {
51         .name           = "omap24xxcam",
52         .id             = -1,
53         .num_resources  = ARRAY_SIZE(cam_resources),
54         .resource       = cam_resources,
55 };
56
57 static inline void omap_init_camera(void)
58 {
59         platform_device_register(&omap_cam_device);
60 }
61
62 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
63
64 static struct resource omap3isp_resources[] = {
65         {
66                 .start          = OMAP3430_ISP_BASE,
67                 .end            = OMAP3430_ISP_END,
68                 .flags          = IORESOURCE_MEM,
69         },
70         {
71                 .start          = OMAP3430_ISP_CBUFF_BASE,
72                 .end            = OMAP3430_ISP_CBUFF_END,
73                 .flags          = IORESOURCE_MEM,
74         },
75         {
76                 .start          = OMAP3430_ISP_CCP2_BASE,
77                 .end            = OMAP3430_ISP_CCP2_END,
78                 .flags          = IORESOURCE_MEM,
79         },
80         {
81                 .start          = OMAP3430_ISP_CCDC_BASE,
82                 .end            = OMAP3430_ISP_CCDC_END,
83                 .flags          = IORESOURCE_MEM,
84         },
85         {
86                 .start          = OMAP3430_ISP_HIST_BASE,
87                 .end            = OMAP3430_ISP_HIST_END,
88                 .flags          = IORESOURCE_MEM,
89         },
90         {
91                 .start          = OMAP3430_ISP_H3A_BASE,
92                 .end            = OMAP3430_ISP_H3A_END,
93                 .flags          = IORESOURCE_MEM,
94         },
95         {
96                 .start          = OMAP3430_ISP_PREV_BASE,
97                 .end            = OMAP3430_ISP_PREV_END,
98                 .flags          = IORESOURCE_MEM,
99         },
100         {
101                 .start          = OMAP3430_ISP_RESZ_BASE,
102                 .end            = OMAP3430_ISP_RESZ_END,
103                 .flags          = IORESOURCE_MEM,
104         },
105         {
106                 .start          = OMAP3430_ISP_SBL_BASE,
107                 .end            = OMAP3430_ISP_SBL_END,
108                 .flags          = IORESOURCE_MEM,
109         },
110         {
111                 .start          = OMAP3430_ISP_CSI2A_BASE,
112                 .end            = OMAP3430_ISP_CSI2A_END,
113                 .flags          = IORESOURCE_MEM,
114         },
115         {
116                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
117                 .end            = OMAP3430_ISP_CSI2PHY_END,
118                 .flags          = IORESOURCE_MEM,
119         },
120         {
121                 .start          = INT_34XX_CAM_IRQ,
122                 .flags          = IORESOURCE_IRQ,
123         }
124 };
125
126 static struct platform_device omap3isp_device = {
127         .name           = "omap3isp",
128         .id             = -1,
129         .num_resources  = ARRAY_SIZE(omap3isp_resources),
130         .resource       = omap3isp_resources,
131 };
132
133 static inline void omap_init_camera(void)
134 {
135         platform_device_register(&omap3isp_device);
136 }
137 #else
138 static inline void omap_init_camera(void)
139 {
140 }
141 #endif
142
143 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
144
145 #define MBOX_REG_SIZE   0x120
146
147 #ifdef CONFIG_ARCH_OMAP2
148 static struct resource omap2_mbox_resources[] = {
149         {
150                 .start          = OMAP24XX_MAILBOX_BASE,
151                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
152                 .flags          = IORESOURCE_MEM,
153         },
154         {
155                 .start          = INT_24XX_MAIL_U0_MPU,
156                 .flags          = IORESOURCE_IRQ,
157                 .name           = "dsp",
158         },
159         {
160                 .start          = INT_24XX_MAIL_U3_MPU,
161                 .flags          = IORESOURCE_IRQ,
162                 .name           = "iva",
163         },
164 };
165 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
166 #else
167 #define omap2_mbox_resources            NULL
168 #define omap2_mbox_resources_sz         0
169 #endif
170
171 #ifdef CONFIG_ARCH_OMAP3
172 static struct resource omap3_mbox_resources[] = {
173         {
174                 .start          = OMAP34XX_MAILBOX_BASE,
175                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
176                 .flags          = IORESOURCE_MEM,
177         },
178         {
179                 .start          = INT_24XX_MAIL_U0_MPU,
180                 .flags          = IORESOURCE_IRQ,
181                 .name           = "dsp",
182         },
183 };
184 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
185 #else
186 #define omap3_mbox_resources            NULL
187 #define omap3_mbox_resources_sz         0
188 #endif
189
190 #ifdef CONFIG_ARCH_OMAP4
191
192 #define OMAP4_MBOX_REG_SIZE     0x130
193 static struct resource omap4_mbox_resources[] = {
194         {
195                 .start          = OMAP44XX_MAILBOX_BASE,
196                 .end            = OMAP44XX_MAILBOX_BASE +
197                                         OMAP4_MBOX_REG_SIZE - 1,
198                 .flags          = IORESOURCE_MEM,
199         },
200         {
201                 .start          = OMAP44XX_IRQ_MAIL_U0,
202                 .flags          = IORESOURCE_IRQ,
203                 .name           = "mbox",
204         },
205 };
206 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
207 #else
208 #define omap4_mbox_resources            NULL
209 #define omap4_mbox_resources_sz         0
210 #endif
211
212 static struct platform_device mbox_device = {
213         .name           = "omap-mailbox",
214         .id             = -1,
215 };
216
217 static inline void omap_init_mbox(void)
218 {
219         if (cpu_is_omap24xx()) {
220                 mbox_device.resource = omap2_mbox_resources;
221                 mbox_device.num_resources = omap2_mbox_resources_sz;
222         } else if (cpu_is_omap34xx()) {
223                 mbox_device.resource = omap3_mbox_resources;
224                 mbox_device.num_resources = omap3_mbox_resources_sz;
225         } else if (cpu_is_omap44xx()) {
226                 mbox_device.resource = omap4_mbox_resources;
227                 mbox_device.num_resources = omap4_mbox_resources_sz;
228         } else {
229                 pr_err("%s: platform not supported\n", __func__);
230                 return;
231         }
232         platform_device_register(&mbox_device);
233 }
234 #else
235 static inline void omap_init_mbox(void) { }
236 #endif /* CONFIG_OMAP_MBOX_FWK */
237
238 static inline void omap_init_sti(void) {}
239
240 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
241
242 #include <plat/mcspi.h>
243
244 #define OMAP2_MCSPI1_BASE               0x48098000
245 #define OMAP2_MCSPI2_BASE               0x4809a000
246 #define OMAP2_MCSPI3_BASE               0x480b8000
247 #define OMAP2_MCSPI4_BASE               0x480ba000
248
249 #define OMAP4_MCSPI1_BASE               0x48098100
250 #define OMAP4_MCSPI2_BASE               0x4809a100
251 #define OMAP4_MCSPI3_BASE               0x480b8100
252 #define OMAP4_MCSPI4_BASE               0x480ba100
253
254 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
255         .num_cs         = 4,
256 };
257
258 static struct resource omap2_mcspi1_resources[] = {
259         {
260                 .start          = OMAP2_MCSPI1_BASE,
261                 .end            = OMAP2_MCSPI1_BASE + 0xff,
262                 .flags          = IORESOURCE_MEM,
263         },
264 };
265
266 static struct platform_device omap2_mcspi1 = {
267         .name           = "omap2_mcspi",
268         .id             = 1,
269         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
270         .resource       = omap2_mcspi1_resources,
271         .dev            = {
272                 .platform_data = &omap2_mcspi1_config,
273         },
274 };
275
276 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
277         .num_cs         = 2,
278 };
279
280 static struct resource omap2_mcspi2_resources[] = {
281         {
282                 .start          = OMAP2_MCSPI2_BASE,
283                 .end            = OMAP2_MCSPI2_BASE + 0xff,
284                 .flags          = IORESOURCE_MEM,
285         },
286 };
287
288 static struct platform_device omap2_mcspi2 = {
289         .name           = "omap2_mcspi",
290         .id             = 2,
291         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
292         .resource       = omap2_mcspi2_resources,
293         .dev            = {
294                 .platform_data = &omap2_mcspi2_config,
295         },
296 };
297
298 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
299         defined(CONFIG_ARCH_OMAP4)
300 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
301         .num_cs         = 2,
302 };
303
304 static struct resource omap2_mcspi3_resources[] = {
305         {
306         .start          = OMAP2_MCSPI3_BASE,
307         .end            = OMAP2_MCSPI3_BASE + 0xff,
308         .flags          = IORESOURCE_MEM,
309         },
310 };
311
312 static struct platform_device omap2_mcspi3 = {
313         .name           = "omap2_mcspi",
314         .id             = 3,
315         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
316         .resource       = omap2_mcspi3_resources,
317         .dev            = {
318                 .platform_data = &omap2_mcspi3_config,
319         },
320 };
321 #endif
322
323 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
324 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
325         .num_cs         = 1,
326 };
327
328 static struct resource omap2_mcspi4_resources[] = {
329         {
330                 .start          = OMAP2_MCSPI4_BASE,
331                 .end            = OMAP2_MCSPI4_BASE + 0xff,
332                 .flags          = IORESOURCE_MEM,
333         },
334 };
335
336 static struct platform_device omap2_mcspi4 = {
337         .name           = "omap2_mcspi",
338         .id             = 4,
339         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
340         .resource       = omap2_mcspi4_resources,
341         .dev            = {
342                 .platform_data = &omap2_mcspi4_config,
343         },
344 };
345 #endif
346
347 #ifdef CONFIG_ARCH_OMAP4
348 static inline void omap4_mcspi_fixup(void)
349 {
350         omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
351         omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
352         omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
353         omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
354         omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
355         omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
356         omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
357         omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
358 }
359 #else
360 static inline void omap4_mcspi_fixup(void)
361 {
362 }
363 #endif
364
365 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
366         defined(CONFIG_ARCH_OMAP4)
367 static inline void omap2_mcspi3_init(void)
368 {
369         platform_device_register(&omap2_mcspi3);
370 }
371 #else
372 static inline void omap2_mcspi3_init(void)
373 {
374 }
375 #endif
376
377 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
378 static inline void omap2_mcspi4_init(void)
379 {
380         platform_device_register(&omap2_mcspi4);
381 }
382 #else
383 static inline void omap2_mcspi4_init(void)
384 {
385 }
386 #endif
387
388 static void omap_init_mcspi(void)
389 {
390         if (cpu_is_omap44xx())
391                 omap4_mcspi_fixup();
392
393         platform_device_register(&omap2_mcspi1);
394         platform_device_register(&omap2_mcspi2);
395
396         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
397                 omap2_mcspi3_init();
398
399         if (cpu_is_omap343x() || cpu_is_omap44xx())
400                 omap2_mcspi4_init();
401 }
402
403 #else
404 static inline void omap_init_mcspi(void) {}
405 #endif
406
407 static struct resource omap2_pmu_resource = {
408         .start  = 3,
409         .end    = 3,
410         .flags  = IORESOURCE_IRQ,
411 };
412
413 static struct resource omap3_pmu_resource = {
414         .start  = INT_34XX_BENCH_MPU_EMUL,
415         .end    = INT_34XX_BENCH_MPU_EMUL,
416         .flags  = IORESOURCE_IRQ,
417 };
418
419 static struct platform_device omap_pmu_device = {
420         .name           = "arm-pmu",
421         .id             = ARM_PMU_DEVICE_CPU,
422         .num_resources  = 1,
423 };
424
425 static void omap_init_pmu(void)
426 {
427         if (cpu_is_omap24xx())
428                 omap_pmu_device.resource = &omap2_pmu_resource;
429         else if (cpu_is_omap34xx())
430                 omap_pmu_device.resource = &omap3_pmu_resource;
431         else
432                 return;
433
434         platform_device_register(&omap_pmu_device);
435 }
436
437
438 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
439
440 #ifdef CONFIG_ARCH_OMAP2
441 static struct resource omap2_sham_resources[] = {
442         {
443                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
444                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
445                 .flags  = IORESOURCE_MEM,
446         },
447         {
448                 .start  = INT_24XX_SHA1MD5,
449                 .flags  = IORESOURCE_IRQ,
450         }
451 };
452 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
453 #else
454 #define omap2_sham_resources            NULL
455 #define omap2_sham_resources_sz         0
456 #endif
457
458 #ifdef CONFIG_ARCH_OMAP3
459 static struct resource omap3_sham_resources[] = {
460         {
461                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
462                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
463                 .flags  = IORESOURCE_MEM,
464         },
465         {
466                 .start  = INT_34XX_SHA1MD52_IRQ,
467                 .flags  = IORESOURCE_IRQ,
468         },
469         {
470                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
471                 .flags  = IORESOURCE_DMA,
472         }
473 };
474 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
475 #else
476 #define omap3_sham_resources            NULL
477 #define omap3_sham_resources_sz         0
478 #endif
479
480 static struct platform_device sham_device = {
481         .name           = "omap-sham",
482         .id             = -1,
483 };
484
485 static void omap_init_sham(void)
486 {
487         if (cpu_is_omap24xx()) {
488                 sham_device.resource = omap2_sham_resources;
489                 sham_device.num_resources = omap2_sham_resources_sz;
490         } else if (cpu_is_omap34xx()) {
491                 sham_device.resource = omap3_sham_resources;
492                 sham_device.num_resources = omap3_sham_resources_sz;
493         } else {
494                 pr_err("%s: platform not supported\n", __func__);
495                 return;
496         }
497         platform_device_register(&sham_device);
498 }
499 #else
500 static inline void omap_init_sham(void) { }
501 #endif
502
503 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
504
505 #ifdef CONFIG_ARCH_OMAP2
506 static struct resource omap2_aes_resources[] = {
507         {
508                 .start  = OMAP24XX_SEC_AES_BASE,
509                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
510                 .flags  = IORESOURCE_MEM,
511         },
512         {
513                 .start  = OMAP24XX_DMA_AES_TX,
514                 .flags  = IORESOURCE_DMA,
515         },
516         {
517                 .start  = OMAP24XX_DMA_AES_RX,
518                 .flags  = IORESOURCE_DMA,
519         }
520 };
521 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
522 #else
523 #define omap2_aes_resources             NULL
524 #define omap2_aes_resources_sz          0
525 #endif
526
527 #ifdef CONFIG_ARCH_OMAP3
528 static struct resource omap3_aes_resources[] = {
529         {
530                 .start  = OMAP34XX_SEC_AES_BASE,
531                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
532                 .flags  = IORESOURCE_MEM,
533         },
534         {
535                 .start  = OMAP34XX_DMA_AES2_TX,
536                 .flags  = IORESOURCE_DMA,
537         },
538         {
539                 .start  = OMAP34XX_DMA_AES2_RX,
540                 .flags  = IORESOURCE_DMA,
541         }
542 };
543 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
544 #else
545 #define omap3_aes_resources             NULL
546 #define omap3_aes_resources_sz          0
547 #endif
548
549 static struct platform_device aes_device = {
550         .name           = "omap-aes",
551         .id             = -1,
552 };
553
554 static void omap_init_aes(void)
555 {
556         if (cpu_is_omap24xx()) {
557                 aes_device.resource = omap2_aes_resources;
558                 aes_device.num_resources = omap2_aes_resources_sz;
559         } else if (cpu_is_omap34xx()) {
560                 aes_device.resource = omap3_aes_resources;
561                 aes_device.num_resources = omap3_aes_resources_sz;
562         } else {
563                 pr_err("%s: platform not supported\n", __func__);
564                 return;
565         }
566         platform_device_register(&aes_device);
567 }
568
569 #else
570 static inline void omap_init_aes(void) { }
571 #endif
572
573 /*-------------------------------------------------------------------------*/
574
575 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
576
577 #define MMCHS_SYSCONFIG                 0x0010
578 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
579 #define MMCHS_SYSSTATUS                 0x0014
580 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
581
582 static struct platform_device dummy_pdev = {
583         .dev = {
584                 .bus = &platform_bus_type,
585         },
586 };
587
588 /**
589  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
590  *
591  * Ensure that each MMC controller is fully reset.  Controllers
592  * left in an unknown state (by bootloader) may prevent retention
593  * or OFF-mode.  This is especially important in cases where the
594  * MMC driver is not enabled, _or_ built as a module.
595  *
596  * In order for reset to work, interface, functional and debounce
597  * clocks must be enabled.  The debounce clock comes from func_32k_clk
598  * and is not under SW control, so we only enable i- and f-clocks.
599  **/
600 static void __init omap_hsmmc_reset(void)
601 {
602         u32 i, nr_controllers;
603
604         if (cpu_is_omap242x())
605                 return;
606
607         nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
608                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
609
610         for (i = 0; i < nr_controllers; i++) {
611                 u32 v, base = 0;
612                 struct clk *iclk, *fclk;
613                 struct device *dev = &dummy_pdev.dev;
614
615                 switch (i) {
616                 case 0:
617                         base = OMAP2_MMC1_BASE;
618                         break;
619                 case 1:
620                         base = OMAP2_MMC2_BASE;
621                         break;
622                 case 2:
623                         base = OMAP3_MMC3_BASE;
624                         break;
625                 case 3:
626                         if (!cpu_is_omap44xx())
627                                 return;
628                         base = OMAP4_MMC4_BASE;
629                         break;
630                 case 4:
631                         if (!cpu_is_omap44xx())
632                                 return;
633                         base = OMAP4_MMC5_BASE;
634                         break;
635                 }
636
637                 if (cpu_is_omap44xx())
638                         base += OMAP4_MMC_REG_OFFSET;
639
640                 dummy_pdev.id = i;
641                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
642                 iclk = clk_get(dev, "ick");
643                 if (iclk && clk_enable(iclk))
644                         iclk = NULL;
645
646                 fclk = clk_get(dev, "fck");
647                 if (fclk && clk_enable(fclk))
648                         fclk = NULL;
649
650                 if (!iclk || !fclk) {
651                         printk(KERN_WARNING
652                                "%s: Unable to enable clocks for MMC%d, "
653                                "cannot reset.\n",  __func__, i);
654                         break;
655                 }
656
657                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
658                 v = omap_readl(base + MMCHS_SYSSTATUS);
659                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
660                          MMCHS_SYSSTATUS_RESETDONE))
661                         cpu_relax();
662
663                 if (fclk) {
664                         clk_disable(fclk);
665                         clk_put(fclk);
666                 }
667                 if (iclk) {
668                         clk_disable(iclk);
669                         clk_put(iclk);
670                 }
671         }
672 }
673 #else
674 static inline void omap_hsmmc_reset(void) {}
675 #endif
676
677 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
678         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
679
680 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
681                         int controller_nr)
682 {
683         if ((mmc_controller->slots[0].switch_pin > 0) && \
684                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
685                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
686                                         OMAP_PIN_INPUT_PULLUP);
687         if ((mmc_controller->slots[0].gpio_wp > 0) && \
688                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
689                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
690                                         OMAP_PIN_INPUT_PULLUP);
691
692         if (cpu_is_omap2420() && controller_nr == 0) {
693                 omap_mux_init_signal("sdmmc_cmd", 0);
694                 omap_mux_init_signal("sdmmc_clki", 0);
695                 omap_mux_init_signal("sdmmc_clko", 0);
696                 omap_mux_init_signal("sdmmc_dat0", 0);
697                 omap_mux_init_signal("sdmmc_dat_dir0", 0);
698                 omap_mux_init_signal("sdmmc_cmd_dir", 0);
699                 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
700                         omap_mux_init_signal("sdmmc_dat1", 0);
701                         omap_mux_init_signal("sdmmc_dat2", 0);
702                         omap_mux_init_signal("sdmmc_dat3", 0);
703                         omap_mux_init_signal("sdmmc_dat_dir1", 0);
704                         omap_mux_init_signal("sdmmc_dat_dir2", 0);
705                         omap_mux_init_signal("sdmmc_dat_dir3", 0);
706                 }
707
708                 /*
709                  * Use internal loop-back in MMC/SDIO Module Input Clock
710                  * selection
711                  */
712                 if (mmc_controller->slots[0].internal_clock) {
713                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
714                         v |= (1 << 24);
715                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
716                 }
717         }
718
719         if (cpu_is_omap34xx()) {
720                 if (controller_nr == 0) {
721                         omap_mux_init_signal("sdmmc1_clk",
722                                 OMAP_PIN_INPUT_PULLUP);
723                         omap_mux_init_signal("sdmmc1_cmd",
724                                 OMAP_PIN_INPUT_PULLUP);
725                         omap_mux_init_signal("sdmmc1_dat0",
726                                 OMAP_PIN_INPUT_PULLUP);
727                         if (mmc_controller->slots[0].caps &
728                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
729                                 omap_mux_init_signal("sdmmc1_dat1",
730                                         OMAP_PIN_INPUT_PULLUP);
731                                 omap_mux_init_signal("sdmmc1_dat2",
732                                         OMAP_PIN_INPUT_PULLUP);
733                                 omap_mux_init_signal("sdmmc1_dat3",
734                                         OMAP_PIN_INPUT_PULLUP);
735                         }
736                         if (mmc_controller->slots[0].caps &
737                                                 MMC_CAP_8_BIT_DATA) {
738                                 omap_mux_init_signal("sdmmc1_dat4",
739                                         OMAP_PIN_INPUT_PULLUP);
740                                 omap_mux_init_signal("sdmmc1_dat5",
741                                         OMAP_PIN_INPUT_PULLUP);
742                                 omap_mux_init_signal("sdmmc1_dat6",
743                                         OMAP_PIN_INPUT_PULLUP);
744                                 omap_mux_init_signal("sdmmc1_dat7",
745                                         OMAP_PIN_INPUT_PULLUP);
746                         }
747                 }
748                 if (controller_nr == 1) {
749                         /* MMC2 */
750                         omap_mux_init_signal("sdmmc2_clk",
751                                 OMAP_PIN_INPUT_PULLUP);
752                         omap_mux_init_signal("sdmmc2_cmd",
753                                 OMAP_PIN_INPUT_PULLUP);
754                         omap_mux_init_signal("sdmmc2_dat0",
755                                 OMAP_PIN_INPUT_PULLUP);
756
757                         /*
758                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
759                          * in the board-*.c files
760                          */
761                         if (mmc_controller->slots[0].caps &
762                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
763                                 omap_mux_init_signal("sdmmc2_dat1",
764                                         OMAP_PIN_INPUT_PULLUP);
765                                 omap_mux_init_signal("sdmmc2_dat2",
766                                         OMAP_PIN_INPUT_PULLUP);
767                                 omap_mux_init_signal("sdmmc2_dat3",
768                                         OMAP_PIN_INPUT_PULLUP);
769                         }
770                         if (mmc_controller->slots[0].caps &
771                                                         MMC_CAP_8_BIT_DATA) {
772                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
773                                         OMAP_PIN_INPUT_PULLUP);
774                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
775                                         OMAP_PIN_INPUT_PULLUP);
776                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
777                                         OMAP_PIN_INPUT_PULLUP);
778                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
779                                         OMAP_PIN_INPUT_PULLUP);
780                         }
781                 }
782
783                 /*
784                  * For MMC3 the pins need to be muxed in the board-*.c files
785                  */
786         }
787 }
788
789 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
790                         int nr_controllers)
791 {
792         int i;
793         char *name;
794
795         for (i = 0; i < nr_controllers; i++) {
796                 unsigned long base, size;
797                 unsigned int irq = 0;
798
799                 if (!mmc_data[i])
800                         continue;
801
802                 omap2_mmc_mux(mmc_data[i], i);
803
804                 switch (i) {
805                 case 0:
806                         base = OMAP2_MMC1_BASE;
807                         irq = INT_24XX_MMC_IRQ;
808                         break;
809                 case 1:
810                         base = OMAP2_MMC2_BASE;
811                         irq = INT_24XX_MMC2_IRQ;
812                         break;
813                 case 2:
814                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
815                                 return;
816                         base = OMAP3_MMC3_BASE;
817                         irq = INT_34XX_MMC3_IRQ;
818                         break;
819                 case 3:
820                         if (!cpu_is_omap44xx())
821                                 return;
822                         base = OMAP4_MMC4_BASE;
823                         irq = OMAP44XX_IRQ_MMC4;
824                         break;
825                 case 4:
826                         if (!cpu_is_omap44xx())
827                                 return;
828                         base = OMAP4_MMC5_BASE;
829                         irq = OMAP44XX_IRQ_MMC5;
830                         break;
831                 default:
832                         continue;
833                 }
834
835                 if (cpu_is_omap2420()) {
836                         size = OMAP2420_MMC_SIZE;
837                         name = "mmci-omap";
838                 } else if (cpu_is_omap44xx()) {
839                         if (i < 3)
840                                 irq += OMAP44XX_IRQ_GIC_START;
841                         size = OMAP4_HSMMC_SIZE;
842                         name = "mmci-omap-hs";
843                 } else {
844                         size = OMAP3_HSMMC_SIZE;
845                         name = "mmci-omap-hs";
846                 }
847                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
848         };
849 }
850
851 #endif
852
853 /*-------------------------------------------------------------------------*/
854
855 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
856 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
857 #define OMAP_HDQ_BASE   0x480B2000
858 #endif
859 static struct resource omap_hdq_resources[] = {
860         {
861                 .start          = OMAP_HDQ_BASE,
862                 .end            = OMAP_HDQ_BASE + 0x1C,
863                 .flags          = IORESOURCE_MEM,
864         },
865         {
866                 .start          = INT_24XX_HDQ_IRQ,
867                 .flags          = IORESOURCE_IRQ,
868         },
869 };
870 static struct platform_device omap_hdq_dev = {
871         .name = "omap_hdq",
872         .id = 0,
873         .dev = {
874                 .platform_data = NULL,
875         },
876         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
877         .resource       = omap_hdq_resources,
878 };
879 static inline void omap_hdq_init(void)
880 {
881         (void) platform_device_register(&omap_hdq_dev);
882 }
883 #else
884 static inline void omap_hdq_init(void) {}
885 #endif
886
887 /*---------------------------------------------------------------------------*/
888
889 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
890         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
891 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
892 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
893 };
894 #else
895 static struct resource omap_vout_resource[2] = {
896 };
897 #endif
898
899 static struct platform_device omap_vout_device = {
900         .name           = "omap_vout",
901         .num_resources  = ARRAY_SIZE(omap_vout_resource),
902         .resource       = &omap_vout_resource[0],
903         .id             = -1,
904 };
905 static void omap_init_vout(void)
906 {
907         if (platform_device_register(&omap_vout_device) < 0)
908                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
909 }
910 #else
911 static inline void omap_init_vout(void) {}
912 #endif
913
914 /*-------------------------------------------------------------------------*/
915
916 /*
917  * Inorder to avoid any assumptions from bootloader regarding WDT
918  * settings, WDT module is reset during init. This enables the watchdog
919  * timer. Hence it is required to disable the watchdog after the WDT reset
920  * during init. Otherwise the system would reboot as per the default
921  * watchdog timer registers settings.
922  */
923 #define OMAP_WDT_WPS    (0x34)
924 #define OMAP_WDT_SPR    (0x48)
925
926 static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
927 {
928         void __iomem *base;
929         int ret;
930
931         if (!oh) {
932                 pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
933                 return -EINVAL;
934         }
935
936         base = omap_hwmod_get_mpu_rt_va(oh);
937         if (!base) {
938                 pr_err("%s: Could not get the base address for %s\n",
939                                 oh->name, __func__);
940                 return -EINVAL;
941         }
942
943         /* Enable the clocks before accessing the WDT registers */
944         ret = omap_hwmod_enable(oh);
945         if (ret) {
946                 pr_err("%s: Could not enable clocks for %s\n",
947                                 oh->name, __func__);
948                 return ret;
949         }
950
951         /* sequence required to disable watchdog */
952         __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
953         while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
954                 cpu_relax();
955
956         __raw_writel(0x5555, base + OMAP_WDT_SPR);
957         while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
958                 cpu_relax();
959
960         ret = omap_hwmod_idle(oh);
961         if (ret)
962                 pr_err("%s: Could not disable clocks for %s\n",
963                                 oh->name, __func__);
964
965         return ret;
966 }
967
968 static void __init omap_disable_wdt(void)
969 {
970         if (cpu_class_is_omap2())
971                 omap_hwmod_for_each_by_class("wd_timer",
972                                                 omap2_disable_wdt, NULL);
973         return;
974 }
975
976 static int __init omap2_init_devices(void)
977 {
978         /* please keep these calls, and their implementations above,
979          * in alphabetical order so they're easier to sort through.
980          */
981         omap_disable_wdt();
982         omap_hsmmc_reset();
983         omap_init_camera();
984         omap_init_mbox();
985         omap_init_mcspi();
986         omap_init_pmu();
987         omap_hdq_init();
988         omap_init_sti();
989         omap_init_sham();
990         omap_init_aes();
991         omap_init_vout();
992
993         return 0;
994 }
995 arch_initcall(omap2_init_devices);
996
997 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
998 struct omap_device_pm_latency omap_wdt_latency[] = {
999         [0] = {
1000                 .deactivate_func = omap_device_idle_hwmods,
1001                 .activate_func   = omap_device_enable_hwmods,
1002                 .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
1003         },
1004 };
1005
1006 static int __init omap_init_wdt(void)
1007 {
1008         int id = -1;
1009         struct omap_device *od;
1010         struct omap_hwmod *oh;
1011         char *oh_name = "wd_timer2";
1012         char *dev_name = "omap_wdt";
1013
1014         if (!cpu_class_is_omap2())
1015                 return 0;
1016
1017         oh = omap_hwmod_lookup(oh_name);
1018         if (!oh) {
1019                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1020                 return -EINVAL;
1021         }
1022
1023         od = omap_device_build(dev_name, id, oh, NULL, 0,
1024                                 omap_wdt_latency,
1025                                 ARRAY_SIZE(omap_wdt_latency), 0);
1026         WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
1027                                 dev_name, oh->name);
1028         return 0;
1029 }
1030 subsys_initcall(omap_init_wdt);
1031 #endif