818452ac905d5f568c896ddbd0cdec7a9a49c358
[linux-2.6.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19
20 #include <mach/hardware.h>
21 #include <mach/irqs.h>
22 #include <asm/mach-types.h>
23 #include <asm/mach/map.h>
24 #include <asm/pmu.h>
25
26 #include <plat/control.h>
27 #include <plat/tc.h>
28 #include <plat/board.h>
29 #include <mach/gpio.h>
30 #include <plat/mmc.h>
31 #include <plat/dma.h>
32 #include <plat/omap_hwmod.h>
33 #include <plat/omap_device.h>
34
35 #include "mux.h"
36
37 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
38
39 static struct resource cam_resources[] = {
40         {
41                 .start          = OMAP24XX_CAMERA_BASE,
42                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
43                 .flags          = IORESOURCE_MEM,
44         },
45         {
46                 .start          = INT_24XX_CAM_IRQ,
47                 .flags          = IORESOURCE_IRQ,
48         }
49 };
50
51 static struct platform_device omap_cam_device = {
52         .name           = "omap24xxcam",
53         .id             = -1,
54         .num_resources  = ARRAY_SIZE(cam_resources),
55         .resource       = cam_resources,
56 };
57
58 static inline void omap_init_camera(void)
59 {
60         platform_device_register(&omap_cam_device);
61 }
62
63 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
64
65 static struct resource omap3isp_resources[] = {
66         {
67                 .start          = OMAP3430_ISP_BASE,
68                 .end            = OMAP3430_ISP_END,
69                 .flags          = IORESOURCE_MEM,
70         },
71         {
72                 .start          = OMAP3430_ISP_CBUFF_BASE,
73                 .end            = OMAP3430_ISP_CBUFF_END,
74                 .flags          = IORESOURCE_MEM,
75         },
76         {
77                 .start          = OMAP3430_ISP_CCP2_BASE,
78                 .end            = OMAP3430_ISP_CCP2_END,
79                 .flags          = IORESOURCE_MEM,
80         },
81         {
82                 .start          = OMAP3430_ISP_CCDC_BASE,
83                 .end            = OMAP3430_ISP_CCDC_END,
84                 .flags          = IORESOURCE_MEM,
85         },
86         {
87                 .start          = OMAP3430_ISP_HIST_BASE,
88                 .end            = OMAP3430_ISP_HIST_END,
89                 .flags          = IORESOURCE_MEM,
90         },
91         {
92                 .start          = OMAP3430_ISP_H3A_BASE,
93                 .end            = OMAP3430_ISP_H3A_END,
94                 .flags          = IORESOURCE_MEM,
95         },
96         {
97                 .start          = OMAP3430_ISP_PREV_BASE,
98                 .end            = OMAP3430_ISP_PREV_END,
99                 .flags          = IORESOURCE_MEM,
100         },
101         {
102                 .start          = OMAP3430_ISP_RESZ_BASE,
103                 .end            = OMAP3430_ISP_RESZ_END,
104                 .flags          = IORESOURCE_MEM,
105         },
106         {
107                 .start          = OMAP3430_ISP_SBL_BASE,
108                 .end            = OMAP3430_ISP_SBL_END,
109                 .flags          = IORESOURCE_MEM,
110         },
111         {
112                 .start          = OMAP3430_ISP_CSI2A_BASE,
113                 .end            = OMAP3430_ISP_CSI2A_END,
114                 .flags          = IORESOURCE_MEM,
115         },
116         {
117                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
118                 .end            = OMAP3430_ISP_CSI2PHY_END,
119                 .flags          = IORESOURCE_MEM,
120         },
121         {
122                 .start          = INT_34XX_CAM_IRQ,
123                 .flags          = IORESOURCE_IRQ,
124         }
125 };
126
127 static struct platform_device omap3isp_device = {
128         .name           = "omap3isp",
129         .id             = -1,
130         .num_resources  = ARRAY_SIZE(omap3isp_resources),
131         .resource       = omap3isp_resources,
132 };
133
134 static inline void omap_init_camera(void)
135 {
136         platform_device_register(&omap3isp_device);
137 }
138 #else
139 static inline void omap_init_camera(void)
140 {
141 }
142 #endif
143
144 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
145
146 #define MBOX_REG_SIZE   0x120
147
148 #ifdef CONFIG_ARCH_OMAP2
149 static struct resource omap2_mbox_resources[] = {
150         {
151                 .start          = OMAP24XX_MAILBOX_BASE,
152                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
153                 .flags          = IORESOURCE_MEM,
154         },
155         {
156                 .start          = INT_24XX_MAIL_U0_MPU,
157                 .flags          = IORESOURCE_IRQ,
158                 .name           = "dsp",
159         },
160         {
161                 .start          = INT_24XX_MAIL_U3_MPU,
162                 .flags          = IORESOURCE_IRQ,
163                 .name           = "iva",
164         },
165 };
166 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
167 #else
168 #define omap2_mbox_resources            NULL
169 #define omap2_mbox_resources_sz         0
170 #endif
171
172 #ifdef CONFIG_ARCH_OMAP3
173 static struct resource omap3_mbox_resources[] = {
174         {
175                 .start          = OMAP34XX_MAILBOX_BASE,
176                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
177                 .flags          = IORESOURCE_MEM,
178         },
179         {
180                 .start          = INT_24XX_MAIL_U0_MPU,
181                 .flags          = IORESOURCE_IRQ,
182                 .name           = "dsp",
183         },
184 };
185 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
186 #else
187 #define omap3_mbox_resources            NULL
188 #define omap3_mbox_resources_sz         0
189 #endif
190
191 #ifdef CONFIG_ARCH_OMAP4
192
193 #define OMAP4_MBOX_REG_SIZE     0x130
194 static struct resource omap4_mbox_resources[] = {
195         {
196                 .start          = OMAP44XX_MAILBOX_BASE,
197                 .end            = OMAP44XX_MAILBOX_BASE +
198                                         OMAP4_MBOX_REG_SIZE - 1,
199                 .flags          = IORESOURCE_MEM,
200         },
201         {
202                 .start          = OMAP44XX_IRQ_MAIL_U0,
203                 .flags          = IORESOURCE_IRQ,
204                 .name           = "mbox",
205         },
206 };
207 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
208 #else
209 #define omap4_mbox_resources            NULL
210 #define omap4_mbox_resources_sz         0
211 #endif
212
213 static struct platform_device mbox_device = {
214         .name           = "omap-mailbox",
215         .id             = -1,
216 };
217
218 static inline void omap_init_mbox(void)
219 {
220         if (cpu_is_omap24xx()) {
221                 mbox_device.resource = omap2_mbox_resources;
222                 mbox_device.num_resources = omap2_mbox_resources_sz;
223         } else if (cpu_is_omap34xx()) {
224                 mbox_device.resource = omap3_mbox_resources;
225                 mbox_device.num_resources = omap3_mbox_resources_sz;
226         } else if (cpu_is_omap44xx()) {
227                 mbox_device.resource = omap4_mbox_resources;
228                 mbox_device.num_resources = omap4_mbox_resources_sz;
229         } else {
230                 pr_err("%s: platform not supported\n", __func__);
231                 return;
232         }
233         platform_device_register(&mbox_device);
234 }
235 #else
236 static inline void omap_init_mbox(void) { }
237 #endif /* CONFIG_OMAP_MBOX_FWK */
238
239 static inline void omap_init_sti(void) {}
240
241 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
242
243 #include <plat/mcspi.h>
244
245 #define OMAP2_MCSPI1_BASE               0x48098000
246 #define OMAP2_MCSPI2_BASE               0x4809a000
247 #define OMAP2_MCSPI3_BASE               0x480b8000
248 #define OMAP2_MCSPI4_BASE               0x480ba000
249
250 #define OMAP4_MCSPI1_BASE               0x48098100
251 #define OMAP4_MCSPI2_BASE               0x4809a100
252 #define OMAP4_MCSPI3_BASE               0x480b8100
253 #define OMAP4_MCSPI4_BASE               0x480ba100
254
255 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
256         .num_cs         = 4,
257 };
258
259 static struct resource omap2_mcspi1_resources[] = {
260         {
261                 .start          = OMAP2_MCSPI1_BASE,
262                 .end            = OMAP2_MCSPI1_BASE + 0xff,
263                 .flags          = IORESOURCE_MEM,
264         },
265 };
266
267 static struct platform_device omap2_mcspi1 = {
268         .name           = "omap2_mcspi",
269         .id             = 1,
270         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
271         .resource       = omap2_mcspi1_resources,
272         .dev            = {
273                 .platform_data = &omap2_mcspi1_config,
274         },
275 };
276
277 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
278         .num_cs         = 2,
279 };
280
281 static struct resource omap2_mcspi2_resources[] = {
282         {
283                 .start          = OMAP2_MCSPI2_BASE,
284                 .end            = OMAP2_MCSPI2_BASE + 0xff,
285                 .flags          = IORESOURCE_MEM,
286         },
287 };
288
289 static struct platform_device omap2_mcspi2 = {
290         .name           = "omap2_mcspi",
291         .id             = 2,
292         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
293         .resource       = omap2_mcspi2_resources,
294         .dev            = {
295                 .platform_data = &omap2_mcspi2_config,
296         },
297 };
298
299 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
300         defined(CONFIG_ARCH_OMAP4)
301 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
302         .num_cs         = 2,
303 };
304
305 static struct resource omap2_mcspi3_resources[] = {
306         {
307         .start          = OMAP2_MCSPI3_BASE,
308         .end            = OMAP2_MCSPI3_BASE + 0xff,
309         .flags          = IORESOURCE_MEM,
310         },
311 };
312
313 static struct platform_device omap2_mcspi3 = {
314         .name           = "omap2_mcspi",
315         .id             = 3,
316         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
317         .resource       = omap2_mcspi3_resources,
318         .dev            = {
319                 .platform_data = &omap2_mcspi3_config,
320         },
321 };
322 #endif
323
324 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
325 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
326         .num_cs         = 1,
327 };
328
329 static struct resource omap2_mcspi4_resources[] = {
330         {
331                 .start          = OMAP2_MCSPI4_BASE,
332                 .end            = OMAP2_MCSPI4_BASE + 0xff,
333                 .flags          = IORESOURCE_MEM,
334         },
335 };
336
337 static struct platform_device omap2_mcspi4 = {
338         .name           = "omap2_mcspi",
339         .id             = 4,
340         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
341         .resource       = omap2_mcspi4_resources,
342         .dev            = {
343                 .platform_data = &omap2_mcspi4_config,
344         },
345 };
346 #endif
347
348 #ifdef CONFIG_ARCH_OMAP4
349 static inline void omap4_mcspi_fixup(void)
350 {
351         omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
352         omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
353         omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
354         omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
355         omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
356         omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
357         omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
358         omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
359 }
360 #else
361 static inline void omap4_mcspi_fixup(void)
362 {
363 }
364 #endif
365
366 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
367         defined(CONFIG_ARCH_OMAP4)
368 static inline void omap2_mcspi3_init(void)
369 {
370         platform_device_register(&omap2_mcspi3);
371 }
372 #else
373 static inline void omap2_mcspi3_init(void)
374 {
375 }
376 #endif
377
378 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
379 static inline void omap2_mcspi4_init(void)
380 {
381         platform_device_register(&omap2_mcspi4);
382 }
383 #else
384 static inline void omap2_mcspi4_init(void)
385 {
386 }
387 #endif
388
389 static void omap_init_mcspi(void)
390 {
391         if (cpu_is_omap44xx())
392                 omap4_mcspi_fixup();
393
394         platform_device_register(&omap2_mcspi1);
395         platform_device_register(&omap2_mcspi2);
396
397         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
398                 omap2_mcspi3_init();
399
400         if (cpu_is_omap343x() || cpu_is_omap44xx())
401                 omap2_mcspi4_init();
402 }
403
404 #else
405 static inline void omap_init_mcspi(void) {}
406 #endif
407
408 static struct resource omap2_pmu_resource = {
409         .start  = 3,
410         .end    = 3,
411         .flags  = IORESOURCE_IRQ,
412 };
413
414 static struct resource omap3_pmu_resource = {
415         .start  = INT_34XX_BENCH_MPU_EMUL,
416         .end    = INT_34XX_BENCH_MPU_EMUL,
417         .flags  = IORESOURCE_IRQ,
418 };
419
420 static struct platform_device omap_pmu_device = {
421         .name           = "arm-pmu",
422         .id             = ARM_PMU_DEVICE_CPU,
423         .num_resources  = 1,
424 };
425
426 static void omap_init_pmu(void)
427 {
428         if (cpu_is_omap24xx())
429                 omap_pmu_device.resource = &omap2_pmu_resource;
430         else if (cpu_is_omap34xx())
431                 omap_pmu_device.resource = &omap3_pmu_resource;
432         else
433                 return;
434
435         platform_device_register(&omap_pmu_device);
436 }
437
438
439 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
440
441 #ifdef CONFIG_ARCH_OMAP2
442 static struct resource omap2_sham_resources[] = {
443         {
444                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
445                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
446                 .flags  = IORESOURCE_MEM,
447         },
448         {
449                 .start  = INT_24XX_SHA1MD5,
450                 .flags  = IORESOURCE_IRQ,
451         }
452 };
453 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
454 #else
455 #define omap2_sham_resources            NULL
456 #define omap2_sham_resources_sz         0
457 #endif
458
459 #ifdef CONFIG_ARCH_OMAP3
460 static struct resource omap3_sham_resources[] = {
461         {
462                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
463                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
464                 .flags  = IORESOURCE_MEM,
465         },
466         {
467                 .start  = INT_34XX_SHA1MD52_IRQ,
468                 .flags  = IORESOURCE_IRQ,
469         },
470         {
471                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
472                 .flags  = IORESOURCE_DMA,
473         }
474 };
475 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
476 #else
477 #define omap3_sham_resources            NULL
478 #define omap3_sham_resources_sz         0
479 #endif
480
481 static struct platform_device sham_device = {
482         .name           = "omap-sham",
483         .id             = -1,
484 };
485
486 static void omap_init_sham(void)
487 {
488         if (cpu_is_omap24xx()) {
489                 sham_device.resource = omap2_sham_resources;
490                 sham_device.num_resources = omap2_sham_resources_sz;
491         } else if (cpu_is_omap34xx()) {
492                 sham_device.resource = omap3_sham_resources;
493                 sham_device.num_resources = omap3_sham_resources_sz;
494         } else {
495                 pr_err("%s: platform not supported\n", __func__);
496                 return;
497         }
498         platform_device_register(&sham_device);
499 }
500 #else
501 static inline void omap_init_sham(void) { }
502 #endif
503
504 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
505
506 #ifdef CONFIG_ARCH_OMAP2
507 static struct resource omap2_aes_resources[] = {
508         {
509                 .start  = OMAP24XX_SEC_AES_BASE,
510                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
511                 .flags  = IORESOURCE_MEM,
512         },
513         {
514                 .start  = OMAP24XX_DMA_AES_TX,
515                 .flags  = IORESOURCE_DMA,
516         },
517         {
518                 .start  = OMAP24XX_DMA_AES_RX,
519                 .flags  = IORESOURCE_DMA,
520         }
521 };
522 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
523 #else
524 #define omap2_aes_resources             NULL
525 #define omap2_aes_resources_sz          0
526 #endif
527
528 #ifdef CONFIG_ARCH_OMAP3
529 static struct resource omap3_aes_resources[] = {
530         {
531                 .start  = OMAP34XX_SEC_AES_BASE,
532                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
533                 .flags  = IORESOURCE_MEM,
534         },
535         {
536                 .start  = OMAP34XX_DMA_AES2_TX,
537                 .flags  = IORESOURCE_DMA,
538         },
539         {
540                 .start  = OMAP34XX_DMA_AES2_RX,
541                 .flags  = IORESOURCE_DMA,
542         }
543 };
544 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
545 #else
546 #define omap3_aes_resources             NULL
547 #define omap3_aes_resources_sz          0
548 #endif
549
550 static struct platform_device aes_device = {
551         .name           = "omap-aes",
552         .id             = -1,
553 };
554
555 static void omap_init_aes(void)
556 {
557         if (cpu_is_omap24xx()) {
558                 aes_device.resource = omap2_aes_resources;
559                 aes_device.num_resources = omap2_aes_resources_sz;
560         } else if (cpu_is_omap34xx()) {
561                 aes_device.resource = omap3_aes_resources;
562                 aes_device.num_resources = omap3_aes_resources_sz;
563         } else {
564                 pr_err("%s: platform not supported\n", __func__);
565                 return;
566         }
567         platform_device_register(&aes_device);
568 }
569
570 #else
571 static inline void omap_init_aes(void) { }
572 #endif
573
574 /*-------------------------------------------------------------------------*/
575
576 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
577
578 #define MMCHS_SYSCONFIG                 0x0010
579 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
580 #define MMCHS_SYSSTATUS                 0x0014
581 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
582
583 static struct platform_device dummy_pdev = {
584         .dev = {
585                 .bus = &platform_bus_type,
586         },
587 };
588
589 /**
590  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
591  *
592  * Ensure that each MMC controller is fully reset.  Controllers
593  * left in an unknown state (by bootloader) may prevent retention
594  * or OFF-mode.  This is especially important in cases where the
595  * MMC driver is not enabled, _or_ built as a module.
596  *
597  * In order for reset to work, interface, functional and debounce
598  * clocks must be enabled.  The debounce clock comes from func_32k_clk
599  * and is not under SW control, so we only enable i- and f-clocks.
600  **/
601 static void __init omap_hsmmc_reset(void)
602 {
603         u32 i, nr_controllers;
604
605         if (cpu_is_omap242x())
606                 return;
607
608         nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
609                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
610
611         for (i = 0; i < nr_controllers; i++) {
612                 u32 v, base = 0;
613                 struct clk *iclk, *fclk;
614                 struct device *dev = &dummy_pdev.dev;
615
616                 switch (i) {
617                 case 0:
618                         base = OMAP2_MMC1_BASE;
619                         break;
620                 case 1:
621                         base = OMAP2_MMC2_BASE;
622                         break;
623                 case 2:
624                         base = OMAP3_MMC3_BASE;
625                         break;
626                 case 3:
627                         if (!cpu_is_omap44xx())
628                                 return;
629                         base = OMAP4_MMC4_BASE;
630                         break;
631                 case 4:
632                         if (!cpu_is_omap44xx())
633                                 return;
634                         base = OMAP4_MMC5_BASE;
635                         break;
636                 }
637
638                 if (cpu_is_omap44xx())
639                         base += OMAP4_MMC_REG_OFFSET;
640
641                 dummy_pdev.id = i;
642                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
643                 iclk = clk_get(dev, "ick");
644                 if (iclk && clk_enable(iclk))
645                         iclk = NULL;
646
647                 fclk = clk_get(dev, "fck");
648                 if (fclk && clk_enable(fclk))
649                         fclk = NULL;
650
651                 if (!iclk || !fclk) {
652                         printk(KERN_WARNING
653                                "%s: Unable to enable clocks for MMC%d, "
654                                "cannot reset.\n",  __func__, i);
655                         break;
656                 }
657
658                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
659                 v = omap_readl(base + MMCHS_SYSSTATUS);
660                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
661                          MMCHS_SYSSTATUS_RESETDONE))
662                         cpu_relax();
663
664                 if (fclk) {
665                         clk_disable(fclk);
666                         clk_put(fclk);
667                 }
668                 if (iclk) {
669                         clk_disable(iclk);
670                         clk_put(iclk);
671                 }
672         }
673 }
674 #else
675 static inline void omap_hsmmc_reset(void) {}
676 #endif
677
678 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
679         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
680
681 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
682                         int controller_nr)
683 {
684         if ((mmc_controller->slots[0].switch_pin > 0) && \
685                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
686                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
687                                         OMAP_PIN_INPUT_PULLUP);
688         if ((mmc_controller->slots[0].gpio_wp > 0) && \
689                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
690                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
691                                         OMAP_PIN_INPUT_PULLUP);
692
693         if (cpu_is_omap2420() && controller_nr == 0) {
694                 omap_mux_init_signal("sdmmc_cmd", 0);
695                 omap_mux_init_signal("sdmmc_clki", 0);
696                 omap_mux_init_signal("sdmmc_clko", 0);
697                 omap_mux_init_signal("sdmmc_dat0", 0);
698                 omap_mux_init_signal("sdmmc_dat_dir0", 0);
699                 omap_mux_init_signal("sdmmc_cmd_dir", 0);
700                 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
701                         omap_mux_init_signal("sdmmc_dat1", 0);
702                         omap_mux_init_signal("sdmmc_dat2", 0);
703                         omap_mux_init_signal("sdmmc_dat3", 0);
704                         omap_mux_init_signal("sdmmc_dat_dir1", 0);
705                         omap_mux_init_signal("sdmmc_dat_dir2", 0);
706                         omap_mux_init_signal("sdmmc_dat_dir3", 0);
707                 }
708
709                 /*
710                  * Use internal loop-back in MMC/SDIO Module Input Clock
711                  * selection
712                  */
713                 if (mmc_controller->slots[0].internal_clock) {
714                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
715                         v |= (1 << 24);
716                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
717                 }
718         }
719
720         if (cpu_is_omap34xx()) {
721                 if (controller_nr == 0) {
722                         omap_mux_init_signal("sdmmc1_clk",
723                                 OMAP_PIN_INPUT_PULLUP);
724                         omap_mux_init_signal("sdmmc1_cmd",
725                                 OMAP_PIN_INPUT_PULLUP);
726                         omap_mux_init_signal("sdmmc1_dat0",
727                                 OMAP_PIN_INPUT_PULLUP);
728                         if (mmc_controller->slots[0].caps &
729                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
730                                 omap_mux_init_signal("sdmmc1_dat1",
731                                         OMAP_PIN_INPUT_PULLUP);
732                                 omap_mux_init_signal("sdmmc1_dat2",
733                                         OMAP_PIN_INPUT_PULLUP);
734                                 omap_mux_init_signal("sdmmc1_dat3",
735                                         OMAP_PIN_INPUT_PULLUP);
736                         }
737                         if (mmc_controller->slots[0].caps &
738                                                 MMC_CAP_8_BIT_DATA) {
739                                 omap_mux_init_signal("sdmmc1_dat4",
740                                         OMAP_PIN_INPUT_PULLUP);
741                                 omap_mux_init_signal("sdmmc1_dat5",
742                                         OMAP_PIN_INPUT_PULLUP);
743                                 omap_mux_init_signal("sdmmc1_dat6",
744                                         OMAP_PIN_INPUT_PULLUP);
745                                 omap_mux_init_signal("sdmmc1_dat7",
746                                         OMAP_PIN_INPUT_PULLUP);
747                         }
748                 }
749                 if (controller_nr == 1) {
750                         /* MMC2 */
751                         omap_mux_init_signal("sdmmc2_clk",
752                                 OMAP_PIN_INPUT_PULLUP);
753                         omap_mux_init_signal("sdmmc2_cmd",
754                                 OMAP_PIN_INPUT_PULLUP);
755                         omap_mux_init_signal("sdmmc2_dat0",
756                                 OMAP_PIN_INPUT_PULLUP);
757
758                         /*
759                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
760                          * in the board-*.c files
761                          */
762                         if (mmc_controller->slots[0].caps &
763                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
764                                 omap_mux_init_signal("sdmmc2_dat1",
765                                         OMAP_PIN_INPUT_PULLUP);
766                                 omap_mux_init_signal("sdmmc2_dat2",
767                                         OMAP_PIN_INPUT_PULLUP);
768                                 omap_mux_init_signal("sdmmc2_dat3",
769                                         OMAP_PIN_INPUT_PULLUP);
770                         }
771                         if (mmc_controller->slots[0].caps &
772                                                         MMC_CAP_8_BIT_DATA) {
773                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
774                                         OMAP_PIN_INPUT_PULLUP);
775                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
776                                         OMAP_PIN_INPUT_PULLUP);
777                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
778                                         OMAP_PIN_INPUT_PULLUP);
779                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
780                                         OMAP_PIN_INPUT_PULLUP);
781                         }
782                 }
783
784                 /*
785                  * For MMC3 the pins need to be muxed in the board-*.c files
786                  */
787         }
788 }
789
790 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
791                         int nr_controllers)
792 {
793         int i;
794         char *name;
795
796         for (i = 0; i < nr_controllers; i++) {
797                 unsigned long base, size;
798                 unsigned int irq = 0;
799
800                 if (!mmc_data[i])
801                         continue;
802
803                 omap2_mmc_mux(mmc_data[i], i);
804
805                 switch (i) {
806                 case 0:
807                         base = OMAP2_MMC1_BASE;
808                         irq = INT_24XX_MMC_IRQ;
809                         break;
810                 case 1:
811                         base = OMAP2_MMC2_BASE;
812                         irq = INT_24XX_MMC2_IRQ;
813                         break;
814                 case 2:
815                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
816                                 return;
817                         base = OMAP3_MMC3_BASE;
818                         irq = INT_34XX_MMC3_IRQ;
819                         break;
820                 case 3:
821                         if (!cpu_is_omap44xx())
822                                 return;
823                         base = OMAP4_MMC4_BASE;
824                         irq = OMAP44XX_IRQ_MMC4;
825                         break;
826                 case 4:
827                         if (!cpu_is_omap44xx())
828                                 return;
829                         base = OMAP4_MMC5_BASE;
830                         irq = OMAP44XX_IRQ_MMC5;
831                         break;
832                 default:
833                         continue;
834                 }
835
836                 if (cpu_is_omap2420()) {
837                         size = OMAP2420_MMC_SIZE;
838                         name = "mmci-omap";
839                 } else if (cpu_is_omap44xx()) {
840                         if (i < 3)
841                                 irq += OMAP44XX_IRQ_GIC_START;
842                         size = OMAP4_HSMMC_SIZE;
843                         name = "mmci-omap-hs";
844                 } else {
845                         size = OMAP3_HSMMC_SIZE;
846                         name = "mmci-omap-hs";
847                 }
848                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
849         };
850 }
851
852 #endif
853
854 /*-------------------------------------------------------------------------*/
855
856 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
857 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
858 #define OMAP_HDQ_BASE   0x480B2000
859 #endif
860 static struct resource omap_hdq_resources[] = {
861         {
862                 .start          = OMAP_HDQ_BASE,
863                 .end            = OMAP_HDQ_BASE + 0x1C,
864                 .flags          = IORESOURCE_MEM,
865         },
866         {
867                 .start          = INT_24XX_HDQ_IRQ,
868                 .flags          = IORESOURCE_IRQ,
869         },
870 };
871 static struct platform_device omap_hdq_dev = {
872         .name = "omap_hdq",
873         .id = 0,
874         .dev = {
875                 .platform_data = NULL,
876         },
877         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
878         .resource       = omap_hdq_resources,
879 };
880 static inline void omap_hdq_init(void)
881 {
882         (void) platform_device_register(&omap_hdq_dev);
883 }
884 #else
885 static inline void omap_hdq_init(void) {}
886 #endif
887
888 /*---------------------------------------------------------------------------*/
889
890 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
891         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
892 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
893 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
894 };
895 #else
896 static struct resource omap_vout_resource[2] = {
897 };
898 #endif
899
900 static struct platform_device omap_vout_device = {
901         .name           = "omap_vout",
902         .num_resources  = ARRAY_SIZE(omap_vout_resource),
903         .resource       = &omap_vout_resource[0],
904         .id             = -1,
905 };
906 static void omap_init_vout(void)
907 {
908         if (platform_device_register(&omap_vout_device) < 0)
909                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
910 }
911 #else
912 static inline void omap_init_vout(void) {}
913 #endif
914
915 /*-------------------------------------------------------------------------*/
916
917 /*
918  * Inorder to avoid any assumptions from bootloader regarding WDT
919  * settings, WDT module is reset during init. This enables the watchdog
920  * timer. Hence it is required to disable the watchdog after the WDT reset
921  * during init. Otherwise the system would reboot as per the default
922  * watchdog timer registers settings.
923  */
924 #define OMAP_WDT_WPS    (0x34)
925 #define OMAP_WDT_SPR    (0x48)
926
927 static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
928 {
929         void __iomem *base;
930         int ret;
931
932         if (!oh) {
933                 pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
934                 return -EINVAL;
935         }
936
937         base = omap_hwmod_get_mpu_rt_va(oh);
938         if (!base) {
939                 pr_err("%s: Could not get the base address for %s\n",
940                                 oh->name, __func__);
941                 return -EINVAL;
942         }
943
944         /* Enable the clocks before accessing the WDT registers */
945         ret = omap_hwmod_enable(oh);
946         if (ret) {
947                 pr_err("%s: Could not enable clocks for %s\n",
948                                 oh->name, __func__);
949                 return ret;
950         }
951
952         /* sequence required to disable watchdog */
953         __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
954         while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
955                 cpu_relax();
956
957         __raw_writel(0x5555, base + OMAP_WDT_SPR);
958         while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
959                 cpu_relax();
960
961         ret = omap_hwmod_idle(oh);
962         if (ret)
963                 pr_err("%s: Could not disable clocks for %s\n",
964                                 oh->name, __func__);
965
966         return ret;
967 }
968
969 static void __init omap_disable_wdt(void)
970 {
971         if (cpu_class_is_omap2())
972                 omap_hwmod_for_each_by_class("wd_timer",
973                                                 omap2_disable_wdt, NULL);
974         return;
975 }
976
977 static int __init omap2_init_devices(void)
978 {
979         /* please keep these calls, and their implementations above,
980          * in alphabetical order so they're easier to sort through.
981          */
982         omap_disable_wdt();
983         omap_hsmmc_reset();
984         omap_init_camera();
985         omap_init_mbox();
986         omap_init_mcspi();
987         omap_init_pmu();
988         omap_hdq_init();
989         omap_init_sti();
990         omap_init_sham();
991         omap_init_aes();
992         omap_init_vout();
993
994         return 0;
995 }
996 arch_initcall(omap2_init_devices);
997
998 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
999 struct omap_device_pm_latency omap_wdt_latency[] = {
1000         [0] = {
1001                 .deactivate_func = omap_device_idle_hwmods,
1002                 .activate_func   = omap_device_enable_hwmods,
1003                 .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
1004         },
1005 };
1006
1007 static int __init omap_init_wdt(void)
1008 {
1009         int id = -1;
1010         struct omap_device *od;
1011         struct omap_hwmod *oh;
1012         char *oh_name = "wd_timer2";
1013         char *dev_name = "omap_wdt";
1014
1015         if (!cpu_class_is_omap2())
1016                 return 0;
1017
1018         oh = omap_hwmod_lookup(oh_name);
1019         if (!oh) {
1020                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1021                 return -EINVAL;
1022         }
1023
1024         od = omap_device_build(dev_name, id, oh, NULL, 0,
1025                                 omap_wdt_latency,
1026                                 ARRAY_SIZE(omap_wdt_latency), 0);
1027         WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
1028                                 dev_name, oh->name);
1029         return 0;
1030 }
1031 subsys_initcall(omap_init_wdt);
1032 #endif