arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37
  38 /* Maximum DPLL multiplier, divider values for OMAP3 */
  39 #define OMAP3_MAX_DPLL_MULT             2048
  40 #define OMAP3_MAX_DPLL_DIV              128
  41
  42 /*
  43  * DPLL1 supplies clock to the MPU.
  44  * DPLL2 supplies clock to the IVA2.
  45  * DPLL3 supplies CORE domain clocks.
  46  * DPLL4 supplies peripheral clocks.
  47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  48  */
  49
  50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  51 #define DPLL_LOW_POWER_STOP             0x1
  52 #define DPLL_LOW_POWER_BYPASS           0x5
  53 #define DPLL_LOCKED                     0x7
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .rate           = 32768,
  61         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  62                                 ALWAYS_ENABLED,
  63         .recalc         = &propagate_rate,
  64 };
  65
  66 static struct clk secure_32k_fck = {
  67         .name           = "secure_32k_fck",
  68         .rate           = 32768,
  69         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  70                                 ALWAYS_ENABLED,
  71         .recalc         = &propagate_rate,
  72 };
  73
  74 /* Virtual source clocks for osc_sys_ck */
  75 static struct clk virt_12m_ck = {
  76         .name           = "virt_12m_ck",
  77         .rate           = 12000000,
  78         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  79                                 ALWAYS_ENABLED,
  80         .recalc         = &propagate_rate,
  81 };
  82
  83 static struct clk virt_13m_ck = {
  84         .name           = "virt_13m_ck",
  85         .rate           = 13000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .recalc         = &propagate_rate,
  89 };
  90
  91 static struct clk virt_16_8m_ck = {
  92         .name           = "virt_16_8m_ck",
  93         .rate           = 16800000,
  94         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .recalc         = &propagate_rate,
  97 };
  98
  99 static struct clk virt_19_2m_ck = {
 100         .name           = "virt_19_2m_ck",
 101         .rate           = 19200000,
 102         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 103                                 ALWAYS_ENABLED,
 104         .recalc         = &propagate_rate,
 105 };
 106
 107 static struct clk virt_26m_ck = {
 108         .name           = "virt_26m_ck",
 109         .rate           = 26000000,
 110         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 111                                 ALWAYS_ENABLED,
 112         .recalc         = &propagate_rate,
 113 };
 114
 115 static struct clk virt_38_4m_ck = {
 116         .name           = "virt_38_4m_ck",
 117         .rate           = 38400000,
 118         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 119                                 ALWAYS_ENABLED,
 120         .recalc         = &propagate_rate,
 121 };
 122
 123 static const struct clksel_rate osc_sys_12m_rates[] = {
 124         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 125         { .div = 0 }
 126 };
 127
 128 static const struct clksel_rate osc_sys_13m_rates[] = {
 129         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 130         { .div = 0 }
 131 };
 132
 133 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 134         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 139         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel_rate osc_sys_26m_rates[] = {
 144         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 145         { .div = 0 }
 146 };
 147
 148 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 149         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 150         { .div = 0 }
 151 };
 152
 153 static const struct clksel osc_sys_clksel[] = {
 154         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 155         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 156         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 157         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 158         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 159         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 160         { .parent = NULL },
 161 };
 162
 163 /* Oscillator clock */
 164 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 165 static struct clk osc_sys_ck = {
 166         .name           = "osc_sys_ck",
 167         .init           = &omap2_init_clksel_parent,
 168         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 169         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 170         .clksel         = osc_sys_clksel,
 171         /* REVISIT: deal with autoextclkmode? */
 172         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 173                                 ALWAYS_ENABLED,
 174         .recalc         = &omap2_clksel_recalc,
 175 };
 176
 177 static const struct clksel_rate div2_rates[] = {
 178         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 179         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 180         { .div = 0 }
 181 };
 182
 183 static const struct clksel sys_clksel[] = {
 184         { .parent = &osc_sys_ck, .rates = div2_rates },
 185         { .parent = NULL }
 186 };
 187
 188 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 189 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 190 static struct clk sys_ck = {
 191         .name           = "sys_ck",
 192         .parent         = &osc_sys_ck,
 193         .init           = &omap2_init_clksel_parent,
 194         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 195         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 196         .clksel         = sys_clksel,
 197         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 198         .recalc         = &omap2_clksel_recalc,
 199 };
 200
 201 static struct clk sys_altclk = {
 202         .name           = "sys_altclk",
 203         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 204         .recalc         = &propagate_rate,
 205 };
 206
 207 /* Optional external clock input for some McBSPs */
 208 static struct clk mcbsp_clks = {
 209         .name           = "mcbsp_clks",
 210         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 211         .recalc         = &propagate_rate,
 212 };
 213
 214 /* PRM EXTERNAL CLOCK OUTPUT */
 215
 216 static struct clk sys_clkout1 = {
 217         .name           = "sys_clkout1",
 218         .parent         = &osc_sys_ck,
 219         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 220         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 221         .flags          = CLOCK_IN_OMAP343X,
 222         .recalc         = &followparent_recalc,
 223 };
 224
 225 /* DPLLS */
 226
 227 /* CM CLOCKS */
 228
 229 static const struct clksel_rate dpll_bypass_rates[] = {
 230         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 231         { .div = 0 }
 232 };
 233
 234 static const struct clksel_rate dpll_locked_rates[] = {
 235         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 236         { .div = 0 }
 237 };
 238
 239 static const struct clksel_rate div16_dpll_rates[] = {
 240         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 241         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 242         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 243         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 244         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 245         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 246         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 247         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 248         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 249         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 250         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 251         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 252         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 253         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 254         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 255         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 256         { .div = 0 }
 257 };
 258
 259 /* DPLL1 */
 260 /* MPU clock source */
 261 /* Type: DPLL */
 262 static struct dpll_data dpll1_dd = {
 263         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 264         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 265         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 266         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 267         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 268         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 269         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 270         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 271         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 272         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 273         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 274         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 275         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 276         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 277         .max_divider    = OMAP3_MAX_DPLL_DIV,
 278         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 279 };
 280
 281 static struct clk dpll1_ck = {
 282         .name           = "dpll1_ck",
 283         .parent         = &sys_ck,
 284         .dpll_data      = &dpll1_dd,
 285         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 286         .round_rate     = &omap2_dpll_round_rate,
 287         .recalc         = &omap3_dpll_recalc,
 288 };
 289
 290 /*
 291  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 292  * DPLL isn't bypassed.
 293  */
 294 static struct clk dpll1_x2_ck = {
 295         .name           = "dpll1_x2_ck",
 296         .parent         = &dpll1_ck,
 297         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 298                                 PARENT_CONTROLS_CLOCK,
 299         .recalc         = &omap3_clkoutx2_recalc,
 300 };
 301
 302 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 303 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 304         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 305         { .parent = NULL }
 306 };
 307
 308 /*
 309  * Does not exist in the TRM - needed to separate the M2 divider from
 310  * bypass selection in mpu_ck
 311  */
 312 static struct clk dpll1_x2m2_ck = {
 313         .name           = "dpll1_x2m2_ck",
 314         .parent         = &dpll1_x2_ck,
 315         .init           = &omap2_init_clksel_parent,
 316         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 317         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 318         .clksel         = div16_dpll1_x2m2_clksel,
 319         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 320                                 PARENT_CONTROLS_CLOCK,
 321         .recalc         = &omap2_clksel_recalc,
 322 };
 323
 324 /* DPLL2 */
 325 /* IVA2 clock source */
 326 /* Type: DPLL */
 327
 328 static struct dpll_data dpll2_dd = {
 329         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 330         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 331         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 332         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 333         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 334         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 335                                 (1 << DPLL_LOW_POWER_BYPASS),
 336         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 337         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 338         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 339         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 340         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 341         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 342         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 343         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 344         .max_divider    = OMAP3_MAX_DPLL_DIV,
 345         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 346 };
 347
 348 static struct clk dpll2_ck = {
 349         .name           = "dpll2_ck",
 350         .parent         = &sys_ck,
 351         .dpll_data      = &dpll2_dd,
 352         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 353         .enable         = &omap3_noncore_dpll_enable,
 354         .disable        = &omap3_noncore_dpll_disable,
 355         .round_rate     = &omap2_dpll_round_rate,
 356         .recalc         = &omap3_dpll_recalc,
 357 };
 358
 359 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 360         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 361         { .parent = NULL }
 362 };
 363
 364 /*
 365  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 366  * or CLKOUTX2. CLKOUT seems most plausible.
 367  */
 368 static struct clk dpll2_m2_ck = {
 369         .name           = "dpll2_m2_ck",
 370         .parent         = &dpll2_ck,
 371         .init           = &omap2_init_clksel_parent,
 372         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 373                                           OMAP3430_CM_CLKSEL2_PLL),
 374         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 375         .clksel         = div16_dpll2_m2x2_clksel,
 376         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 377                                 PARENT_CONTROLS_CLOCK,
 378         .recalc         = &omap2_clksel_recalc,
 379 };
 380
 381 /*
 382  * DPLL3
 383  * Source clock for all interfaces and for some device fclks
 384  * REVISIT: Also supports fast relock bypass - not included below
 385  */
 386 static struct dpll_data dpll3_dd = {
 387         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 388         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 389         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 390         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 391         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 392         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 393         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 394         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 395         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 396         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 397         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 398         .max_divider    = OMAP3_MAX_DPLL_DIV,
 399         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 400 };
 401
 402 static struct clk dpll3_ck = {
 403         .name           = "dpll3_ck",
 404         .parent         = &sys_ck,
 405         .dpll_data      = &dpll3_dd,
 406         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 407         .round_rate     = &omap2_dpll_round_rate,
 408         .recalc         = &omap3_dpll_recalc,
 409 };
 410
 411 /*
 412  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 413  * DPLL isn't bypassed
 414  */
 415 static struct clk dpll3_x2_ck = {
 416         .name           = "dpll3_x2_ck",
 417         .parent         = &dpll3_ck,
 418         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 419                                 PARENT_CONTROLS_CLOCK,
 420         .recalc         = &omap3_clkoutx2_recalc,
 421 };
 422
 423 static const struct clksel_rate div31_dpll3_rates[] = {
 424         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 425         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 426         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 427         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 428         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 429         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 430         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 431         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 432         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 433         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 434         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 435         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 436         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 437         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 438         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 439         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 440         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 441         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 442         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 443         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 444         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 445         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 446         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 447         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 448         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 449         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 450         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 451         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 452         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 453         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 454         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 455         { .div = 0 },
 456 };
 457
 458 static const struct clksel div31_dpll3m2_clksel[] = {
 459         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 460         { .parent = NULL }
 461 };
 462
 463 /*
 464  * DPLL3 output M2
 465  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 466  * that code is ready, this should remain a 'read-only' clksel clock.
 467  */
 468 static struct clk dpll3_m2_ck = {
 469         .name           = "dpll3_m2_ck",
 470         .parent         = &dpll3_ck,
 471         .init           = &omap2_init_clksel_parent,
 472         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 473         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 474         .clksel         = div31_dpll3m2_clksel,
 475         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 476                                 PARENT_CONTROLS_CLOCK,
 477         .recalc         = &omap2_clksel_recalc,
 478 };
 479
 480 static const struct clksel core_ck_clksel[] = {
 481         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 482         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 483         { .parent = NULL }
 484 };
 485
 486 static struct clk core_ck = {
 487         .name           = "core_ck",
 488         .init           = &omap2_init_clksel_parent,
 489         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 490         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 491         .clksel         = core_ck_clksel,
 492         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 493                                 PARENT_CONTROLS_CLOCK,
 494         .recalc         = &omap2_clksel_recalc,
 495 };
 496
 497 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 498         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 499         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 500         { .parent = NULL }
 501 };
 502
 503 static struct clk dpll3_m2x2_ck = {
 504         .name           = "dpll3_m2x2_ck",
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 508         .clksel         = dpll3_m2x2_ck_clksel,
 509         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 510                                 PARENT_CONTROLS_CLOCK,
 511         .recalc         = &omap2_clksel_recalc,
 512 };
 513
 514 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 515 static const struct clksel div16_dpll3_clksel[] = {
 516         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 517         { .parent = NULL }
 518 };
 519
 520 /* This virtual clock is the source for dpll3_m3x2_ck */
 521 static struct clk dpll3_m3_ck = {
 522         .name           = "dpll3_m3_ck",
 523         .parent         = &dpll3_ck,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 527         .clksel         = div16_dpll3_clksel,
 528         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 529                                 PARENT_CONTROLS_CLOCK,
 530         .recalc         = &omap2_clksel_recalc,
 531 };
 532
 533 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 534 static struct clk dpll3_m3x2_ck = {
 535         .name           = "dpll3_m3x2_ck",
 536         .parent         = &dpll3_m3_ck,
 537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 539         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 540         .recalc         = &omap3_clkoutx2_recalc,
 541 };
 542
 543 static const struct clksel emu_core_alwon_ck_clksel[] = {
 544         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 545         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 546         { .parent = NULL }
 547 };
 548
 549 static struct clk emu_core_alwon_ck = {
 550         .name           = "emu_core_alwon_ck",
 551         .parent         = &dpll3_m3x2_ck,
 552         .init           = &omap2_init_clksel_parent,
 553         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 554         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 555         .clksel         = emu_core_alwon_ck_clksel,
 556         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 557                                 PARENT_CONTROLS_CLOCK,
 558         .recalc         = &omap2_clksel_recalc,
 559 };
 560
 561 /* DPLL4 */
 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563 /* Type: DPLL */
 564 static struct dpll_data dpll4_dd = {
 565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 568         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 569         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 570         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 571         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 572         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 573         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 574         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 575         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 576         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 577         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 578         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 579         .max_divider    = OMAP3_MAX_DPLL_DIV,
 580         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 581 };
 582
 583 static struct clk dpll4_ck = {
 584         .name           = "dpll4_ck",
 585         .parent         = &sys_ck,
 586         .dpll_data      = &dpll4_dd,
 587         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 588         .enable         = &omap3_noncore_dpll_enable,
 589         .disable        = &omap3_noncore_dpll_disable,
 590         .round_rate     = &omap2_dpll_round_rate,
 591         .recalc         = &omap3_dpll_recalc,
 592 };
 593
 594 /*
 595  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 596  * DPLL isn't bypassed --
 597  * XXX does this serve any downstream clocks?
 598  */
 599 static struct clk dpll4_x2_ck = {
 600         .name           = "dpll4_x2_ck",
 601         .parent         = &dpll4_ck,
 602         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 603                                 PARENT_CONTROLS_CLOCK,
 604         .recalc         = &omap3_clkoutx2_recalc,
 605 };
 606
 607 static const struct clksel div16_dpll4_clksel[] = {
 608         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 609         { .parent = NULL }
 610 };
 611
 612 /* This virtual clock is the source for dpll4_m2x2_ck */
 613 static struct clk dpll4_m2_ck = {
 614         .name           = "dpll4_m2_ck",
 615         .parent         = &dpll4_ck,
 616         .init           = &omap2_init_clksel_parent,
 617         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 618         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 619         .clksel         = div16_dpll4_clksel,
 620         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 621                                 PARENT_CONTROLS_CLOCK,
 622         .recalc         = &omap2_clksel_recalc,
 623 };
 624
 625 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 626 static struct clk dpll4_m2x2_ck = {
 627         .name           = "dpll4_m2x2_ck",
 628         .parent         = &dpll4_m2_ck,
 629         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 630         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 631         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 632         .recalc         = &omap3_clkoutx2_recalc,
 633 };
 634
 635 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 636         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 637         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 638         { .parent = NULL }
 639 };
 640
 641 static struct clk omap_96m_alwon_fck = {
 642         .name           = "omap_96m_alwon_fck",
 643         .parent         = &dpll4_m2x2_ck,
 644         .init           = &omap2_init_clksel_parent,
 645         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 646         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 647         .clksel         = omap_96m_alwon_fck_clksel,
 648         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 649                                  PARENT_CONTROLS_CLOCK,
 650         .recalc         = &omap2_clksel_recalc,
 651 };
 652
 653 static struct clk omap_96m_fck = {
 654         .name           = "omap_96m_fck",
 655         .parent         = &omap_96m_alwon_fck,
 656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 657                                 PARENT_CONTROLS_CLOCK,
 658         .recalc         = &followparent_recalc,
 659 };
 660
 661 static const struct clksel cm_96m_fck_clksel[] = {
 662         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 663         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 664         { .parent = NULL }
 665 };
 666
 667 static struct clk cm_96m_fck = {
 668         .name           = "cm_96m_fck",
 669         .parent         = &dpll4_m2x2_ck,
 670         .init           = &omap2_init_clksel_parent,
 671         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 672         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 673         .clksel         = cm_96m_fck_clksel,
 674         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 675                                 PARENT_CONTROLS_CLOCK,
 676         .recalc         = &omap2_clksel_recalc,
 677 };
 678
 679 /* This virtual clock is the source for dpll4_m3x2_ck */
 680 static struct clk dpll4_m3_ck = {
 681         .name           = "dpll4_m3_ck",
 682         .parent         = &dpll4_ck,
 683         .init           = &omap2_init_clksel_parent,
 684         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 685         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 686         .clksel         = div16_dpll4_clksel,
 687         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 688                                 PARENT_CONTROLS_CLOCK,
 689         .recalc         = &omap2_clksel_recalc,
 690 };
 691
 692 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 693 static struct clk dpll4_m3x2_ck = {
 694         .name           = "dpll4_m3x2_ck",
 695         .parent         = &dpll4_m3_ck,
 696         .init           = &omap2_init_clksel_parent,
 697         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 698         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 699         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 700         .recalc         = &omap3_clkoutx2_recalc,
 701 };
 702
 703 static const struct clksel virt_omap_54m_fck_clksel[] = {
 704         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 705         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 706         { .parent = NULL }
 707 };
 708
 709 static struct clk virt_omap_54m_fck = {
 710         .name           = "virt_omap_54m_fck",
 711         .parent         = &dpll4_m3x2_ck,
 712         .init           = &omap2_init_clksel_parent,
 713         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 714         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 715         .clksel         = virt_omap_54m_fck_clksel,
 716         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 717                                 PARENT_CONTROLS_CLOCK,
 718         .recalc         = &omap2_clksel_recalc,
 719 };
 720
 721 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 722         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 723         { .div = 0 }
 724 };
 725
 726 static const struct clksel_rate omap_54m_alt_rates[] = {
 727         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 728         { .div = 0 }
 729 };
 730
 731 static const struct clksel omap_54m_clksel[] = {
 732         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 733         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 734         { .parent = NULL }
 735 };
 736
 737 static struct clk omap_54m_fck = {
 738         .name           = "omap_54m_fck",
 739         .init           = &omap2_init_clksel_parent,
 740         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 741         .clksel_mask    = OMAP3430_SOURCE_54M,
 742         .clksel         = omap_54m_clksel,
 743         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 744                                 PARENT_CONTROLS_CLOCK,
 745         .recalc         = &omap2_clksel_recalc,
 746 };
 747
 748 static const struct clksel_rate omap_48m_96md2_rates[] = {
 749         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 750         { .div = 0 }
 751 };
 752
 753 static const struct clksel_rate omap_48m_alt_rates[] = {
 754         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 755         { .div = 0 }
 756 };
 757
 758 static const struct clksel omap_48m_clksel[] = {
 759         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 760         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 761         { .parent = NULL }
 762 };
 763
 764 static struct clk omap_48m_fck = {
 765         .name           = "omap_48m_fck",
 766         .init           = &omap2_init_clksel_parent,
 767         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 768         .clksel_mask    = OMAP3430_SOURCE_48M,
 769         .clksel         = omap_48m_clksel,
 770         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 771                                 PARENT_CONTROLS_CLOCK,
 772         .recalc         = &omap2_clksel_recalc,
 773 };
 774
 775 static struct clk omap_12m_fck = {
 776         .name           = "omap_12m_fck",
 777         .parent         = &omap_48m_fck,
 778         .fixed_div      = 4,
 779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 780                                 PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_fixed_divisor_recalc,
 782 };
 783
 784 /* This virstual clock is the source for dpll4_m4x2_ck */
 785 static struct clk dpll4_m4_ck = {
 786         .name           = "dpll4_m4_ck",
 787         .parent         = &dpll4_ck,
 788         .init           = &omap2_init_clksel_parent,
 789         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 790         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 791         .clksel         = div16_dpll4_clksel,
 792         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 793                                 PARENT_CONTROLS_CLOCK,
 794         .recalc         = &omap2_clksel_recalc,
 795 };
 796
 797 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 798 static struct clk dpll4_m4x2_ck = {
 799         .name           = "dpll4_m4x2_ck",
 800         .parent         = &dpll4_m4_ck,
 801         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 802         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 803         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 804         .recalc         = &omap3_clkoutx2_recalc,
 805 };
 806
 807 /* This virtual clock is the source for dpll4_m5x2_ck */
 808 static struct clk dpll4_m5_ck = {
 809         .name           = "dpll4_m5_ck",
 810         .parent         = &dpll4_ck,
 811         .init           = &omap2_init_clksel_parent,
 812         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 813         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 814         .clksel         = div16_dpll4_clksel,
 815         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 816                                 PARENT_CONTROLS_CLOCK,
 817         .recalc         = &omap2_clksel_recalc,
 818 };
 819
 820 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 821 static struct clk dpll4_m5x2_ck = {
 822         .name           = "dpll4_m5x2_ck",
 823         .parent         = &dpll4_m5_ck,
 824         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 825         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 826         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 827         .recalc         = &omap3_clkoutx2_recalc,
 828 };
 829
 830 /* This virtual clock is the source for dpll4_m6x2_ck */
 831 static struct clk dpll4_m6_ck = {
 832         .name           = "dpll4_m6_ck",
 833         .parent         = &dpll4_ck,
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 836         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 837         .clksel         = div16_dpll4_clksel,
 838         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 839                                 PARENT_CONTROLS_CLOCK,
 840         .recalc         = &omap2_clksel_recalc,
 841 };
 842
 843 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 844 static struct clk dpll4_m6x2_ck = {
 845         .name           = "dpll4_m6x2_ck",
 846         .parent         = &dpll4_m6_ck,
 847         .init           = &omap2_init_clksel_parent,
 848         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 849         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 850         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 851         .recalc         = &omap3_clkoutx2_recalc,
 852 };
 853
 854 static struct clk emu_per_alwon_ck = {
 855         .name           = "emu_per_alwon_ck",
 856         .parent         = &dpll4_m6x2_ck,
 857         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 858                                 PARENT_CONTROLS_CLOCK,
 859         .recalc         = &followparent_recalc,
 860 };
 861
 862 /* DPLL5 */
 863 /* Supplies 120MHz clock, USIM source clock */
 864 /* Type: DPLL */
 865 /* 3430ES2 only */
 866 static struct dpll_data dpll5_dd = {
 867         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 868         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 869         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 870         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 871         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 872         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 873         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 874         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 875         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 876         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 877         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 878         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 879         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 880         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 881         .max_divider    = OMAP3_MAX_DPLL_DIV,
 882         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 883 };
 884
 885 static struct clk dpll5_ck = {
 886         .name           = "dpll5_ck",
 887         .parent         = &sys_ck,
 888         .dpll_data      = &dpll5_dd,
 889         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 890         .enable         = &omap3_noncore_dpll_enable,
 891         .disable        = &omap3_noncore_dpll_disable,
 892         .round_rate     = &omap2_dpll_round_rate,
 893         .recalc         = &omap3_dpll_recalc,
 894 };
 895
 896 static const struct clksel div16_dpll5_clksel[] = {
 897         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 898         { .parent = NULL }
 899 };
 900
 901 static struct clk dpll5_m2_ck = {
 902         .name           = "dpll5_m2_ck",
 903         .parent         = &dpll5_ck,
 904         .init           = &omap2_init_clksel_parent,
 905         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 906         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 907         .clksel         = div16_dpll5_clksel,
 908         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 909                                 PARENT_CONTROLS_CLOCK,
 910         .recalc         = &omap2_clksel_recalc,
 911 };
 912
 913 static const struct clksel omap_120m_fck_clksel[] = {
 914         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 915         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 916         { .parent = NULL }
 917 };
 918
 919 static struct clk omap_120m_fck = {
 920         .name           = "omap_120m_fck",
 921         .parent         = &dpll5_m2_ck,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 924         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 925         .clksel         = omap_120m_fck_clksel,
 926         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 927                                 PARENT_CONTROLS_CLOCK,
 928         .recalc         = &omap2_clksel_recalc,
 929 };
 930
 931 /* CM EXTERNAL CLOCK OUTPUTS */
 932
 933 static const struct clksel_rate clkout2_src_core_rates[] = {
 934         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 935         { .div = 0 }
 936 };
 937
 938 static const struct clksel_rate clkout2_src_sys_rates[] = {
 939         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 940         { .div = 0 }
 941 };
 942
 943 static const struct clksel_rate clkout2_src_96m_rates[] = {
 944         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 945         { .div = 0 }
 946 };
 947
 948 static const struct clksel_rate clkout2_src_54m_rates[] = {
 949         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 950         { .div = 0 }
 951 };
 952
 953 static const struct clksel clkout2_src_clksel[] = {
 954         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 955         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 956         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 957         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 958         { .parent = NULL }
 959 };
 960
 961 static struct clk clkout2_src_ck = {
 962         .name           = "clkout2_src_ck",
 963         .init           = &omap2_init_clksel_parent,
 964         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 965         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 966         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 967         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 968         .clksel         = clkout2_src_clksel,
 969         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 970         .recalc         = &omap2_clksel_recalc,
 971 };
 972
 973 static const struct clksel_rate sys_clkout2_rates[] = {
 974         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 975         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 976         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 977         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 978         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 979         { .div = 0 },
 980 };
 981
 982 static const struct clksel sys_clkout2_clksel[] = {
 983         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 984         { .parent = NULL },
 985 };
 986
 987 static struct clk sys_clkout2 = {
 988         .name           = "sys_clkout2",
 989         .init           = &omap2_init_clksel_parent,
 990         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 991         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 992         .clksel         = sys_clkout2_clksel,
 993         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 994         .recalc         = &omap2_clksel_recalc,
 995 };
 996
 997 /* CM OUTPUT CLOCKS */
 998
 999 static struct clk corex2_fck = {
1000         .name           = "corex2_fck",
1001         .parent         = &dpll3_m2x2_ck,
1002         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1003                                 PARENT_CONTROLS_CLOCK,
1004         .recalc         = &followparent_recalc,
1005 };
1006
1007 /* DPLL power domain clock controls */
1008
1009 static const struct clksel div2_core_clksel[] = {
1010         { .parent = &core_ck, .rates = div2_rates },
1011         { .parent = NULL }
1012 };
1013
1014 /*
1015  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1016  * may be inconsistent here?
1017  */
1018 static struct clk dpll1_fck = {
1019         .name           = "dpll1_fck",
1020         .parent         = &core_ck,
1021         .init           = &omap2_init_clksel_parent,
1022         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1024         .clksel         = div2_core_clksel,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026                                 PARENT_CONTROLS_CLOCK,
1027         .recalc         = &omap2_clksel_recalc,
1028 };
1029
1030 /*
1031  * MPU clksel:
1032  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1033  * derives from the high-frequency bypass clock originating from DPLL3,
1034  * called 'dpll1_fck'
1035  */
1036 static const struct clksel mpu_clksel[] = {
1037         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1038         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039         { .parent = NULL }
1040 };
1041
1042 static struct clk mpu_ck = {
1043         .name           = "mpu_ck",
1044         .parent         = &dpll1_x2m2_ck,
1045         .init           = &omap2_init_clksel_parent,
1046         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1048         .clksel         = mpu_clksel,
1049         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050                                 PARENT_CONTROLS_CLOCK,
1051         .recalc         = &omap2_clksel_recalc,
1052 };
1053
1054 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1055 static const struct clksel_rate arm_fck_rates[] = {
1056         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1057         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1058         { .div = 0 },
1059 };
1060
1061 static const struct clksel arm_fck_clksel[] = {
1062         { .parent = &mpu_ck, .rates = arm_fck_rates },
1063         { .parent = NULL }
1064 };
1065
1066 static struct clk arm_fck = {
1067         .name           = "arm_fck",
1068         .parent         = &mpu_ck,
1069         .init           = &omap2_init_clksel_parent,
1070         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1071         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1072         .clksel         = arm_fck_clksel,
1073         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1074                                 PARENT_CONTROLS_CLOCK,
1075         .recalc         = &omap2_clksel_recalc,
1076 };
1077
1078 /*
1079  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1080  * although it is referenced - so this is a guess
1081  */
1082 static struct clk emu_mpu_alwon_ck = {
1083         .name           = "emu_mpu_alwon_ck",
1084         .parent         = &mpu_ck,
1085         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1086                                 PARENT_CONTROLS_CLOCK,
1087         .recalc         = &followparent_recalc,
1088 };
1089
1090 static struct clk dpll2_fck = {
1091         .name           = "dpll2_fck",
1092         .parent         = &core_ck,
1093         .init           = &omap2_init_clksel_parent,
1094         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1095         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1096         .clksel         = div2_core_clksel,
1097         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1098                                 PARENT_CONTROLS_CLOCK,
1099         .recalc         = &omap2_clksel_recalc,
1100 };
1101
1102 /*
1103  * IVA2 clksel:
1104  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1105  * derives from the high-frequency bypass clock originating from DPLL3,
1106  * called 'dpll2_fck'
1107  */
1108
1109 static const struct clksel iva2_clksel[] = {
1110         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1111         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1112         { .parent = NULL }
1113 };
1114
1115 static struct clk iva2_ck = {
1116         .name           = "iva2_ck",
1117         .parent         = &dpll2_m2_ck,
1118         .init           = &omap2_init_clksel_parent,
1119         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1120         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1121         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1122                                           OMAP3430_CM_IDLEST_PLL),
1123         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1124         .clksel         = iva2_clksel,
1125         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1126         .recalc         = &omap2_clksel_recalc,
1127 };
1128
1129 /* Common interface clocks */
1130
1131 static struct clk l3_ick = {
1132         .name           = "l3_ick",
1133         .parent         = &core_ck,
1134         .init           = &omap2_init_clksel_parent,
1135         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1136         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1137         .clksel         = div2_core_clksel,
1138         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1139                                 PARENT_CONTROLS_CLOCK,
1140         .recalc         = &omap2_clksel_recalc,
1141 };
1142
1143 static const struct clksel div2_l3_clksel[] = {
1144         { .parent = &l3_ick, .rates = div2_rates },
1145         { .parent = NULL }
1146 };
1147
1148 static struct clk l4_ick = {
1149         .name           = "l4_ick",
1150         .parent         = &l3_ick,
1151         .init           = &omap2_init_clksel_parent,
1152         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1153         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1154         .clksel         = div2_l3_clksel,
1155         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1156                                 PARENT_CONTROLS_CLOCK,
1157         .recalc         = &omap2_clksel_recalc,
1158
1159 };
1160
1161 static const struct clksel div2_l4_clksel[] = {
1162         { .parent = &l4_ick, .rates = div2_rates },
1163         { .parent = NULL }
1164 };
1165
1166 static struct clk rm_ick = {
1167         .name           = "rm_ick",
1168         .parent         = &l4_ick,
1169         .init           = &omap2_init_clksel_parent,
1170         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1171         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1172         .clksel         = div2_l4_clksel,
1173         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1174         .recalc         = &omap2_clksel_recalc,
1175 };
1176
1177 /* GFX power domain */
1178
1179 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1180
1181 static const struct clksel gfx_l3_clksel[] = {
1182         { .parent = &l3_ick, .rates = gfx_l3_rates },
1183         { .parent = NULL }
1184 };
1185
1186 static struct clk gfx_l3_fck = {
1187         .name           = "gfx_l3_fck",
1188         .parent         = &l3_ick,
1189         .init           = &omap2_init_clksel_parent,
1190         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1191         .enable_bit     = OMAP_EN_GFX_SHIFT,
1192         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1193         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1194         .clksel         = gfx_l3_clksel,
1195         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1196         .recalc         = &omap2_clksel_recalc,
1197 };
1198
1199 static struct clk gfx_l3_ick = {
1200         .name           = "gfx_l3_ick",
1201         .parent         = &l3_ick,
1202         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1203         .enable_bit     = OMAP_EN_GFX_SHIFT,
1204         .flags          = CLOCK_IN_OMAP3430ES1,
1205         .recalc         = &followparent_recalc,
1206 };
1207
1208 static struct clk gfx_cg1_ck = {
1209         .name           = "gfx_cg1_ck",
1210         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1211         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1212         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1213         .flags          = CLOCK_IN_OMAP3430ES1,
1214         .recalc         = &followparent_recalc,
1215 };
1216
1217 static struct clk gfx_cg2_ck = {
1218         .name           = "gfx_cg2_ck",
1219         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1220         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1221         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1222         .flags          = CLOCK_IN_OMAP3430ES1,
1223         .recalc         = &followparent_recalc,
1224 };
1225
1226 /* SGX power domain - 3430ES2 only */
1227
1228 static const struct clksel_rate sgx_core_rates[] = {
1229         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1230         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1231         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1232         { .div = 0 },
1233 };
1234
1235 static const struct clksel_rate sgx_96m_rates[] = {
1236         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1237         { .div = 0 },
1238 };
1239
1240 static const struct clksel sgx_clksel[] = {
1241         { .parent = &core_ck,    .rates = sgx_core_rates },
1242         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1243         { .parent = NULL },
1244 };
1245
1246 static struct clk sgx_fck = {
1247         .name           = "sgx_fck",
1248         .init           = &omap2_init_clksel_parent,
1249         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1250         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1251         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1252         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1253         .clksel         = sgx_clksel,
1254         .flags          = CLOCK_IN_OMAP3430ES2,
1255         .recalc         = &omap2_clksel_recalc,
1256 };
1257
1258 static struct clk sgx_ick = {
1259         .name           = "sgx_ick",
1260         .parent         = &l3_ick,
1261         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1262         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1263         .flags          = CLOCK_IN_OMAP3430ES2,
1264         .recalc         = &followparent_recalc,
1265 };
1266
1267 /* CORE power domain */
1268
1269 static struct clk d2d_26m_fck = {
1270         .name           = "d2d_26m_fck",
1271         .parent         = &sys_ck,
1272         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1273         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1274         .flags          = CLOCK_IN_OMAP3430ES1,
1275         .recalc         = &followparent_recalc,
1276 };
1277
1278 static const struct clksel omap343x_gpt_clksel[] = {
1279         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1280         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1281         { .parent = NULL}
1282 };
1283
1284 static struct clk gpt10_fck = {
1285         .name           = "gpt10_fck",
1286         .parent         = &sys_ck,
1287         .init           = &omap2_init_clksel_parent,
1288         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1289         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1290         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1291         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1292         .clksel         = omap343x_gpt_clksel,
1293         .flags          = CLOCK_IN_OMAP343X,
1294         .recalc         = &omap2_clksel_recalc,
1295 };
1296
1297 static struct clk gpt11_fck = {
1298         .name           = "gpt11_fck",
1299         .parent         = &sys_ck,
1300         .init           = &omap2_init_clksel_parent,
1301         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1302         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1303         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1304         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1305         .clksel         = omap343x_gpt_clksel,
1306         .flags          = CLOCK_IN_OMAP343X,
1307         .recalc         = &omap2_clksel_recalc,
1308 };
1309
1310 static struct clk cpefuse_fck = {
1311         .name           = "cpefuse_fck",
1312         .parent         = &sys_ck,
1313         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1314         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1315         .flags          = CLOCK_IN_OMAP3430ES2,
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 static struct clk ts_fck = {
1320         .name           = "ts_fck",
1321         .parent         = &omap_32k_fck,
1322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1323         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1324         .flags          = CLOCK_IN_OMAP3430ES2,
1325         .recalc         = &followparent_recalc,
1326 };
1327
1328 static struct clk usbtll_fck = {
1329         .name           = "usbtll_fck",
1330         .parent         = &omap_120m_fck,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1332         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1333         .flags          = CLOCK_IN_OMAP3430ES2,
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 /* CORE 96M FCLK-derived clocks */
1338
1339 static struct clk core_96m_fck = {
1340         .name           = "core_96m_fck",
1341         .parent         = &omap_96m_fck,
1342         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1343                                 PARENT_CONTROLS_CLOCK,
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static struct clk mmchs3_fck = {
1348         .name           = "mmchs_fck",
1349         .id             = 3,
1350         .parent         = &core_96m_fck,
1351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1352         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1353         .flags          = CLOCK_IN_OMAP3430ES2,
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk mmchs2_fck = {
1358         .name           = "mmchs_fck",
1359         .id             = 2,
1360         .parent         = &core_96m_fck,
1361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1362         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1363         .flags          = CLOCK_IN_OMAP343X,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk mspro_fck = {
1368         .name           = "mspro_fck",
1369         .parent         = &core_96m_fck,
1370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1372         .flags          = CLOCK_IN_OMAP343X,
1373         .recalc         = &followparent_recalc,
1374 };
1375
1376 static struct clk mmchs1_fck = {
1377         .name           = "mmchs_fck",
1378         .id             = 1,
1379         .parent         = &core_96m_fck,
1380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1382         .flags          = CLOCK_IN_OMAP343X,
1383         .recalc         = &followparent_recalc,
1384 };
1385
1386 static struct clk i2c3_fck = {
1387         .name           = "i2c_fck",
1388         .id             = 3,
1389         .parent         = &core_96m_fck,
1390         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1392         .flags          = CLOCK_IN_OMAP343X,
1393         .recalc         = &followparent_recalc,
1394 };
1395
1396 static struct clk i2c2_fck = {
1397         .name           = "i2c_fck",
1398         .id             = 2,
1399         .parent         = &core_96m_fck,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1402         .flags          = CLOCK_IN_OMAP343X,
1403         .recalc         = &followparent_recalc,
1404 };
1405
1406 static struct clk i2c1_fck = {
1407         .name           = "i2c_fck",
1408         .id             = 1,
1409         .parent         = &core_96m_fck,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1412         .flags          = CLOCK_IN_OMAP343X,
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 /*
1417  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1418  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1419  */
1420 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1421         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1422         { .div = 0 }
1423 };
1424
1425 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1426         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1427         { .div = 0 }
1428 };
1429
1430 static const struct clksel mcbsp_15_clksel[] = {
1431         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1432         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1433         { .parent = NULL }
1434 };
1435
1436 static struct clk mcbsp5_fck = {
1437         .name           = "mcbsp_fck",
1438         .id             = 5,
1439         .init           = &omap2_init_clksel_parent,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1442         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1443         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1444         .clksel         = mcbsp_15_clksel,
1445         .flags          = CLOCK_IN_OMAP343X,
1446         .recalc         = &omap2_clksel_recalc,
1447 };
1448
1449 static struct clk mcbsp1_fck = {
1450         .name           = "mcbsp_fck",
1451         .id             = 1,
1452         .init           = &omap2_init_clksel_parent,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1455         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1456         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1457         .clksel         = mcbsp_15_clksel,
1458         .flags          = CLOCK_IN_OMAP343X,
1459         .recalc         = &omap2_clksel_recalc,
1460 };
1461
1462 /* CORE_48M_FCK-derived clocks */
1463
1464 static struct clk core_48m_fck = {
1465         .name           = "core_48m_fck",
1466         .parent         = &omap_48m_fck,
1467         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1468                                 PARENT_CONTROLS_CLOCK,
1469         .recalc         = &followparent_recalc,
1470 };
1471
1472 static struct clk mcspi4_fck = {
1473         .name           = "mcspi_fck",
1474         .id             = 4,
1475         .parent         = &core_48m_fck,
1476         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1477         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1478         .flags          = CLOCK_IN_OMAP343X,
1479         .recalc         = &followparent_recalc,
1480 };
1481
1482 static struct clk mcspi3_fck = {
1483         .name           = "mcspi_fck",
1484         .id             = 3,
1485         .parent         = &core_48m_fck,
1486         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1487         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1488         .flags          = CLOCK_IN_OMAP343X,
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 static struct clk mcspi2_fck = {
1493         .name           = "mcspi_fck",
1494         .id             = 2,
1495         .parent         = &core_48m_fck,
1496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1498         .flags          = CLOCK_IN_OMAP343X,
1499         .recalc         = &followparent_recalc,
1500 };
1501
1502 static struct clk mcspi1_fck = {
1503         .name           = "mcspi_fck",
1504         .id             = 1,
1505         .parent         = &core_48m_fck,
1506         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1508         .flags          = CLOCK_IN_OMAP343X,
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk uart2_fck = {
1513         .name           = "uart2_fck",
1514         .parent         = &core_48m_fck,
1515         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1517         .flags          = CLOCK_IN_OMAP343X,
1518         .recalc         = &followparent_recalc,
1519 };
1520
1521 static struct clk uart1_fck = {
1522         .name           = "uart1_fck",
1523         .parent         = &core_48m_fck,
1524         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1526         .flags          = CLOCK_IN_OMAP343X,
1527         .recalc         = &followparent_recalc,
1528 };
1529
1530 static struct clk fshostusb_fck = {
1531         .name           = "fshostusb_fck",
1532         .parent         = &core_48m_fck,
1533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1535         .flags          = CLOCK_IN_OMAP3430ES1,
1536         .recalc         = &followparent_recalc,
1537 };
1538
1539 /* CORE_12M_FCK based clocks */
1540
1541 static struct clk core_12m_fck = {
1542         .name           = "core_12m_fck",
1543         .parent         = &omap_12m_fck,
1544         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1545                                 PARENT_CONTROLS_CLOCK,
1546         .recalc         = &followparent_recalc,
1547 };
1548
1549 static struct clk hdq_fck = {
1550         .name           = "hdq_fck",
1551         .parent         = &core_12m_fck,
1552         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1554         .flags          = CLOCK_IN_OMAP343X,
1555         .recalc         = &followparent_recalc,
1556 };
1557
1558 /* DPLL3-derived clock */
1559
1560 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1561         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1562         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1563         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1564         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1565         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1566         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1567         { .div = 0 }
1568 };
1569
1570 static const struct clksel ssi_ssr_clksel[] = {
1571         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1572         { .parent = NULL }
1573 };
1574
1575 static struct clk ssi_ssr_fck = {
1576         .name           = "ssi_ssr_fck",
1577         .init           = &omap2_init_clksel_parent,
1578         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1579         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1580         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1581         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1582         .clksel         = ssi_ssr_clksel,
1583         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1584         .recalc         = &omap2_clksel_recalc,
1585 };
1586
1587 static struct clk ssi_sst_fck = {
1588         .name           = "ssi_sst_fck",
1589         .parent         = &ssi_ssr_fck,
1590         .fixed_div      = 2,
1591         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1592         .recalc         = &omap2_fixed_divisor_recalc,
1593 };
1594
1595
1596
1597 /* CORE_L3_ICK based clocks */
1598
1599 static struct clk core_l3_ick = {
1600         .name           = "core_l3_ick",
1601         .parent         = &l3_ick,
1602         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1603                                 PARENT_CONTROLS_CLOCK,
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk hsotgusb_ick = {
1608         .name           = "hsotgusb_ick",
1609         .parent         = &core_l3_ick,
1610         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1611         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1612         .flags          = CLOCK_IN_OMAP343X,
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk sdrc_ick = {
1617         .name           = "sdrc_ick",
1618         .parent         = &core_l3_ick,
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1620         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1621         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1622         .recalc         = &followparent_recalc,
1623 };
1624
1625 static struct clk gpmc_fck = {
1626         .name           = "gpmc_fck",
1627         .parent         = &core_l3_ick,
1628         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1629                                 ENABLE_ON_INIT,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 /* SECURITY_L3_ICK based clocks */
1634
1635 static struct clk security_l3_ick = {
1636         .name           = "security_l3_ick",
1637         .parent         = &l3_ick,
1638         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1639                                 PARENT_CONTROLS_CLOCK,
1640         .recalc         = &followparent_recalc,
1641 };
1642
1643 static struct clk pka_ick = {
1644         .name           = "pka_ick",
1645         .parent         = &security_l3_ick,
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1647         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1648         .flags          = CLOCK_IN_OMAP343X,
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 /* CORE_L4_ICK based clocks */
1653
1654 static struct clk core_l4_ick = {
1655         .name           = "core_l4_ick",
1656         .parent         = &l4_ick,
1657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1658                                 PARENT_CONTROLS_CLOCK,
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk usbtll_ick = {
1663         .name           = "usbtll_ick",
1664         .parent         = &core_l4_ick,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1666         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1667         .flags          = CLOCK_IN_OMAP3430ES2,
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk mmchs3_ick = {
1672         .name           = "mmchs_ick",
1673         .id             = 3,
1674         .parent         = &core_l4_ick,
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1676         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1677         .flags          = CLOCK_IN_OMAP3430ES2,
1678         .recalc         = &followparent_recalc,
1679 };
1680
1681 /* Intersystem Communication Registers - chassis mode only */
1682 static struct clk icr_ick = {
1683         .name           = "icr_ick",
1684         .parent         = &core_l4_ick,
1685         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1686         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1687         .flags          = CLOCK_IN_OMAP343X,
1688         .recalc         = &followparent_recalc,
1689 };
1690
1691 static struct clk aes2_ick = {
1692         .name           = "aes2_ick",
1693         .parent         = &core_l4_ick,
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1696         .flags          = CLOCK_IN_OMAP343X,
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 static struct clk sha12_ick = {
1701         .name           = "sha12_ick",
1702         .parent         = &core_l4_ick,
1703         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1704         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1705         .flags          = CLOCK_IN_OMAP343X,
1706         .recalc         = &followparent_recalc,
1707 };
1708
1709 static struct clk des2_ick = {
1710         .name           = "des2_ick",
1711         .parent         = &core_l4_ick,
1712         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1714         .flags          = CLOCK_IN_OMAP343X,
1715         .recalc         = &followparent_recalc,
1716 };
1717
1718 static struct clk mmchs2_ick = {
1719         .name           = "mmchs_ick",
1720         .id             = 2,
1721         .parent         = &core_l4_ick,
1722         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1724         .flags          = CLOCK_IN_OMAP343X,
1725         .recalc         = &followparent_recalc,
1726 };
1727
1728 static struct clk mmchs1_ick = {
1729         .name           = "mmchs_ick",
1730         .id             = 1,
1731         .parent         = &core_l4_ick,
1732         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1734         .flags          = CLOCK_IN_OMAP343X,
1735         .recalc         = &followparent_recalc,
1736 };
1737
1738 static struct clk mspro_ick = {
1739         .name           = "mspro_ick",
1740         .parent         = &core_l4_ick,
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1743         .flags          = CLOCK_IN_OMAP343X,
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static struct clk hdq_ick = {
1748         .name           = "hdq_ick",
1749         .parent         = &core_l4_ick,
1750         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1751         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1752         .flags          = CLOCK_IN_OMAP343X,
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk mcspi4_ick = {
1757         .name           = "mcspi_ick",
1758         .id             = 4,
1759         .parent         = &core_l4_ick,
1760         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1761         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1762         .flags          = CLOCK_IN_OMAP343X,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk mcspi3_ick = {
1767         .name           = "mcspi_ick",
1768         .id             = 3,
1769         .parent         = &core_l4_ick,
1770         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1771         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1772         .flags          = CLOCK_IN_OMAP343X,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk mcspi2_ick = {
1777         .name           = "mcspi_ick",
1778         .id             = 2,
1779         .parent         = &core_l4_ick,
1780         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1781         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1782         .flags          = CLOCK_IN_OMAP343X,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk mcspi1_ick = {
1787         .name           = "mcspi_ick",
1788         .id             = 1,
1789         .parent         = &core_l4_ick,
1790         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1792         .flags          = CLOCK_IN_OMAP343X,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk i2c3_ick = {
1797         .name           = "i2c_ick",
1798         .id             = 3,
1799         .parent         = &core_l4_ick,
1800         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1802         .flags          = CLOCK_IN_OMAP343X,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk i2c2_ick = {
1807         .name           = "i2c_ick",
1808         .id             = 2,
1809         .parent         = &core_l4_ick,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1812         .flags          = CLOCK_IN_OMAP343X,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk i2c1_ick = {
1817         .name           = "i2c_ick",
1818         .id             = 1,
1819         .parent         = &core_l4_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1822         .flags          = CLOCK_IN_OMAP343X,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk uart2_ick = {
1827         .name           = "uart2_ick",
1828         .parent         = &core_l4_ick,
1829         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1831         .flags          = CLOCK_IN_OMAP343X,
1832         .recalc         = &followparent_recalc,
1833 };
1834
1835 static struct clk uart1_ick = {
1836         .name           = "uart1_ick",
1837         .parent         = &core_l4_ick,
1838         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1840         .flags          = CLOCK_IN_OMAP343X,
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk gpt11_ick = {
1845         .name           = "gpt11_ick",
1846         .parent         = &core_l4_ick,
1847         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1849         .flags          = CLOCK_IN_OMAP343X,
1850         .recalc         = &followparent_recalc,
1851 };
1852
1853 static struct clk gpt10_ick = {
1854         .name           = "gpt10_ick",
1855         .parent         = &core_l4_ick,
1856         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1858         .flags          = CLOCK_IN_OMAP343X,
1859         .recalc         = &followparent_recalc,
1860 };
1861
1862 static struct clk mcbsp5_ick = {
1863         .name           = "mcbsp_ick",
1864         .id             = 5,
1865         .parent         = &core_l4_ick,
1866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1868         .flags          = CLOCK_IN_OMAP343X,
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcbsp1_ick = {
1873         .name           = "mcbsp_ick",
1874         .id             = 1,
1875         .parent         = &core_l4_ick,
1876         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1878         .flags          = CLOCK_IN_OMAP343X,
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk fac_ick = {
1883         .name           = "fac_ick",
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1887         .flags          = CLOCK_IN_OMAP3430ES1,
1888         .recalc         = &followparent_recalc,
1889 };
1890
1891 static struct clk mailboxes_ick = {
1892         .name           = "mailboxes_ick",
1893         .parent         = &core_l4_ick,
1894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1896         .flags          = CLOCK_IN_OMAP343X,
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk omapctrl_ick = {
1901         .name           = "omapctrl_ick",
1902         .parent         = &core_l4_ick,
1903         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1904         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1905         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1906         .recalc         = &followparent_recalc,
1907 };
1908
1909 /* SSI_L4_ICK based clocks */
1910
1911 static struct clk ssi_l4_ick = {
1912         .name           = "ssi_l4_ick",
1913         .parent         = &l4_ick,
1914         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1915                                 PARENT_CONTROLS_CLOCK,
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk ssi_ick = {
1920         .name           = "ssi_ick",
1921         .parent         = &ssi_l4_ick,
1922         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1924         .flags          = CLOCK_IN_OMAP343X,
1925         .recalc         = &followparent_recalc,
1926 };
1927
1928 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1929  * but l4_ick makes more sense to me */
1930
1931 static const struct clksel usb_l4_clksel[] = {
1932         { .parent = &l4_ick, .rates = div2_rates },
1933         { .parent = NULL },
1934 };
1935
1936 static struct clk usb_l4_ick = {
1937         .name           = "usb_l4_ick",
1938         .parent         = &l4_ick,
1939         .init           = &omap2_init_clksel_parent,
1940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1942         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1943         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1944         .clksel         = usb_l4_clksel,
1945         .flags          = CLOCK_IN_OMAP3430ES1,
1946         .recalc         = &omap2_clksel_recalc,
1947 };
1948
1949 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1950
1951 /* SECURITY_L4_ICK2 based clocks */
1952
1953 static struct clk security_l4_ick2 = {
1954         .name           = "security_l4_ick2",
1955         .parent         = &l4_ick,
1956         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1957                                 PARENT_CONTROLS_CLOCK,
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk aes1_ick = {
1962         .name           = "aes1_ick",
1963         .parent         = &security_l4_ick2,
1964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1965         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk rng_ick = {
1971         .name           = "rng_ick",
1972         .parent         = &security_l4_ick2,
1973         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1974         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1975         .flags          = CLOCK_IN_OMAP343X,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk sha11_ick = {
1980         .name           = "sha11_ick",
1981         .parent         = &security_l4_ick2,
1982         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1983         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1984         .flags          = CLOCK_IN_OMAP343X,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk des1_ick = {
1989         .name           = "des1_ick",
1990         .parent         = &security_l4_ick2,
1991         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1992         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1993         .flags          = CLOCK_IN_OMAP343X,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 /* DSS */
1998 static const struct clksel dss1_alwon_fck_clksel[] = {
1999         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2000         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2001         { .parent = NULL }
2002 };
2003
2004 static struct clk dss1_alwon_fck = {
2005         .name           = "dss1_alwon_fck",
2006         .parent         = &dpll4_m4x2_ck,
2007         .init           = &omap2_init_clksel_parent,
2008         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2009         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2010         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2011         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2012         .clksel         = dss1_alwon_fck_clksel,
2013         .flags          = CLOCK_IN_OMAP343X,
2014         .recalc         = &omap2_clksel_recalc,
2015 };
2016
2017 static struct clk dss_tv_fck = {
2018         .name           = "dss_tv_fck",
2019         .parent         = &omap_54m_fck,
2020         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2021         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2022         .flags          = CLOCK_IN_OMAP343X,
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 static struct clk dss_96m_fck = {
2027         .name           = "dss_96m_fck",
2028         .parent         = &omap_96m_fck,
2029         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2030         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2031         .flags          = CLOCK_IN_OMAP343X,
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk dss2_alwon_fck = {
2036         .name           = "dss2_alwon_fck",
2037         .parent         = &sys_ck,
2038         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2039         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2040         .flags          = CLOCK_IN_OMAP343X,
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 static struct clk dss_ick = {
2045         /* Handles both L3 and L4 clocks */
2046         .name           = "dss_ick",
2047         .parent         = &l4_ick,
2048         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2049         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2050         .flags          = CLOCK_IN_OMAP343X,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 /* CAM */
2055
2056 static const struct clksel cam_mclk_clksel[] = {
2057         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2058         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2059         { .parent = NULL }
2060 };
2061
2062 static struct clk cam_mclk = {
2063         .name           = "cam_mclk",
2064         .parent         = &dpll4_m5x2_ck,
2065         .init           = &omap2_init_clksel_parent,
2066         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2067         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2068         .clksel         = cam_mclk_clksel,
2069         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2070         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2071         .flags          = CLOCK_IN_OMAP343X,
2072         .recalc         = &omap2_clksel_recalc,
2073 };
2074
2075 static struct clk cam_l3_ick = {
2076         .name           = "cam_l3_ick",
2077         .parent         = &l3_ick,
2078         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2079         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2080         .flags          = CLOCK_IN_OMAP343X,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk cam_l4_ick = {
2085         .name           = "cam_l4_ick",
2086         .parent         = &l4_ick,
2087         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2088         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2089         .flags          = CLOCK_IN_OMAP343X,
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 /* USBHOST - 3430ES2 only */
2094
2095 static struct clk usbhost_120m_fck = {
2096         .name           = "usbhost_120m_fck",
2097         .parent         = &omap_120m_fck,
2098         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2099         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2100         .flags          = CLOCK_IN_OMAP3430ES2,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 static struct clk usbhost_48m_fck = {
2105         .name           = "usbhost_48m_fck",
2106         .parent         = &omap_48m_fck,
2107         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2108         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2109         .flags          = CLOCK_IN_OMAP3430ES2,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk usbhost_l3_ick = {
2114         .name           = "usbhost_l3_ick",
2115         .parent         = &l3_ick,
2116         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2117         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2118         .flags          = CLOCK_IN_OMAP3430ES2,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk usbhost_l4_ick = {
2123         .name           = "usbhost_l4_ick",
2124         .parent         = &l4_ick,
2125         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2126         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2127         .flags          = CLOCK_IN_OMAP3430ES2,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk usbhost_sar_fck = {
2132         .name           = "usbhost_sar_fck",
2133         .parent         = &osc_sys_ck,
2134         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2135         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2136         .flags          = CLOCK_IN_OMAP3430ES2,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 /* WKUP */
2141
2142 static const struct clksel_rate usim_96m_rates[] = {
2143         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2144         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2145         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2146         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2147         { .div = 0 },
2148 };
2149
2150 static const struct clksel_rate usim_120m_rates[] = {
2151         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2152         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2153         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2154         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2155         { .div = 0 },
2156 };
2157
2158 static const struct clksel usim_clksel[] = {
2159         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2160         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2161         { .parent = &sys_ck,            .rates = div2_rates },
2162         { .parent = NULL },
2163 };
2164
2165 /* 3430ES2 only */
2166 static struct clk usim_fck = {
2167         .name           = "usim_fck",
2168         .init           = &omap2_init_clksel_parent,
2169         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2170         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2171         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2172         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2173         .clksel         = usim_clksel,
2174         .flags          = CLOCK_IN_OMAP3430ES2,
2175         .recalc         = &omap2_clksel_recalc,
2176 };
2177
2178 static struct clk gpt1_fck = {
2179         .name           = "gpt1_fck",
2180         .init           = &omap2_init_clksel_parent,
2181         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2182         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2183         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2184         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2185         .clksel         = omap343x_gpt_clksel,
2186         .flags          = CLOCK_IN_OMAP343X,
2187         .recalc         = &omap2_clksel_recalc,
2188 };
2189
2190 static struct clk wkup_32k_fck = {
2191         .name           = "wkup_32k_fck",
2192         .parent         = &omap_32k_fck,
2193         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2194         .recalc         = &followparent_recalc,
2195 };
2196
2197 static struct clk gpio1_fck = {
2198         .name           = "gpio1_fck",
2199         .parent         = &wkup_32k_fck,
2200         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2201         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2202         .flags          = CLOCK_IN_OMAP343X,
2203         .recalc         = &followparent_recalc,
2204 };
2205
2206 static struct clk wdt2_fck = {
2207         .name           = "wdt2_fck",
2208         .parent         = &wkup_32k_fck,
2209         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2210         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2211         .flags          = CLOCK_IN_OMAP343X,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk wkup_l4_ick = {
2216         .name           = "wkup_l4_ick",
2217         .parent         = &sys_ck,
2218         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 /* 3430ES2 only */
2223 /* Never specifically named in the TRM, so we have to infer a likely name */
2224 static struct clk usim_ick = {
2225         .name           = "usim_ick",
2226         .parent         = &wkup_l4_ick,
2227         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2228         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2229         .flags          = CLOCK_IN_OMAP3430ES2,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk wdt2_ick = {
2234         .name           = "wdt2_ick",
2235         .parent         = &wkup_l4_ick,
2236         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2237         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2238         .flags          = CLOCK_IN_OMAP343X,
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk wdt1_ick = {
2243         .name           = "wdt1_ick",
2244         .parent         = &wkup_l4_ick,
2245         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2246         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2247         .flags          = CLOCK_IN_OMAP343X,
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 static struct clk gpio1_ick = {
2252         .name           = "gpio1_ick",
2253         .parent         = &wkup_l4_ick,
2254         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2255         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2256         .flags          = CLOCK_IN_OMAP343X,
2257         .recalc         = &followparent_recalc,
2258 };
2259
2260 static struct clk omap_32ksync_ick = {
2261         .name           = "omap_32ksync_ick",
2262         .parent         = &wkup_l4_ick,
2263         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2264         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2265         .flags          = CLOCK_IN_OMAP343X,
2266         .recalc         = &followparent_recalc,
2267 };
2268
2269 static struct clk gpt12_ick = {
2270         .name           = "gpt12_ick",
2271         .parent         = &wkup_l4_ick,
2272         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2273         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2274         .flags          = CLOCK_IN_OMAP343X,
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 static struct clk gpt1_ick = {
2279         .name           = "gpt1_ick",
2280         .parent         = &wkup_l4_ick,
2281         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2282         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2283         .flags          = CLOCK_IN_OMAP343X,
2284         .recalc         = &followparent_recalc,
2285 };
2286
2287
2288
2289 /* PER clock domain */
2290
2291 static struct clk per_96m_fck = {
2292         .name           = "per_96m_fck",
2293         .parent         = &omap_96m_alwon_fck,
2294         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2295                                 PARENT_CONTROLS_CLOCK,
2296         .recalc         = &followparent_recalc,
2297 };
2298
2299 static struct clk per_48m_fck = {
2300         .name           = "per_48m_fck",
2301         .parent         = &omap_48m_fck,
2302         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2303                                 PARENT_CONTROLS_CLOCK,
2304         .recalc         = &followparent_recalc,
2305 };
2306
2307 static struct clk uart3_fck = {
2308         .name           = "uart3_fck",
2309         .parent         = &per_48m_fck,
2310         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2311         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2312         .flags          = CLOCK_IN_OMAP343X,
2313         .recalc         = &followparent_recalc,
2314 };
2315
2316 static struct clk gpt2_fck = {
2317         .name           = "gpt2_fck",
2318         .init           = &omap2_init_clksel_parent,
2319         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2320         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2321         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2322         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2323         .clksel         = omap343x_gpt_clksel,
2324         .flags          = CLOCK_IN_OMAP343X,
2325         .recalc         = &omap2_clksel_recalc,
2326 };
2327
2328 static struct clk gpt3_fck = {
2329         .name           = "gpt3_fck",
2330         .init           = &omap2_init_clksel_parent,
2331         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2332         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2333         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2334         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2335         .clksel         = omap343x_gpt_clksel,
2336         .flags          = CLOCK_IN_OMAP343X,
2337         .recalc         = &omap2_clksel_recalc,
2338 };
2339
2340 static struct clk gpt4_fck = {
2341         .name           = "gpt4_fck",
2342         .init           = &omap2_init_clksel_parent,
2343         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2344         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2345         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2346         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2347         .clksel         = omap343x_gpt_clksel,
2348         .flags          = CLOCK_IN_OMAP343X,
2349         .recalc         = &omap2_clksel_recalc,
2350 };
2351
2352 static struct clk gpt5_fck = {
2353         .name           = "gpt5_fck",
2354         .init           = &omap2_init_clksel_parent,
2355         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2356         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2357         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2358         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2359         .clksel         = omap343x_gpt_clksel,
2360         .flags          = CLOCK_IN_OMAP343X,
2361         .recalc         = &omap2_clksel_recalc,
2362 };
2363
2364 static struct clk gpt6_fck = {
2365         .name           = "gpt6_fck",
2366         .init           = &omap2_init_clksel_parent,
2367         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2368         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2369         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2370         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2371         .clksel         = omap343x_gpt_clksel,
2372         .flags          = CLOCK_IN_OMAP343X,
2373         .recalc         = &omap2_clksel_recalc,
2374 };
2375
2376 static struct clk gpt7_fck = {
2377         .name           = "gpt7_fck",
2378         .init           = &omap2_init_clksel_parent,
2379         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2380         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2381         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2382         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2383         .clksel         = omap343x_gpt_clksel,
2384         .flags          = CLOCK_IN_OMAP343X,
2385         .recalc         = &omap2_clksel_recalc,
2386 };
2387
2388 static struct clk gpt8_fck = {
2389         .name           = "gpt8_fck",
2390         .init           = &omap2_init_clksel_parent,
2391         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2392         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2393         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2394         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2395         .clksel         = omap343x_gpt_clksel,
2396         .flags          = CLOCK_IN_OMAP343X,
2397         .recalc         = &omap2_clksel_recalc,
2398 };
2399
2400 static struct clk gpt9_fck = {
2401         .name           = "gpt9_fck",
2402         .init           = &omap2_init_clksel_parent,
2403         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2404         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2405         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2406         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2407         .clksel         = omap343x_gpt_clksel,
2408         .flags          = CLOCK_IN_OMAP343X,
2409         .recalc         = &omap2_clksel_recalc,
2410 };
2411
2412 static struct clk per_32k_alwon_fck = {
2413         .name           = "per_32k_alwon_fck",
2414         .parent         = &omap_32k_fck,
2415         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 static struct clk gpio6_fck = {
2420         .name           = "gpio6_fck",
2421         .parent         = &per_32k_alwon_fck,
2422         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2423         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2424         .flags          = CLOCK_IN_OMAP343X,
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 static struct clk gpio5_fck = {
2429         .name           = "gpio5_fck",
2430         .parent         = &per_32k_alwon_fck,
2431         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2432         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2433         .flags          = CLOCK_IN_OMAP343X,
2434         .recalc         = &followparent_recalc,
2435 };
2436
2437 static struct clk gpio4_fck = {
2438         .name           = "gpio4_fck",
2439         .parent         = &per_32k_alwon_fck,
2440         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2442         .flags          = CLOCK_IN_OMAP343X,
2443         .recalc         = &followparent_recalc,
2444 };
2445
2446 static struct clk gpio3_fck = {
2447         .name           = "gpio3_fck",
2448         .parent         = &per_32k_alwon_fck,
2449         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2450         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2451         .flags          = CLOCK_IN_OMAP343X,
2452         .recalc         = &followparent_recalc,
2453 };
2454
2455 static struct clk gpio2_fck = {
2456         .name           = "gpio2_fck",
2457         .parent         = &per_32k_alwon_fck,
2458         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2459         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2460         .flags          = CLOCK_IN_OMAP343X,
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk wdt3_fck = {
2465         .name           = "wdt3_fck",
2466         .parent         = &per_32k_alwon_fck,
2467         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2469         .flags          = CLOCK_IN_OMAP343X,
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk per_l4_ick = {
2474         .name           = "per_l4_ick",
2475         .parent         = &l4_ick,
2476         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2477                                 PARENT_CONTROLS_CLOCK,
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 static struct clk gpio6_ick = {
2482         .name           = "gpio6_ick",
2483         .parent         = &per_l4_ick,
2484         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2485         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2486         .flags          = CLOCK_IN_OMAP343X,
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk gpio5_ick = {
2491         .name           = "gpio5_ick",
2492         .parent         = &per_l4_ick,
2493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2494         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2495         .flags          = CLOCK_IN_OMAP343X,
2496         .recalc         = &followparent_recalc,
2497 };
2498
2499 static struct clk gpio4_ick = {
2500         .name           = "gpio4_ick",
2501         .parent         = &per_l4_ick,
2502         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2503         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2504         .flags          = CLOCK_IN_OMAP343X,
2505         .recalc         = &followparent_recalc,
2506 };
2507
2508 static struct clk gpio3_ick = {
2509         .name           = "gpio3_ick",
2510         .parent         = &per_l4_ick,
2511         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2512         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2513         .flags          = CLOCK_IN_OMAP343X,
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517 static struct clk gpio2_ick = {
2518         .name           = "gpio2_ick",
2519         .parent         = &per_l4_ick,
2520         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2521         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2522         .flags          = CLOCK_IN_OMAP343X,
2523         .recalc         = &followparent_recalc,
2524 };
2525
2526 static struct clk wdt3_ick = {
2527         .name           = "wdt3_ick",
2528         .parent         = &per_l4_ick,
2529         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2530         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2531         .flags          = CLOCK_IN_OMAP343X,
2532         .recalc         = &followparent_recalc,
2533 };
2534
2535 static struct clk uart3_ick = {
2536         .name           = "uart3_ick",
2537         .parent         = &per_l4_ick,
2538         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2539         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2540         .flags          = CLOCK_IN_OMAP343X,
2541         .recalc         = &followparent_recalc,
2542 };
2543
2544 static struct clk gpt9_ick = {
2545         .name           = "gpt9_ick",
2546         .parent         = &per_l4_ick,
2547         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2548         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2549         .flags          = CLOCK_IN_OMAP343X,
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static struct clk gpt8_ick = {
2554         .name           = "gpt8_ick",
2555         .parent         = &per_l4_ick,
2556         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2557         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2558         .flags          = CLOCK_IN_OMAP343X,
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk gpt7_ick = {
2563         .name           = "gpt7_ick",
2564         .parent         = &per_l4_ick,
2565         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2566         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2567         .flags          = CLOCK_IN_OMAP343X,
2568         .recalc         = &followparent_recalc,
2569 };
2570
2571 static struct clk gpt6_ick = {
2572         .name           = "gpt6_ick",
2573         .parent         = &per_l4_ick,
2574         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2575         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2576         .flags          = CLOCK_IN_OMAP343X,
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk gpt5_ick = {
2581         .name           = "gpt5_ick",
2582         .parent         = &per_l4_ick,
2583         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2584         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2585         .flags          = CLOCK_IN_OMAP343X,
2586         .recalc         = &followparent_recalc,
2587 };
2588
2589 static struct clk gpt4_ick = {
2590         .name           = "gpt4_ick",
2591         .parent         = &per_l4_ick,
2592         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2593         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2594         .flags          = CLOCK_IN_OMAP343X,
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk gpt3_ick = {
2599         .name           = "gpt3_ick",
2600         .parent         = &per_l4_ick,
2601         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2602         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2603         .flags          = CLOCK_IN_OMAP343X,
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk gpt2_ick = {
2608         .name           = "gpt2_ick",
2609         .parent         = &per_l4_ick,
2610         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2612         .flags          = CLOCK_IN_OMAP343X,
2613         .recalc         = &followparent_recalc,
2614 };
2615
2616 static struct clk mcbsp2_ick = {
2617         .name           = "mcbsp_ick",
2618         .id             = 2,
2619         .parent         = &per_l4_ick,
2620         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2622         .flags          = CLOCK_IN_OMAP343X,
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk mcbsp3_ick = {
2627         .name           = "mcbsp_ick",
2628         .id             = 3,
2629         .parent         = &per_l4_ick,
2630         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2632         .flags          = CLOCK_IN_OMAP343X,
2633         .recalc         = &followparent_recalc,
2634 };
2635
2636 static struct clk mcbsp4_ick = {
2637         .name           = "mcbsp_ick",
2638         .id             = 4,
2639         .parent         = &per_l4_ick,
2640         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2642         .flags          = CLOCK_IN_OMAP343X,
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 static const struct clksel mcbsp_234_clksel[] = {
2647         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2648         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2649         { .parent = NULL }
2650 };
2651
2652 static struct clk mcbsp2_fck = {
2653         .name           = "mcbsp_fck",
2654         .id             = 2,
2655         .init           = &omap2_init_clksel_parent,
2656         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2657         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2658         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2659         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2660         .clksel         = mcbsp_234_clksel,
2661         .flags          = CLOCK_IN_OMAP343X,
2662         .recalc         = &omap2_clksel_recalc,
2663 };
2664
2665 static struct clk mcbsp3_fck = {
2666         .name           = "mcbsp_fck",
2667         .id             = 3,
2668         .init           = &omap2_init_clksel_parent,
2669         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2670         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2671         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2672         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2673         .clksel         = mcbsp_234_clksel,
2674         .flags          = CLOCK_IN_OMAP343X,
2675         .recalc         = &omap2_clksel_recalc,
2676 };
2677
2678 static struct clk mcbsp4_fck = {
2679         .name           = "mcbsp_fck",
2680         .id             = 4,
2681         .init           = &omap2_init_clksel_parent,
2682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2683         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2684         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2685         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2686         .clksel         = mcbsp_234_clksel,
2687         .flags          = CLOCK_IN_OMAP343X,
2688         .recalc         = &omap2_clksel_recalc,
2689 };
2690
2691 /* EMU clocks */
2692
2693 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2694
2695 static const struct clksel_rate emu_src_sys_rates[] = {
2696         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2697         { .div = 0 },
2698 };
2699
2700 static const struct clksel_rate emu_src_core_rates[] = {
2701         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2702         { .div = 0 },
2703 };
2704
2705 static const struct clksel_rate emu_src_per_rates[] = {
2706         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2707         { .div = 0 },
2708 };
2709
2710 static const struct clksel_rate emu_src_mpu_rates[] = {
2711         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2712         { .div = 0 },
2713 };
2714
2715 static const struct clksel emu_src_clksel[] = {
2716         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2717         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2718         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2719         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2720         { .parent = NULL },
2721 };
2722
2723 /*
2724  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2725  * to switch the source of some of the EMU clocks.
2726  * XXX Are there CLKEN bits for these EMU clks?
2727  */
2728 static struct clk emu_src_ck = {
2729         .name           = "emu_src_ck",
2730         .init           = &omap2_init_clksel_parent,
2731         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2732         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2733         .clksel         = emu_src_clksel,
2734         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2735         .recalc         = &omap2_clksel_recalc,
2736 };
2737
2738 static const struct clksel_rate pclk_emu_rates[] = {
2739         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2740         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2741         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2742         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2743         { .div = 0 },
2744 };
2745
2746 static const struct clksel pclk_emu_clksel[] = {
2747         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2748         { .parent = NULL },
2749 };
2750
2751 static struct clk pclk_fck = {
2752         .name           = "pclk_fck",
2753         .init           = &omap2_init_clksel_parent,
2754         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2755         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2756         .clksel         = pclk_emu_clksel,
2757         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2758         .recalc         = &omap2_clksel_recalc,
2759 };
2760
2761 static const struct clksel_rate pclkx2_emu_rates[] = {
2762         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2763         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2764         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2765         { .div = 0 },
2766 };
2767
2768 static const struct clksel pclkx2_emu_clksel[] = {
2769         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2770         { .parent = NULL },
2771 };
2772
2773 static struct clk pclkx2_fck = {
2774         .name           = "pclkx2_fck",
2775         .init           = &omap2_init_clksel_parent,
2776         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2777         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2778         .clksel         = pclkx2_emu_clksel,
2779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2780         .recalc         = &omap2_clksel_recalc,
2781 };
2782
2783 static const struct clksel atclk_emu_clksel[] = {
2784         { .parent = &emu_src_ck, .rates = div2_rates },
2785         { .parent = NULL },
2786 };
2787
2788 static struct clk atclk_fck = {
2789         .name           = "atclk_fck",
2790         .init           = &omap2_init_clksel_parent,
2791         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2792         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2793         .clksel         = atclk_emu_clksel,
2794         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2795         .recalc         = &omap2_clksel_recalc,
2796 };
2797
2798 static struct clk traceclk_src_fck = {
2799         .name           = "traceclk_src_fck",
2800         .init           = &omap2_init_clksel_parent,
2801         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2802         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2803         .clksel         = emu_src_clksel,
2804         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2805         .recalc         = &omap2_clksel_recalc,
2806 };
2807
2808 static const struct clksel_rate traceclk_rates[] = {
2809         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2810         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2811         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2812         { .div = 0 },
2813 };
2814
2815 static const struct clksel traceclk_clksel[] = {
2816         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2817         { .parent = NULL },
2818 };
2819
2820 static struct clk traceclk_fck = {
2821         .name           = "traceclk_fck",
2822         .init           = &omap2_init_clksel_parent,
2823         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2824         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2825         .clksel         = traceclk_clksel,
2826         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2827         .recalc         = &omap2_clksel_recalc,
2828 };
2829
2830 /* SR clocks */
2831
2832 /* SmartReflex fclk (VDD1) */
2833 static struct clk sr1_fck = {
2834         .name           = "sr1_fck",
2835         .parent         = &sys_ck,
2836         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2837         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2838         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2839         .recalc         = &followparent_recalc,
2840 };
2841
2842 /* SmartReflex fclk (VDD2) */
2843 static struct clk sr2_fck = {
2844         .name           = "sr2_fck",
2845         .parent         = &sys_ck,
2846         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2847         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2848         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2849         .recalc         = &followparent_recalc,
2850 };
2851
2852 static struct clk sr_l4_ick = {
2853         .name           = "sr_l4_ick",
2854         .parent         = &l4_ick,
2855         .flags          = CLOCK_IN_OMAP343X,
2856         .recalc         = &followparent_recalc,
2857 };
2858
2859 /* SECURE_32K_FCK clocks */
2860
2861 static struct clk gpt12_fck = {
2862         .name           = "gpt12_fck",
2863         .parent         = &secure_32k_fck,
2864         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2865         .recalc         = &followparent_recalc,
2866 };
2867
2868 static struct clk wdt1_fck = {
2869         .name           = "wdt1_fck",
2870         .parent         = &secure_32k_fck,
2871         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2872         .recalc         = &followparent_recalc,
2873 };
2874
2875 static struct clk *onchip_34xx_clks[] __initdata = {
2876         &omap_32k_fck,
2877         &virt_12m_ck,
2878         &virt_13m_ck,
2879         &virt_16_8m_ck,
2880         &virt_19_2m_ck,
2881         &virt_26m_ck,
2882         &virt_38_4m_ck,
2883         &osc_sys_ck,
2884         &sys_ck,
2885         &sys_altclk,
2886         &mcbsp_clks,
2887         &sys_clkout1,
2888         &dpll1_ck,
2889         &dpll1_x2_ck,
2890         &dpll1_x2m2_ck,
2891         &dpll2_ck,
2892         &dpll2_m2_ck,
2893         &dpll3_ck,
2894         &core_ck,
2895         &dpll3_x2_ck,
2896         &dpll3_m2_ck,
2897         &dpll3_m2x2_ck,
2898         &dpll3_m3_ck,
2899         &dpll3_m3x2_ck,
2900         &emu_core_alwon_ck,
2901         &dpll4_ck,
2902         &dpll4_x2_ck,
2903         &omap_96m_alwon_fck,
2904         &omap_96m_fck,
2905         &cm_96m_fck,
2906         &virt_omap_54m_fck,
2907         &omap_54m_fck,
2908         &omap_48m_fck,
2909         &omap_12m_fck,
2910         &dpll4_m2_ck,
2911         &dpll4_m2x2_ck,
2912         &dpll4_m3_ck,
2913         &dpll4_m3x2_ck,
2914         &dpll4_m4_ck,
2915         &dpll4_m4x2_ck,
2916         &dpll4_m5_ck,
2917         &dpll4_m5x2_ck,
2918         &dpll4_m6_ck,
2919         &dpll4_m6x2_ck,
2920         &emu_per_alwon_ck,
2921         &dpll5_ck,
2922         &dpll5_m2_ck,
2923         &omap_120m_fck,
2924         &clkout2_src_ck,
2925         &sys_clkout2,
2926         &corex2_fck,
2927         &dpll1_fck,
2928         &mpu_ck,
2929         &arm_fck,
2930         &emu_mpu_alwon_ck,
2931         &dpll2_fck,
2932         &iva2_ck,
2933         &l3_ick,
2934         &l4_ick,
2935         &rm_ick,
2936         &gfx_l3_fck,
2937         &gfx_l3_ick,
2938         &gfx_cg1_ck,
2939         &gfx_cg2_ck,
2940         &sgx_fck,
2941         &sgx_ick,
2942         &d2d_26m_fck,
2943         &gpt10_fck,
2944         &gpt11_fck,
2945         &cpefuse_fck,
2946         &ts_fck,
2947         &usbtll_fck,
2948         &core_96m_fck,
2949         &mmchs3_fck,
2950         &mmchs2_fck,
2951         &mspro_fck,
2952         &mmchs1_fck,
2953         &i2c3_fck,
2954         &i2c2_fck,
2955         &i2c1_fck,
2956         &mcbsp5_fck,
2957         &mcbsp1_fck,
2958         &core_48m_fck,
2959         &mcspi4_fck,
2960         &mcspi3_fck,
2961         &mcspi2_fck,
2962         &mcspi1_fck,
2963         &uart2_fck,
2964         &uart1_fck,
2965         &fshostusb_fck,
2966         &core_12m_fck,
2967         &hdq_fck,
2968         &ssi_ssr_fck,
2969         &ssi_sst_fck,
2970         &core_l3_ick,
2971         &hsotgusb_ick,
2972         &sdrc_ick,
2973         &gpmc_fck,
2974         &security_l3_ick,
2975         &pka_ick,
2976         &core_l4_ick,
2977         &usbtll_ick,
2978         &mmchs3_ick,
2979         &icr_ick,
2980         &aes2_ick,
2981         &sha12_ick,
2982         &des2_ick,
2983         &mmchs2_ick,
2984         &mmchs1_ick,
2985         &mspro_ick,
2986         &hdq_ick,
2987         &mcspi4_ick,
2988         &mcspi3_ick,
2989         &mcspi2_ick,
2990         &mcspi1_ick,
2991         &i2c3_ick,
2992         &i2c2_ick,
2993         &i2c1_ick,
2994         &uart2_ick,
2995         &uart1_ick,
2996         &gpt11_ick,
2997         &gpt10_ick,
2998         &mcbsp5_ick,
2999         &mcbsp1_ick,
3000         &fac_ick,
3001         &mailboxes_ick,
3002         &omapctrl_ick,
3003         &ssi_l4_ick,
3004         &ssi_ick,
3005         &usb_l4_ick,
3006         &security_l4_ick2,
3007         &aes1_ick,
3008         &rng_ick,
3009         &sha11_ick,
3010         &des1_ick,
3011         &dss1_alwon_fck,
3012         &dss_tv_fck,
3013         &dss_96m_fck,
3014         &dss2_alwon_fck,
3015         &dss_ick,
3016         &cam_mclk,
3017         &cam_l3_ick,
3018         &cam_l4_ick,
3019         &usbhost_120m_fck,
3020         &usbhost_48m_fck,
3021         &usbhost_l3_ick,
3022         &usbhost_l4_ick,
3023         &usbhost_sar_fck,
3024         &usim_fck,
3025         &gpt1_fck,
3026         &wkup_32k_fck,
3027         &gpio1_fck,
3028         &wdt2_fck,
3029         &wkup_l4_ick,
3030         &usim_ick,
3031         &wdt2_ick,
3032         &wdt1_ick,
3033         &gpio1_ick,
3034         &omap_32ksync_ick,
3035         &gpt12_ick,
3036         &gpt1_ick,
3037         &per_96m_fck,
3038         &per_48m_fck,
3039         &uart3_fck,
3040         &gpt2_fck,
3041         &gpt3_fck,
3042         &gpt4_fck,
3043         &gpt5_fck,
3044         &gpt6_fck,
3045         &gpt7_fck,
3046         &gpt8_fck,
3047         &gpt9_fck,
3048         &per_32k_alwon_fck,
3049         &gpio6_fck,
3050         &gpio5_fck,
3051         &gpio4_fck,
3052         &gpio3_fck,
3053         &gpio2_fck,
3054         &wdt3_fck,
3055         &per_l4_ick,
3056         &gpio6_ick,
3057         &gpio5_ick,
3058         &gpio4_ick,
3059         &gpio3_ick,
3060         &gpio2_ick,
3061         &wdt3_ick,
3062         &uart3_ick,
3063         &gpt9_ick,
3064         &gpt8_ick,
3065         &gpt7_ick,
3066         &gpt6_ick,
3067         &gpt5_ick,
3068         &gpt4_ick,
3069         &gpt3_ick,
3070         &gpt2_ick,
3071         &mcbsp2_ick,
3072         &mcbsp3_ick,
3073         &mcbsp4_ick,
3074         &mcbsp2_fck,
3075         &mcbsp3_fck,
3076         &mcbsp4_fck,
3077         &emu_src_ck,
3078         &pclk_fck,
3079         &pclkx2_fck,
3080         &atclk_fck,
3081         &traceclk_src_fck,
3082         &traceclk_fck,
3083         &sr1_fck,
3084         &sr2_fck,
3085         &sr_l4_ick,
3086         &secure_32k_fck,
3087         &gpt12_fck,
3088         &wdt1_fck,
3089 };
3090
3091 #endif