arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  19
  20 #include "clock.h"
  21
  22 #include "prm.h"
  23 #include "cm.h"
  24 #include "prm-regbits-24xx.h"
  25 #include "cm-regbits-24xx.h"
  26 #include "sdrc.h"
  27
  28 static void omap2_table_mpu_recalc(struct clk * clk);
  29 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  30 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  31 static void omap2_sys_clk_recalc(struct clk * clk);
  32 static void omap2_osc_clk_recalc(struct clk * clk);
  33 static void omap2_sys_clk_recalc(struct clk * clk);
  34 static void omap2_dpll_recalc(struct clk * clk);
  35 static int omap2_clk_fixed_enable(struct clk * clk);
  36 static void omap2_clk_fixed_disable(struct clk * clk);
  37 static int omap2_enable_osc_ck(struct clk * clk);
  38 static void omap2_disable_osc_ck(struct clk * clk);
  39 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate);
  40
  41 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  42  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  43  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  44  */
  45 struct prcm_config {
  46         unsigned long xtal_speed;       /* crystal rate */
  47         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  48         unsigned long mpu_speed;        /* speed of MPU */
  49         unsigned long cm_clksel_mpu;    /* mpu divider */
  50         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  51         unsigned long cm_clksel_gfx;    /* gfx dividers */
  52         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  53         unsigned long cm_clksel1_pll;   /* m,n */
  54         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  55         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  56         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  57         unsigned char flags;
  58 };
  59
  60 /*
  61  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  62  * These configurations are characterized by voltage and speed for clocks.
  63  * The device is only validated for certain combinations. One way to express
  64  * these combinations is via the 'ratio's' which the clocks operate with
  65  * respect to each other. These ratio sets are for a given voltage/DPLL
  66  * setting. All configurations can be described by a DPLL setting and a ratio
  67  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  68  *
  69  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  70  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  71  * 2430 (iva2.1, NOdsp, mdm)
  72  */
  73
  74 /* Core fields for cm_clksel, not ratio governed */
  75 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  76 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  77 #define RX_CLKSEL_SSI                   (0x5 << 20)
  78
  79 /*-------------------------------------------------------------------------
  80  * Voltage/DPLL ratios
  81  *-------------------------------------------------------------------------*/
  82
  83 /* 2430 Ratio's, 2430-Ratio Config 1 */
  84 #define R1_CLKSEL_L3                    (4 << 0)
  85 #define R1_CLKSEL_L4                    (2 << 5)
  86 #define R1_CLKSEL_USB                   (4 << 25)
  87 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  88                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  89                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  90 #define R1_CLKSEL_MPU                   (2 << 0)
  91 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  92 #define R1_CLKSEL_DSP                   (2 << 0)
  93 #define R1_CLKSEL_DSP_IF                (2 << 5)
  94 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  95 #define R1_CLKSEL_GFX                   (2 << 0)
  96 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  97 #define R1_CLKSEL_MDM                   (4 << 0)
  98 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  99
 100 /* 2430-Ratio Config 2 */
 101 #define R2_CLKSEL_L3                    (6 << 0)
 102 #define R2_CLKSEL_L4                    (2 << 5)
 103 #define R2_CLKSEL_USB                   (2 << 25)
 104 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 105                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 106                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 107 #define R2_CLKSEL_MPU                   (2 << 0)
 108 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 109 #define R2_CLKSEL_DSP                   (2 << 0)
 110 #define R2_CLKSEL_DSP_IF                (3 << 5)
 111 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 112 #define R2_CLKSEL_GFX                   (2 << 0)
 113 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 114 #define R2_CLKSEL_MDM                   (6 << 0)
 115 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 116
 117 /* 2430-Ratio Bootm (BYPASS) */
 118 #define RB_CLKSEL_L3                    (1 << 0)
 119 #define RB_CLKSEL_L4                    (1 << 5)
 120 #define RB_CLKSEL_USB                   (1 << 25)
 121 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 122                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 123                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 124 #define RB_CLKSEL_MPU                   (1 << 0)
 125 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 126 #define RB_CLKSEL_DSP                   (1 << 0)
 127 #define RB_CLKSEL_DSP_IF                (1 << 5)
 128 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 129 #define RB_CLKSEL_GFX                   (1 << 0)
 130 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 131 #define RB_CLKSEL_MDM                   (1 << 0)
 132 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 133
 134 /* 2420 Ratio Equivalents */
 135 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 136 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 137
 138 /* 2420-PRCM III 532MHz core */
 139 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 140 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 141 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 142 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 143                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 144                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 145                                         RIII_CLKSEL_L3
 146 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 147 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 148 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 149 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 150 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 151 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 152 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 153 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 154                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 155                                         RIII_CLKSEL_DSP
 156 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 157 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 158
 159 /* 2420-PRCM II 600MHz core */
 160 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 161 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 162 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 163 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 164                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 165                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 166                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 167 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 168 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 169 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 170 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 171 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 172 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 173 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 174 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 175                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 176                                         RII_CLKSEL_DSP
 177 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 178 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 179
 180 /* 2420-PRCM I 660MHz core */
 181 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 182 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 183 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 184 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 185                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 186                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 187                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 188 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 189 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 190 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 191 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 192 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 193 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 194 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 195 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 196                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 197                                         RI_CLKSEL_DSP
 198 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 199 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 200
 201 /* 2420-PRCM VII (boot) */
 202 #define RVII_CLKSEL_L3                  (1 << 0)
 203 #define RVII_CLKSEL_L4                  (1 << 5)
 204 #define RVII_CLKSEL_DSS1                (1 << 8)
 205 #define RVII_CLKSEL_DSS2                (0 << 13)
 206 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 207 #define RVII_CLKSEL_SSI                 (1 << 20)
 208 #define RVII_CLKSEL_USB                 (1 << 25)
 209
 210 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 211                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 212                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 213
 214 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 215 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 216
 217 #define RVII_CLKSEL_DSP                 (1 << 0)
 218 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 219 #define RVII_SYNC_DSP                   (0 << 7)
 220 #define RVII_CLKSEL_IVA                 (1 << 8)
 221 #define RVII_SYNC_IVA                   (0 << 13)
 222 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 223                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 224
 225 #define RVII_CLKSEL_GFX                 (1 << 0)
 226 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 227
 228 /*-------------------------------------------------------------------------
 229  * 2430 Target modes: Along with each configuration the CPU has several
 230  * modes which goes along with them. Modes mainly are the addition of
 231  * describe DPLL combinations to go along with a ratio.
 232  *-------------------------------------------------------------------------*/
 233
 234 /* Hardware governed */
 235 #define MX_48M_SRC                      (0 << 3)
 236 #define MX_54M_SRC                      (0 << 5)
 237 #define MX_APLLS_CLIKIN_12              (3 << 23)
 238 #define MX_APLLS_CLIKIN_13              (2 << 23)
 239 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 240
 241 /*
 242  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 243  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 244  */
 245 #define M5A_DPLL_MULT_12                (133 << 12)
 246 #define M5A_DPLL_DIV_12                 (5 << 8)
 247 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 248                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 249                                         MX_APLLS_CLIKIN_12
 250 #define M5A_DPLL_MULT_13                (61 << 12)
 251 #define M5A_DPLL_DIV_13                 (2 << 8)
 252 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 253                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 254                                         MX_APLLS_CLIKIN_13
 255 #define M5A_DPLL_MULT_19                (55 << 12)
 256 #define M5A_DPLL_DIV_19                 (3 << 8)
 257 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 258                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 259                                         MX_APLLS_CLIKIN_19_2
 260 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 261 #define M5B_DPLL_MULT_12                (50 << 12)
 262 #define M5B_DPLL_DIV_12                 (2 << 8)
 263 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 264                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 265                                         MX_APLLS_CLIKIN_12
 266 #define M5B_DPLL_MULT_13                (200 << 12)
 267 #define M5B_DPLL_DIV_13                 (12 << 8)
 268
 269 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 271                                         MX_APLLS_CLIKIN_13
 272 #define M5B_DPLL_MULT_19                (125 << 12)
 273 #define M5B_DPLL_DIV_19                 (31 << 8)
 274 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 275                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 276                                         MX_APLLS_CLIKIN_19_2
 277 /*
 278  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 279  */
 280 #define M4_DPLL_MULT_12                 (133 << 12)
 281 #define M4_DPLL_DIV_12                  (3 << 8)
 282 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 283                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 284                                         MX_APLLS_CLIKIN_12
 285
 286 #define M4_DPLL_MULT_13                 (399 << 12)
 287 #define M4_DPLL_DIV_13                  (12 << 8)
 288 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 289                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 290                                         MX_APLLS_CLIKIN_13
 291
 292 #define M4_DPLL_MULT_19                 (145 << 12)
 293 #define M4_DPLL_DIV_19                  (6 << 8)
 294 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 295                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 296                                         MX_APLLS_CLIKIN_19_2
 297
 298 /*
 299  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 300  */
 301 #define M3_DPLL_MULT_12                 (55 << 12)
 302 #define M3_DPLL_DIV_12                  (1 << 8)
 303 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 304                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 305                                         MX_APLLS_CLIKIN_12
 306 #define M3_DPLL_MULT_13                 (76 << 12)
 307 #define M3_DPLL_DIV_13                  (2 << 8)
 308 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 309                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 310                                         MX_APLLS_CLIKIN_13
 311 #define M3_DPLL_MULT_19                 (17 << 12)
 312 #define M3_DPLL_DIV_19                  (0 << 8)
 313 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 314                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 315                                         MX_APLLS_CLIKIN_19_2
 316
 317 /*
 318  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 319  */
 320 #define M2_DPLL_MULT_12                 (55 << 12)
 321 #define M2_DPLL_DIV_12                  (1 << 8)
 322 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 323                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 324                                         MX_APLLS_CLIKIN_12
 325
 326 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 327  * relock time issue */
 328 /* Core frequency changed from 330/165 to 329/164 MHz*/
 329 #define M2_DPLL_MULT_13                 (76 << 12)
 330 #define M2_DPLL_DIV_13                  (2 << 8)
 331 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 332                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 333                                         MX_APLLS_CLIKIN_13
 334
 335 #define M2_DPLL_MULT_19                 (17 << 12)
 336 #define M2_DPLL_DIV_19                  (0 << 8)
 337 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 338                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 339                                         MX_APLLS_CLIKIN_19_2
 340
 341 /* boot (boot) */
 342 #define MB_DPLL_MULT                    (1 << 12)
 343 #define MB_DPLL_DIV                     (0 << 8)
 344 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 345                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 346
 347 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 348                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 349
 350 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 351                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 352
 353 /*
 354  * 2430 - chassis (sedna)
 355  * 165 (ratio1) same as above #2
 356  * 150 (ratio1)
 357  * 133 (ratio2) same as above #4
 358  * 110 (ratio2) same as above #3
 359  * 104 (ratio2)
 360  * boot (boot)
 361  */
 362
 363 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 364 #define MI_DPLL_MULT_12                 (55 << 12)
 365 #define MI_DPLL_DIV_12                  (1 << 8)
 366 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 367                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 368                                         MX_APLLS_CLIKIN_12
 369
 370 /*
 371  * 2420 Equivalent - mode registers
 372  * PRCM II , target DPLL = 2*300MHz = 600MHz
 373  */
 374 #define MII_DPLL_MULT_12                (50 << 12)
 375 #define MII_DPLL_DIV_12                 (1 << 8)
 376 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 377                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 378                                         MX_APLLS_CLIKIN_12
 379 #define MII_DPLL_MULT_13                (300 << 12)
 380 #define MII_DPLL_DIV_13                 (12 << 8)
 381 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 382                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 383                                         MX_APLLS_CLIKIN_13
 384
 385 /* PRCM III target DPLL = 2*266 = 532MHz*/
 386 #define MIII_DPLL_MULT_12               (133 << 12)
 387 #define MIII_DPLL_DIV_12                (5 << 8)
 388 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 389                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 390                                         MX_APLLS_CLIKIN_12
 391 #define MIII_DPLL_MULT_13               (266 << 12)
 392 #define MIII_DPLL_DIV_13                (12 << 8)
 393 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 394                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 395                                         MX_APLLS_CLIKIN_13
 396
 397 /* PRCM VII (boot bypass) */
 398 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 399 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 400
 401 /* High and low operation value */
 402 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 403 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 404
 405 /* MPU speed defines */
 406 #define S12M    12000000
 407 #define S13M    13000000
 408 #define S19M    19200000
 409 #define S26M    26000000
 410 #define S100M   100000000
 411 #define S133M   133000000
 412 #define S150M   150000000
 413 #define S164M   164000000
 414 #define S165M   165000000
 415 #define S199M   199000000
 416 #define S200M   200000000
 417 #define S266M   266000000
 418 #define S300M   300000000
 419 #define S329M   329000000
 420 #define S330M   330000000
 421 #define S399M   399000000
 422 #define S400M   400000000
 423 #define S532M   532000000
 424 #define S600M   600000000
 425 #define S658M   658000000
 426 #define S660M   660000000
 427 #define S798M   798000000
 428
 429 /*-------------------------------------------------------------------------
 430  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 431  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 432  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 433  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 434  *
 435  * Filling in table based on H4 boards and 2430-SDPs variants available.
 436  * There are quite a few more rates combinations which could be defined.
 437  *
 438  * When multiple values are defined the start up will try and choose the
 439  * fastest one. If a 'fast' value is defined, then automatically, the /2
 440  * one should be included as it can be used.    Generally having more that
 441  * one fast set does not make sense, as static timings need to be changed
 442  * to change the set.    The exception is the bypass setting which is
 443  * availble for low power bypass.
 444  *
 445  * Note: This table needs to be sorted, fastest to slowest.
 446  *-------------------------------------------------------------------------*/
 447 static struct prcm_config rate_table[] = {
 448         /* PRCM I - FAST */
 449         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 450                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 451                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 452                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 453                 RATE_IN_242X},
 454
 455         /* PRCM II - FAST */
 456         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 457                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 458                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 459                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 460                 RATE_IN_242X},
 461
 462         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 463                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 464                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 465                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 466                 RATE_IN_242X},
 467
 468         /* PRCM III - FAST */
 469         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 470                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 471                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 472                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 473                 RATE_IN_242X},
 474
 475         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 476                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 477                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 478                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 479                 RATE_IN_242X},
 480
 481         /* PRCM II - SLOW */
 482         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 483                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 484                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 485                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 486                 RATE_IN_242X},
 487
 488         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 489                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 490                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 491                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 492                 RATE_IN_242X},
 493
 494         /* PRCM III - SLOW */
 495         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 496                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 497                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 498                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 499                 RATE_IN_242X},
 500
 501         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 502                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 503                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 504                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 505                 RATE_IN_242X},
 506
 507         /* PRCM-VII (boot-bypass) */
 508         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 509                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 510                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 511                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 512                 RATE_IN_242X},
 513
 514         /* PRCM-VII (boot-bypass) */
 515         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 516                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 517                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 518                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 519                 RATE_IN_242X},
 520
 521         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 522         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 523                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 524                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 525                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 526                 SDRC_RFR_CTRL_133MHz,
 527                 RATE_IN_243X},
 528
 529         /* PRCM #2 - ratio1 (ES2) - FAST */
 530         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 531                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 532                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 533                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 534                 SDRC_RFR_CTRL_165MHz,
 535                 RATE_IN_243X},
 536
 537         /* PRCM #5a - ratio1 - FAST */
 538         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 539                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 540                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 541                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 542                 SDRC_RFR_CTRL_133MHz,
 543                 RATE_IN_243X},
 544
 545         /* PRCM #5b - ratio1 - FAST */
 546         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 547                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 548                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 549                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 550                 SDRC_RFR_CTRL_100MHz,
 551                 RATE_IN_243X},
 552
 553         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 554         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 555                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 556                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 557                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 558                 SDRC_RFR_CTRL_133MHz,
 559                 RATE_IN_243X},
 560
 561         /* PRCM #2 - ratio1 (ES2) - SLOW */
 562         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 563                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 564                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 565                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 566                 SDRC_RFR_CTRL_165MHz,
 567                 RATE_IN_243X},
 568
 569         /* PRCM #5a - ratio1 - SLOW */
 570         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 571                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 572                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 573                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 574                 SDRC_RFR_CTRL_133MHz,
 575                 RATE_IN_243X},
 576
 577         /* PRCM #5b - ratio1 - SLOW*/
 578         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 579                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 580                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 581                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 582                 SDRC_RFR_CTRL_100MHz,
 583                 RATE_IN_243X},
 584
 585         /* PRCM-boot/bypass */
 586         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 587                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 588                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 589                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 590                 SDRC_RFR_CTRL_BYPASS,
 591                 RATE_IN_243X},
 592
 593         /* PRCM-boot/bypass */
 594         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 595                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 596                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 597                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 598                 SDRC_RFR_CTRL_BYPASS,
 599                 RATE_IN_243X},
 600
 601         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 602 };
 603
 604 /*-------------------------------------------------------------------------
 605  * 24xx clock tree.
 606  *
 607  * NOTE:In many cases here we are assigning a 'default' parent. In many
 608  *      cases the parent is selectable. The get/set parent calls will also
 609  *      switch sources.
 610  *
 611  *      Many some clocks say always_enabled, but they can be auto idled for
 612  *      power savings. They will always be available upon clock request.
 613  *
 614  *      Several sources are given initial rates which may be wrong, this will
 615  *      be fixed up in the init func.
 616  *
 617  *      Things are broadly separated below by clock domains. It is
 618  *      noteworthy that most periferals have dependencies on multiple clock
 619  *      domains. Many get their interface clocks from the L4 domain, but get
 620  *      functional clocks from fixed sources or other core domain derived
 621  *      clocks.
 622  *-------------------------------------------------------------------------*/
 623
 624 /* Base external input clocks */
 625 static struct clk func_32k_ck = {
 626         .name           = "func_32k_ck",
 627         .rate           = 32000,
 628         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 629                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 630         .recalc         = &propagate_rate,
 631 };
 632
 633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 634 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 635         .name           = "osc_ck",
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_PROPAGATES,
 638         .enable         = &omap2_enable_osc_ck,
 639         .disable        = &omap2_disable_osc_ck,
 640         .recalc         = &omap2_osc_clk_recalc,
 641 };
 642
 643 /* With out modem likely 12MHz, with modem likely 13MHz */
 644 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 645         .name           = "sys_ck",             /* ~ ref_clk also */
 646         .parent         = &osc_ck,
 647         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 648                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 649         .recalc         = &omap2_sys_clk_recalc,
 650 };
 651
 652 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 653         .name           = "alt_ck",
 654         .rate           = 54000000,
 655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 656                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 657         .recalc         = &propagate_rate,
 658 };
 659
 660 /*
 661  * Analog domain root source clocks
 662  */
 663
 664 /* dpll_ck, is broken out in to special cases through clksel */
 665 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 666  * deal with this
 667  */
 668
 669 static const struct dpll_data dpll_dd = {
 670         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 671         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 672         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 673 };
 674
 675 static struct clk dpll_ck = {
 676         .name           = "dpll_ck",
 677         .parent         = &sys_ck,              /* Can be func_32k also */
 678         .dpll_data      = &dpll_dd,
 679         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 680                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 681         .recalc         = &omap2_dpll_recalc,
 682         .set_rate       = &omap2_reprogram_dpll,
 683 };
 684
 685 static struct clk apll96_ck = {
 686         .name           = "apll96_ck",
 687         .parent         = &sys_ck,
 688         .rate           = 96000000,
 689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 690                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 691         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 692         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 693         .enable         = &omap2_clk_fixed_enable,
 694         .disable        = &omap2_clk_fixed_disable,
 695         .recalc         = &propagate_rate,
 696 };
 697
 698 static struct clk apll54_ck = {
 699         .name           = "apll54_ck",
 700         .parent         = &sys_ck,
 701         .rate           = 54000000,
 702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 703                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 704         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 705         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 706         .enable         = &omap2_clk_fixed_enable,
 707         .disable        = &omap2_clk_fixed_disable,
 708         .recalc         = &propagate_rate,
 709 };
 710
 711 /*
 712  * PRCM digital base sources
 713  */
 714
 715 /* func_54m_ck */
 716
 717 static const struct clksel_rate func_54m_apll54_rates[] = {
 718         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 719         { .div = 0 },
 720 };
 721
 722 static const struct clksel_rate func_54m_alt_rates[] = {
 723         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 724         { .div = 0 },
 725 };
 726
 727 static const struct clksel func_54m_clksel[] = {
 728         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 729         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 730         { .parent = NULL },
 731 };
 732
 733 static struct clk func_54m_ck = {
 734         .name           = "func_54m_ck",
 735         .parent         = &apll54_ck,   /* can also be alt_clk */
 736         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 737                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 738         .init           = &omap2_init_clksel_parent,
 739         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 740         .clksel_mask    = OMAP24XX_54M_SOURCE,
 741         .clksel         = func_54m_clksel,
 742         .recalc         = &omap2_clksel_recalc,
 743 };
 744
 745 static struct clk core_ck = {
 746         .name           = "core_ck",
 747         .parent         = &dpll_ck,             /* can also be 32k */
 748         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 749                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 750         .recalc         = &followparent_recalc,
 751 };
 752
 753 /* func_96m_ck */
 754 static const struct clksel_rate func_96m_apll96_rates[] = {
 755         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 756         { .div = 0 },
 757 };
 758
 759 static const struct clksel_rate func_96m_alt_rates[] = {
 760         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 761         { .div = 0 },
 762 };
 763
 764 static const struct clksel func_96m_clksel[] = {
 765         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 766         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 767         { .parent = NULL }
 768 };
 769
 770 /* The parent of this clock is not selectable on 2420. */
 771 static struct clk func_96m_ck = {
 772         .name           = "func_96m_ck",
 773         .parent         = &apll96_ck,
 774         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 775                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 776         .init           = &omap2_init_clksel_parent,
 777         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 778         .clksel_mask    = OMAP2430_96M_SOURCE,
 779         .clksel         = func_96m_clksel,
 780         .recalc         = &omap2_clksel_recalc,
 781         .round_rate     = &omap2_clksel_round_rate,
 782         .set_rate       = &omap2_clksel_set_rate
 783 };
 784
 785 /* func_48m_ck */
 786
 787 static const struct clksel_rate func_48m_apll96_rates[] = {
 788         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 789         { .div = 0 },
 790 };
 791
 792 static const struct clksel_rate func_48m_alt_rates[] = {
 793         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 794         { .div = 0 },
 795 };
 796
 797 static const struct clksel func_48m_clksel[] = {
 798         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 799         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 800         { .parent = NULL }
 801 };
 802
 803 static struct clk func_48m_ck = {
 804         .name           = "func_48m_ck",
 805         .parent         = &apll96_ck,    /* 96M or Alt */
 806         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 807                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 810         .clksel_mask    = OMAP24XX_48M_SOURCE,
 811         .clksel         = func_48m_clksel,
 812         .recalc         = &omap2_clksel_recalc,
 813         .round_rate     = &omap2_clksel_round_rate,
 814         .set_rate       = &omap2_clksel_set_rate
 815 };
 816
 817 static struct clk func_12m_ck = {
 818         .name           = "func_12m_ck",
 819         .parent         = &func_48m_ck,
 820         .fixed_div      = 4,
 821         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 822                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 823         .recalc         = &omap2_fixed_divisor_recalc,
 824 };
 825
 826 /* Secure timer, only available in secure mode */
 827 static struct clk wdt1_osc_ck = {
 828         .name           = "ck_wdt1_osc",
 829         .parent         = &osc_ck,
 830         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 831         .recalc         = &followparent_recalc,
 832 };
 833
 834 /*
 835  * The common_clkout* clksel_rate structs are common to
 836  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 837  * sys_clkout2_* are 2420-only, so the
 838  * clksel_rate flags fields are inaccurate for those clocks. This is
 839  * harmless since access to those clocks are gated by the struct clk
 840  * flags fields, which mark them as 2420-only.
 841  */
 842 static const struct clksel_rate common_clkout_src_core_rates[] = {
 843         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 844         { .div = 0 }
 845 };
 846
 847 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 848         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 849         { .div = 0 }
 850 };
 851
 852 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 853         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 854         { .div = 0 }
 855 };
 856
 857 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 858         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 859         { .div = 0 }
 860 };
 861
 862 static const struct clksel common_clkout_src_clksel[] = {
 863         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 864         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 865         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 866         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 867         { .parent = NULL }
 868 };
 869
 870 static struct clk sys_clkout_src = {
 871         .name           = "sys_clkout_src",
 872         .parent         = &func_54m_ck,
 873         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 874                                 RATE_PROPAGATES,
 875         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 876         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 877         .init           = &omap2_init_clksel_parent,
 878         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 879         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 880         .clksel         = common_clkout_src_clksel,
 881         .recalc         = &omap2_clksel_recalc,
 882         .round_rate     = &omap2_clksel_round_rate,
 883         .set_rate       = &omap2_clksel_set_rate
 884 };
 885
 886 static const struct clksel_rate common_clkout_rates[] = {
 887         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 888         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 889         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 890         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 891         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 892         { .div = 0 },
 893 };
 894
 895 static const struct clksel sys_clkout_clksel[] = {
 896         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 897         { .parent = NULL }
 898 };
 899
 900 static struct clk sys_clkout = {
 901         .name           = "sys_clkout",
 902         .parent         = &sys_clkout_src,
 903         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 904                                 PARENT_CONTROLS_CLOCK,
 905         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 906         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 907         .clksel         = sys_clkout_clksel,
 908         .recalc         = &omap2_clksel_recalc,
 909         .round_rate     = &omap2_clksel_round_rate,
 910         .set_rate       = &omap2_clksel_set_rate
 911 };
 912
 913 /* In 2430, new in 2420 ES2 */
 914 static struct clk sys_clkout2_src = {
 915         .name           = "sys_clkout2_src",
 916         .parent         = &func_54m_ck,
 917         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 918         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 919         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 920         .init           = &omap2_init_clksel_parent,
 921         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 922         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 923         .clksel         = common_clkout_src_clksel,
 924         .recalc         = &omap2_clksel_recalc,
 925         .round_rate     = &omap2_clksel_round_rate,
 926         .set_rate       = &omap2_clksel_set_rate
 927 };
 928
 929 static const struct clksel sys_clkout2_clksel[] = {
 930         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 931         { .parent = NULL }
 932 };
 933
 934 /* In 2430, new in 2420 ES2 */
 935 static struct clk sys_clkout2 = {
 936         .name           = "sys_clkout2",
 937         .parent         = &sys_clkout2_src,
 938         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 939         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 940         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 941         .clksel         = sys_clkout2_clksel,
 942         .recalc         = &omap2_clksel_recalc,
 943         .round_rate     = &omap2_clksel_round_rate,
 944         .set_rate       = &omap2_clksel_set_rate
 945 };
 946
 947 static struct clk emul_ck = {
 948         .name           = "emul_ck",
 949         .parent         = &func_54m_ck,
 950         .flags          = CLOCK_IN_OMAP242X,
 951         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 952         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 953         .recalc         = &followparent_recalc,
 954
 955 };
 956
 957 /*
 958  * MPU clock domain
 959  *      Clocks:
 960  *              MPU_FCLK, MPU_ICLK
 961  *              INT_M_FCLK, INT_M_I_CLK
 962  *
 963  * - Individual clocks are hardware managed.
 964  * - Base divider comes from: CM_CLKSEL_MPU
 965  *
 966  */
 967 static const struct clksel_rate mpu_core_rates[] = {
 968         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 969         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 970         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 971         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 972         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 973         { .div = 0 },
 974 };
 975
 976 static const struct clksel mpu_clksel[] = {
 977         { .parent = &core_ck, .rates = mpu_core_rates },
 978         { .parent = NULL }
 979 };
 980
 981 static struct clk mpu_ck = {    /* Control cpu */
 982         .name           = "mpu_ck",
 983         .parent         = &core_ck,
 984         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 985                                 ALWAYS_ENABLED | DELAYED_APP |
 986                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 987         .init           = &omap2_init_clksel_parent,
 988         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 989         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 990         .clksel         = mpu_clksel,
 991         .recalc         = &omap2_clksel_recalc,
 992         .round_rate     = &omap2_clksel_round_rate,
 993         .set_rate       = &omap2_clksel_set_rate
 994 };
 995
 996 /*
 997  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 998  * Clocks:
 999  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1000  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1001  *
1002  * Won't be too specific here. The core clock comes into this block
1003  * it is divided then tee'ed. One branch goes directly to xyz enable
1004  * controls. The other branch gets further divided by 2 then possibly
1005  * routed into a synchronizer and out of clocks abc.
1006  */
1007 static const struct clksel_rate dsp_fck_core_rates[] = {
1008         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1009         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1010         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1011         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1012         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1013         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1014         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1015         { .div = 0 },
1016 };
1017
1018 static const struct clksel dsp_fck_clksel[] = {
1019         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1020         { .parent = NULL }
1021 };
1022
1023 static struct clk dsp_fck = {
1024         .name           = "dsp_fck",
1025         .parent         = &core_ck,
1026         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1027                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1028         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1029         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1030         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1031         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1032         .clksel         = dsp_fck_clksel,
1033         .recalc         = &omap2_clksel_recalc,
1034         .round_rate     = &omap2_clksel_round_rate,
1035         .set_rate       = &omap2_clksel_set_rate
1036 };
1037
1038 /* DSP interface clock */
1039 static const struct clksel_rate dsp_irate_ick_rates[] = {
1040         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1041         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1042         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1043         { .div = 0 },
1044 };
1045
1046 static const struct clksel dsp_irate_ick_clksel[] = {
1047         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1048         { .parent = NULL }
1049 };
1050
1051 /*
1052  * This clock does not exist as such in the TRM, but is added to
1053  * separate source selection from  XXX
1054  */
1055 static struct clk dsp_irate_ick = {
1056         .name           = "dsp_irate_ick",
1057         .parent         = &dsp_fck,
1058         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1059                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1060         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1061         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1062         .clksel         = dsp_irate_ick_clksel,
1063         .recalc         = &omap2_clksel_recalc,
1064         .round_rate     = &omap2_clksel_round_rate,
1065         .set_rate             = &omap2_clksel_set_rate
1066 };
1067
1068 /* 2420 only */
1069 static struct clk dsp_ick = {
1070         .name           = "dsp_ick",     /* apparently ipi and isp */
1071         .parent         = &dsp_irate_ick,
1072         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1073         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1074         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1075 };
1076
1077 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1078 static struct clk iva2_1_ick = {
1079         .name           = "iva2_1_ick",
1080         .parent         = &dsp_irate_ick,
1081         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1082         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1083         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1084 };
1085
1086 static struct clk iva1_ifck = {
1087         .name           = "iva1_ifck",
1088         .parent         = &core_ck,
1089         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1090                                 RATE_PROPAGATES | DELAYED_APP,
1091         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1092         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1093         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1094         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1095         .clksel         = dsp_fck_clksel,
1096         .recalc         = &omap2_clksel_recalc,
1097         .round_rate     = &omap2_clksel_round_rate,
1098         .set_rate       = &omap2_clksel_set_rate
1099 };
1100
1101 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1102 static struct clk iva1_mpu_int_ifck = {
1103         .name           = "iva1_mpu_int_ifck",
1104         .parent         = &iva1_ifck,
1105         .flags          = CLOCK_IN_OMAP242X,
1106         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1107         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1108         .fixed_div      = 2,
1109         .recalc         = &omap2_fixed_divisor_recalc,
1110 };
1111
1112 /*
1113  * L3 clock domain
1114  * L3 clocks are used for both interface and functional clocks to
1115  * multiple entities. Some of these clocks are completely managed
1116  * by hardware, and some others allow software control. Hardware
1117  * managed ones general are based on directly CLK_REQ signals and
1118  * various auto idle settings. The functional spec sets many of these
1119  * as 'tie-high' for their enables.
1120  *
1121  * I-CLOCKS:
1122  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1123  *      CAM, HS-USB.
1124  * F-CLOCK
1125  *      SSI.
1126  *
1127  * GPMC memories and SDRC have timing and clock sensitive registers which
1128  * may very well need notification when the clock changes. Currently for low
1129  * operating points, these are taken care of in sleep.S.
1130  */
1131 static const struct clksel_rate core_l3_core_rates[] = {
1132         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1133         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1134         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1135         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1136         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1137         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1138         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1139         { .div = 0 }
1140 };
1141
1142 static const struct clksel core_l3_clksel[] = {
1143         { .parent = &core_ck, .rates = core_l3_core_rates },
1144         { .parent = NULL }
1145 };
1146
1147 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1148         .name           = "core_l3_ck",
1149         .parent         = &core_ck,
1150         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1151                                 ALWAYS_ENABLED | DELAYED_APP |
1152                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1153         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1154         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1155         .clksel         = core_l3_clksel,
1156         .recalc         = &omap2_clksel_recalc,
1157         .round_rate     = &omap2_clksel_round_rate,
1158         .set_rate       = &omap2_clksel_set_rate
1159 };
1160
1161 /* usb_l4_ick */
1162 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1163         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1164         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1165         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1166         { .div = 0 }
1167 };
1168
1169 static const struct clksel usb_l4_ick_clksel[] = {
1170         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1171         { .parent = NULL },
1172 };
1173
1174 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1175         .name           = "usb_l4_ick",
1176         .parent         = &core_l3_ck,
1177         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1178                                 DELAYED_APP | CONFIG_PARTICIPANT,
1179         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1180         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1181         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1182         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1183         .clksel         = usb_l4_ick_clksel,
1184         .recalc         = &omap2_clksel_recalc,
1185         .round_rate     = &omap2_clksel_round_rate,
1186         .set_rate       = &omap2_clksel_set_rate
1187 };
1188
1189 /*
1190  * SSI is in L3 management domain, its direct parent is core not l3,
1191  * many core power domain entities are grouped into the L3 clock
1192  * domain.
1193  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1194  *
1195  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1196  */
1197 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1198         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1199         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1200         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1201         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1202         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1203         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1204         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1205         { .div = 0 }
1206 };
1207
1208 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1209         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1210         { .parent = NULL }
1211 };
1212
1213 static struct clk ssi_ssr_sst_fck = {
1214         .name           = "ssi_fck",
1215         .parent         = &core_ck,
1216         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1217                                 DELAYED_APP,
1218         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1219         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1220         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1221         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1222         .clksel         = ssi_ssr_sst_fck_clksel,
1223         .recalc         = &omap2_clksel_recalc,
1224         .round_rate     = &omap2_clksel_round_rate,
1225         .set_rate       = &omap2_clksel_set_rate
1226 };
1227
1228 /*
1229  * GFX clock domain
1230  *      Clocks:
1231  * GFX_FCLK, GFX_ICLK
1232  * GFX_CG1(2d), GFX_CG2(3d)
1233  *
1234  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1235  * The 2d and 3d clocks run at a hardware determined
1236  * divided value of fclk.
1237  *
1238  */
1239 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1240
1241 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1242 static const struct clksel gfx_fck_clksel[] = {
1243         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1244         { .parent = NULL },
1245 };
1246
1247 static struct clk gfx_3d_fck = {
1248         .name           = "gfx_3d_fck",
1249         .parent         = &core_l3_ck,
1250         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1251         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1252         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1253         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1254         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1255         .clksel         = gfx_fck_clksel,
1256         .recalc         = &omap2_clksel_recalc,
1257         .round_rate     = &omap2_clksel_round_rate,
1258         .set_rate       = &omap2_clksel_set_rate
1259 };
1260
1261 static struct clk gfx_2d_fck = {
1262         .name           = "gfx_2d_fck",
1263         .parent         = &core_l3_ck,
1264         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1265         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1266         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1267         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1268         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1269         .clksel         = gfx_fck_clksel,
1270         .recalc         = &omap2_clksel_recalc,
1271         .round_rate     = &omap2_clksel_round_rate,
1272         .set_rate       = &omap2_clksel_set_rate
1273 };
1274
1275 static struct clk gfx_ick = {
1276         .name           = "gfx_ick",            /* From l3 */
1277         .parent         = &core_l3_ck,
1278         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1279         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1280         .enable_bit     = OMAP_EN_GFX_SHIFT,
1281         .recalc         = &followparent_recalc,
1282 };
1283
1284 /*
1285  * Modem clock domain (2430)
1286  *      CLOCKS:
1287  *              MDM_OSC_CLK
1288  *              MDM_ICLK
1289  * These clocks are usable in chassis mode only.
1290  */
1291 static const struct clksel_rate mdm_ick_core_rates[] = {
1292         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1293         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1294         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1295         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1296         { .div = 0 }
1297 };
1298
1299 static const struct clksel mdm_ick_clksel[] = {
1300         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1301         { .parent = NULL }
1302 };
1303
1304 static struct clk mdm_ick = {           /* used both as a ick and fck */
1305         .name           = "mdm_ick",
1306         .parent         = &core_ck,
1307         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1308         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1309         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1310         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1311         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1312         .clksel         = mdm_ick_clksel,
1313         .recalc         = &omap2_clksel_recalc,
1314         .round_rate     = &omap2_clksel_round_rate,
1315         .set_rate       = &omap2_clksel_set_rate
1316 };
1317
1318 static struct clk mdm_osc_ck = {
1319         .name           = "mdm_osc_ck",
1320         .parent         = &osc_ck,
1321         .flags          = CLOCK_IN_OMAP243X,
1322         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1323         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1324         .recalc         = &followparent_recalc,
1325 };
1326
1327 /*
1328  * L4 clock management domain
1329  *
1330  * This domain contains lots of interface clocks from the L4 interface, some
1331  * functional clocks.   Fixed APLL functional source clocks are managed in
1332  * this domain.
1333  */
1334 static const struct clksel_rate l4_core_l3_rates[] = {
1335         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1336         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1337         { .div = 0 }
1338 };
1339
1340 static const struct clksel l4_clksel[] = {
1341         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1342         { .parent = NULL }
1343 };
1344
1345 static struct clk l4_ck = {             /* used both as an ick and fck */
1346         .name           = "l4_ck",
1347         .parent         = &core_l3_ck,
1348         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1349                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1350         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1351         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1352         .clksel         = l4_clksel,
1353         .recalc         = &omap2_clksel_recalc,
1354         .round_rate     = &omap2_clksel_round_rate,
1355         .set_rate       = &omap2_clksel_set_rate
1356 };
1357
1358 static struct clk ssi_l4_ick = {
1359         .name           = "ssi_l4_ick",
1360         .parent         = &l4_ck,
1361         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1363         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 /*
1368  * DSS clock domain
1369  * CLOCKs:
1370  * DSS_L4_ICLK, DSS_L3_ICLK,
1371  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1372  *
1373  * DSS is both initiator and target.
1374  */
1375 /* XXX Add RATE_NOT_VALIDATED */
1376
1377 static const struct clksel_rate dss1_fck_sys_rates[] = {
1378         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1379         { .div = 0 }
1380 };
1381
1382 static const struct clksel_rate dss1_fck_core_rates[] = {
1383         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1384         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1385         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1386         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1387         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1388         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1389         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1390         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1391         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1392         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1393         { .div = 0 }
1394 };
1395
1396 static const struct clksel dss1_fck_clksel[] = {
1397         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1398         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1399         { .parent = NULL },
1400 };
1401
1402 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1403         .name           = "dss_ick",
1404         .parent         = &l4_ck,       /* really both l3 and l4 */
1405         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1406         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1407         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk dss1_fck = {
1412         .name           = "dss1_fck",
1413         .parent         = &core_ck,             /* Core or sys */
1414         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1415                                 DELAYED_APP,
1416         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1418         .init           = &omap2_init_clksel_parent,
1419         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1420         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1421         .clksel         = dss1_fck_clksel,
1422         .recalc         = &omap2_clksel_recalc,
1423         .round_rate     = &omap2_clksel_round_rate,
1424         .set_rate       = &omap2_clksel_set_rate
1425 };
1426
1427 static const struct clksel_rate dss2_fck_sys_rates[] = {
1428         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1429         { .div = 0 }
1430 };
1431
1432 static const struct clksel_rate dss2_fck_48m_rates[] = {
1433         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1434         { .div = 0 }
1435 };
1436
1437 static const struct clksel dss2_fck_clksel[] = {
1438         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1439         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1440         { .parent = NULL }
1441 };
1442
1443 static struct clk dss2_fck = {          /* Alt clk used in power management */
1444         .name           = "dss2_fck",
1445         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1446         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1447                                 DELAYED_APP,
1448         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1449         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1450         .init           = &omap2_init_clksel_parent,
1451         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1452         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1453         .clksel         = dss2_fck_clksel,
1454         .recalc         = &followparent_recalc,
1455 };
1456
1457 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1458         .name           = "dss_54m_fck",        /* 54m tv clk */
1459         .parent         = &func_54m_ck,
1460         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 /*
1467  * CORE power domain ICLK & FCLK defines.
1468  * Many of the these can have more than one possible parent. Entries
1469  * here will likely have an L4 interface parent, and may have multiple
1470  * functional clock parents.
1471  */
1472 static const struct clksel_rate gpt_alt_rates[] = {
1473         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1474         { .div = 0 }
1475 };
1476
1477 static const struct clksel omap24xx_gpt_clksel[] = {
1478         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1479         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1480         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1481         { .parent = NULL },
1482 };
1483
1484 static struct clk gpt1_ick = {
1485         .name           = "gpt1_ick",
1486         .parent         = &l4_ck,
1487         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1488         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1489         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1490         .recalc         = &followparent_recalc,
1491 };
1492
1493 static struct clk gpt1_fck = {
1494         .name           = "gpt1_fck",
1495         .parent         = &func_32k_ck,
1496         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1497         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1498         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1499         .init           = &omap2_init_clksel_parent,
1500         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1501         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1502         .clksel         = omap24xx_gpt_clksel,
1503         .recalc         = &omap2_clksel_recalc,
1504         .round_rate     = &omap2_clksel_round_rate,
1505         .set_rate       = &omap2_clksel_set_rate
1506 };
1507
1508 static struct clk gpt2_ick = {
1509         .name           = "gpt2_ick",
1510         .parent         = &l4_ck,
1511         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1512         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1513         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1514         .recalc         = &followparent_recalc,
1515 };
1516
1517 static struct clk gpt2_fck = {
1518         .name           = "gpt2_fck",
1519         .parent         = &func_32k_ck,
1520         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1521         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1522         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1523         .init           = &omap2_init_clksel_parent,
1524         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1525         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1526         .clksel         = omap24xx_gpt_clksel,
1527         .recalc         = &omap2_clksel_recalc,
1528 };
1529
1530 static struct clk gpt3_ick = {
1531         .name           = "gpt3_ick",
1532         .parent         = &l4_ck,
1533         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1534         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1535         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1536         .recalc         = &followparent_recalc,
1537 };
1538
1539 static struct clk gpt3_fck = {
1540         .name           = "gpt3_fck",
1541         .parent         = &func_32k_ck,
1542         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1545         .init           = &omap2_init_clksel_parent,
1546         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1547         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1548         .clksel         = omap24xx_gpt_clksel,
1549         .recalc         = &omap2_clksel_recalc,
1550 };
1551
1552 static struct clk gpt4_ick = {
1553         .name           = "gpt4_ick",
1554         .parent         = &l4_ck,
1555         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1556         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1557         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk gpt4_fck = {
1562         .name           = "gpt4_fck",
1563         .parent         = &func_32k_ck,
1564         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1565         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1567         .init           = &omap2_init_clksel_parent,
1568         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1569         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1570         .clksel         = omap24xx_gpt_clksel,
1571         .recalc         = &omap2_clksel_recalc,
1572 };
1573
1574 static struct clk gpt5_ick = {
1575         .name           = "gpt5_ick",
1576         .parent         = &l4_ck,
1577         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1578         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1579         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpt5_fck = {
1584         .name           = "gpt5_fck",
1585         .parent         = &func_32k_ck,
1586         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1589         .init           = &omap2_init_clksel_parent,
1590         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1591         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1592         .clksel         = omap24xx_gpt_clksel,
1593         .recalc         = &omap2_clksel_recalc,
1594 };
1595
1596 static struct clk gpt6_ick = {
1597         .name           = "gpt6_ick",
1598         .parent         = &l4_ck,
1599         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1600         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1601         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk gpt6_fck = {
1606         .name           = "gpt6_fck",
1607         .parent         = &func_32k_ck,
1608         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1611         .init           = &omap2_init_clksel_parent,
1612         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1613         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1614         .clksel         = omap24xx_gpt_clksel,
1615         .recalc         = &omap2_clksel_recalc,
1616 };
1617
1618 static struct clk gpt7_ick = {
1619         .name           = "gpt7_ick",
1620         .parent         = &l4_ck,
1621         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1622         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk gpt7_fck = {
1628         .name           = "gpt7_fck",
1629         .parent         = &func_32k_ck,
1630         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1632         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1633         .init           = &omap2_init_clksel_parent,
1634         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1635         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1636         .clksel         = omap24xx_gpt_clksel,
1637         .recalc         = &omap2_clksel_recalc,
1638 };
1639
1640 static struct clk gpt8_ick = {
1641         .name           = "gpt8_ick",
1642         .parent         = &l4_ck,
1643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1644         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1645         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 static struct clk gpt8_fck = {
1650         .name           = "gpt8_fck",
1651         .parent         = &func_32k_ck,
1652         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1654         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1655         .init           = &omap2_init_clksel_parent,
1656         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1657         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1658         .clksel         = omap24xx_gpt_clksel,
1659         .recalc         = &omap2_clksel_recalc,
1660 };
1661
1662 static struct clk gpt9_ick = {
1663         .name           = "gpt9_ick",
1664         .parent         = &l4_ck,
1665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1667         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk gpt9_fck = {
1672         .name           = "gpt9_fck",
1673         .parent         = &func_32k_ck,
1674         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1676         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1677         .init           = &omap2_init_clksel_parent,
1678         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1679         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1680         .clksel         = omap24xx_gpt_clksel,
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk gpt10_ick = {
1685         .name           = "gpt10_ick",
1686         .parent         = &l4_ck,
1687         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1688         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk gpt10_fck = {
1694         .name           = "gpt10_fck",
1695         .parent         = &func_32k_ck,
1696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1698         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1699         .init           = &omap2_init_clksel_parent,
1700         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1701         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1702         .clksel         = omap24xx_gpt_clksel,
1703         .recalc         = &omap2_clksel_recalc,
1704 };
1705
1706 static struct clk gpt11_ick = {
1707         .name           = "gpt11_ick",
1708         .parent         = &l4_ck,
1709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1710         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1711         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static struct clk gpt11_fck = {
1716         .name           = "gpt11_fck",
1717         .parent         = &func_32k_ck,
1718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1720         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1721         .init           = &omap2_init_clksel_parent,
1722         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1723         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1724         .clksel         = omap24xx_gpt_clksel,
1725         .recalc         = &omap2_clksel_recalc,
1726 };
1727
1728 static struct clk gpt12_ick = {
1729         .name           = "gpt12_ick",
1730         .parent         = &l4_ck,
1731         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1732         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1734         .recalc         = &followparent_recalc,
1735 };
1736
1737 static struct clk gpt12_fck = {
1738         .name           = "gpt12_fck",
1739         .parent         = &func_32k_ck,
1740         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1742         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1743         .init           = &omap2_init_clksel_parent,
1744         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1745         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1746         .clksel         = omap24xx_gpt_clksel,
1747         .recalc         = &omap2_clksel_recalc,
1748 };
1749
1750 static struct clk mcbsp1_ick = {
1751         .name           = "mcbsp1_ick",
1752         .parent         = &l4_ck,
1753         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1754         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 static struct clk mcbsp1_fck = {
1760         .name           = "mcbsp1_fck",
1761         .parent         = &func_96m_ck,
1762         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1763         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1764         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk mcbsp2_ick = {
1769         .name           = "mcbsp2_ick",
1770         .parent         = &l4_ck,
1771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1772         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1773         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1774         .recalc         = &followparent_recalc,
1775 };
1776
1777 static struct clk mcbsp2_fck = {
1778         .name           = "mcbsp2_fck",
1779         .parent         = &func_96m_ck,
1780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1781         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1782         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk mcbsp3_ick = {
1787         .name           = "mcbsp3_ick",
1788         .parent         = &l4_ck,
1789         .flags          = CLOCK_IN_OMAP243X,
1790         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1791         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk mcbsp3_fck = {
1796         .name           = "mcbsp3_fck",
1797         .parent         = &func_96m_ck,
1798         .flags          = CLOCK_IN_OMAP243X,
1799         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1800         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk mcbsp4_ick = {
1805         .name           = "mcbsp4_ick",
1806         .parent         = &l4_ck,
1807         .flags          = CLOCK_IN_OMAP243X,
1808         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1809         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1810         .recalc         = &followparent_recalc,
1811 };
1812
1813 static struct clk mcbsp4_fck = {
1814         .name           = "mcbsp4_fck",
1815         .parent         = &func_96m_ck,
1816         .flags          = CLOCK_IN_OMAP243X,
1817         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1818         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1819         .recalc         = &followparent_recalc,
1820 };
1821
1822 static struct clk mcbsp5_ick = {
1823         .name           = "mcbsp5_ick",
1824         .parent         = &l4_ck,
1825         .flags          = CLOCK_IN_OMAP243X,
1826         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1827         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1828         .recalc         = &followparent_recalc,
1829 };
1830
1831 static struct clk mcbsp5_fck = {
1832         .name           = "mcbsp5_fck",
1833         .parent         = &func_96m_ck,
1834         .flags          = CLOCK_IN_OMAP243X,
1835         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1836         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk mcspi1_ick = {
1841         .name           = "mcspi_ick",
1842         .id             = 1,
1843         .parent         = &l4_ck,
1844         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1845         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1846         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mcspi1_fck = {
1851         .name           = "mcspi_fck",
1852         .id             = 1,
1853         .parent         = &func_48m_ck,
1854         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1856         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1857         .recalc         = &followparent_recalc,
1858 };
1859
1860 static struct clk mcspi2_ick = {
1861         .name           = "mcspi_ick",
1862         .id             = 2,
1863         .parent         = &l4_ck,
1864         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mcspi2_fck = {
1871         .name           = "mcspi_fck",
1872         .id             = 2,
1873         .parent         = &func_48m_ck,
1874         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1876         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1877         .recalc         = &followparent_recalc,
1878 };
1879
1880 static struct clk mcspi3_ick = {
1881         .name           = "mcspi_ick",
1882         .id             = 3,
1883         .parent         = &l4_ck,
1884         .flags          = CLOCK_IN_OMAP243X,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1886         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1887         .recalc         = &followparent_recalc,
1888 };
1889
1890 static struct clk mcspi3_fck = {
1891         .name           = "mcspi_fck",
1892         .id             = 3,
1893         .parent         = &func_48m_ck,
1894         .flags          = CLOCK_IN_OMAP243X,
1895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1896         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk uart1_ick = {
1901         .name           = "uart1_ick",
1902         .parent         = &l4_ck,
1903         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1904         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1905         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1906         .recalc         = &followparent_recalc,
1907 };
1908
1909 static struct clk uart1_fck = {
1910         .name           = "uart1_fck",
1911         .parent         = &func_48m_ck,
1912         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1913         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1914         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk uart2_ick = {
1919         .name           = "uart2_ick",
1920         .parent         = &l4_ck,
1921         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1922         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1924         .recalc         = &followparent_recalc,
1925 };
1926
1927 static struct clk uart2_fck = {
1928         .name           = "uart2_fck",
1929         .parent         = &func_48m_ck,
1930         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1931         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1932         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk uart3_ick = {
1937         .name           = "uart3_ick",
1938         .parent         = &l4_ck,
1939         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1941         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk uart3_fck = {
1946         .name           = "uart3_fck",
1947         .parent         = &func_48m_ck,
1948         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1949         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1950         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1951         .recalc         = &followparent_recalc,
1952 };
1953
1954 static struct clk gpios_ick = {
1955         .name           = "gpios_ick",
1956         .parent         = &l4_ck,
1957         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1958         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1959         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1960         .recalc         = &followparent_recalc,
1961 };
1962
1963 static struct clk gpios_fck = {
1964         .name           = "gpios_fck",
1965         .parent         = &func_32k_ck,
1966         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1967         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1968         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1969         .recalc         = &followparent_recalc,
1970 };
1971
1972 static struct clk mpu_wdt_ick = {
1973         .name           = "mpu_wdt_ick",
1974         .parent         = &l4_ck,
1975         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1976         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1977         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1978         .recalc         = &followparent_recalc,
1979 };
1980
1981 static struct clk mpu_wdt_fck = {
1982         .name           = "mpu_wdt_fck",
1983         .parent         = &func_32k_ck,
1984         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1985         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1986         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1987         .recalc         = &followparent_recalc,
1988 };
1989
1990 static struct clk sync_32k_ick = {
1991         .name           = "sync_32k_ick",
1992         .parent         = &l4_ck,
1993         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1994         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1995         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1996         .recalc         = &followparent_recalc,
1997 };
1998 static struct clk wdt1_ick = {
1999         .name           = "wdt1_ick",
2000         .parent         = &l4_ck,
2001         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2002         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2003         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2004         .recalc         = &followparent_recalc,
2005 };
2006 static struct clk omapctrl_ick = {
2007         .name           = "omapctrl_ick",
2008         .parent         = &l4_ck,
2009         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2010         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2011         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2012         .recalc         = &followparent_recalc,
2013 };
2014 static struct clk icr_ick = {
2015         .name           = "icr_ick",
2016         .parent         = &l4_ck,
2017         .flags          = CLOCK_IN_OMAP243X,
2018         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2019         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk cam_ick = {
2024         .name           = "cam_ick",
2025         .parent         = &l4_ck,
2026         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2027         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2028         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk cam_fck = {
2033         .name           = "cam_fck",
2034         .parent         = &func_96m_ck,
2035         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2036         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2037         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk mailboxes_ick = {
2042         .name           = "mailboxes_ick",
2043         .parent         = &l4_ck,
2044         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2045         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2047         .recalc         = &followparent_recalc,
2048 };
2049
2050 static struct clk wdt4_ick = {
2051         .name           = "wdt4_ick",
2052         .parent         = &l4_ck,
2053         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2054         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2055         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 static struct clk wdt4_fck = {
2060         .name           = "wdt4_fck",
2061         .parent         = &func_32k_ck,
2062         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2063         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2064         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 static struct clk wdt3_ick = {
2069         .name           = "wdt3_ick",
2070         .parent         = &l4_ck,
2071         .flags          = CLOCK_IN_OMAP242X,
2072         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2074         .recalc         = &followparent_recalc,
2075 };
2076
2077 static struct clk wdt3_fck = {
2078         .name           = "wdt3_fck",
2079         .parent         = &func_32k_ck,
2080         .flags          = CLOCK_IN_OMAP242X,
2081         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2082         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2083         .recalc         = &followparent_recalc,
2084 };
2085
2086 static struct clk mspro_ick = {
2087         .name           = "mspro_ick",
2088         .parent         = &l4_ck,
2089         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2091         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 static struct clk mspro_fck = {
2096         .name           = "mspro_fck",
2097         .parent         = &func_96m_ck,
2098         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2100         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 static struct clk mmc_ick = {
2105         .name           = "mmc_ick",
2106         .parent         = &l4_ck,
2107         .flags          = CLOCK_IN_OMAP242X,
2108         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2109         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk mmc_fck = {
2114         .name           = "mmc_fck",
2115         .parent         = &func_96m_ck,
2116         .flags          = CLOCK_IN_OMAP242X,
2117         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2118         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk fac_ick = {
2123         .name           = "fac_ick",
2124         .parent         = &l4_ck,
2125         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2126         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2127         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk fac_fck = {
2132         .name           = "fac_fck",
2133         .parent         = &func_12m_ck,
2134         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2136         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk eac_ick = {
2141         .name           = "eac_ick",
2142         .parent         = &l4_ck,
2143         .flags          = CLOCK_IN_OMAP242X,
2144         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2145         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 static struct clk eac_fck = {
2150         .name           = "eac_fck",
2151         .parent         = &func_96m_ck,
2152         .flags          = CLOCK_IN_OMAP242X,
2153         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2154         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk hdq_ick = {
2159         .name           = "hdq_ick",
2160         .parent         = &l4_ck,
2161         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2162         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2163         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2164         .recalc         = &followparent_recalc,
2165 };
2166
2167 static struct clk hdq_fck = {
2168         .name           = "hdq_fck",
2169         .parent         = &func_12m_ck,
2170         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2171         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2172         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2173         .recalc         = &followparent_recalc,
2174 };
2175
2176 static struct clk i2c2_ick = {
2177         .name           = "i2c_ick",
2178         .id             = 2,
2179         .parent         = &l4_ck,
2180         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2181         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2182         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 static struct clk i2c2_fck = {
2187         .name           = "i2c_fck",
2188         .id             = 2,
2189         .parent         = &func_12m_ck,
2190         .flags          = CLOCK_IN_OMAP242X,
2191         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2192         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk i2chs2_fck = {
2197         .name           = "i2chs_fck",
2198         .id             = 2,
2199         .parent         = &func_96m_ck,
2200         .flags          = CLOCK_IN_OMAP243X,
2201         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2202         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2203         .recalc         = &followparent_recalc,
2204 };
2205
2206 static struct clk i2c1_ick = {
2207         .name           = "i2c_ick",
2208         .id             = 1,
2209         .parent         = &l4_ck,
2210         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2211         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2212         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2213         .recalc         = &followparent_recalc,
2214 };
2215
2216 static struct clk i2c1_fck = {
2217         .name           = "i2c_fck",
2218         .id             = 1,
2219         .parent         = &func_12m_ck,
2220         .flags          = CLOCK_IN_OMAP242X,
2221         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2222         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2223         .recalc         = &followparent_recalc,
2224 };
2225
2226 static struct clk i2chs1_fck = {
2227         .name           = "i2chs_fck",
2228         .id             = 1,
2229         .parent         = &func_96m_ck,
2230         .flags          = CLOCK_IN_OMAP243X,
2231         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2232         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 static struct clk gpmc_fck = {
2237         .name           = "gpmc_fck",
2238         .parent         = &core_l3_ck,
2239         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk sdma_fck = {
2244         .name           = "sdma_fck",
2245         .parent         = &core_l3_ck,
2246         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 static struct clk sdma_ick = {
2251         .name           = "sdma_ick",
2252         .parent         = &l4_ck,
2253         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2254         .recalc         = &followparent_recalc,
2255 };
2256
2257 static struct clk vlynq_ick = {
2258         .name           = "vlynq_ick",
2259         .parent         = &core_l3_ck,
2260         .flags          = CLOCK_IN_OMAP242X,
2261         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2262         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2263         .recalc         = &followparent_recalc,
2264 };
2265
2266 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2267         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2268         { .div = 0 }
2269 };
2270
2271 static const struct clksel_rate vlynq_fck_core_rates[] = {
2272         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2273         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2274         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2275         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2276         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2277         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2278         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2279         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2280         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2281         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2282         { .div = 0 }
2283 };
2284
2285 static const struct clksel vlynq_fck_clksel[] = {
2286         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2287         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2288         { .parent = NULL }
2289 };
2290
2291 static struct clk vlynq_fck = {
2292         .name           = "vlynq_fck",
2293         .parent         = &func_96m_ck,
2294         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2295         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2296         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2297         .init           = &omap2_init_clksel_parent,
2298         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2299         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2300         .clksel         = vlynq_fck_clksel,
2301         .recalc         = &omap2_clksel_recalc,
2302         .round_rate     = &omap2_clksel_round_rate,
2303         .set_rate       = &omap2_clksel_set_rate
2304 };
2305
2306 static struct clk sdrc_ick = {
2307         .name           = "sdrc_ick",
2308         .parent         = &l4_ck,
2309         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2310         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2311         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2312         .recalc         = &followparent_recalc,
2313 };
2314
2315 static struct clk des_ick = {
2316         .name           = "des_ick",
2317         .parent         = &l4_ck,
2318         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2319         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2320         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2321         .recalc         = &followparent_recalc,
2322 };
2323
2324 static struct clk sha_ick = {
2325         .name           = "sha_ick",
2326         .parent         = &l4_ck,
2327         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2328         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2329         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk rng_ick = {
2334         .name           = "rng_ick",
2335         .parent         = &l4_ck,
2336         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2337         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2338         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2339         .recalc         = &followparent_recalc,
2340 };
2341
2342 static struct clk aes_ick = {
2343         .name           = "aes_ick",
2344         .parent         = &l4_ck,
2345         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2346         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2347         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2348         .recalc         = &followparent_recalc,
2349 };
2350
2351 static struct clk pka_ick = {
2352         .name           = "pka_ick",
2353         .parent         = &l4_ck,
2354         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2355         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2356         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2357         .recalc         = &followparent_recalc,
2358 };
2359
2360 static struct clk usb_fck = {
2361         .name           = "usb_fck",
2362         .parent         = &func_48m_ck,
2363         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2364         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2365         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2366         .recalc         = &followparent_recalc,
2367 };
2368
2369 static struct clk usbhs_ick = {
2370         .name           = "usbhs_ick",
2371         .parent         = &core_l3_ck,
2372         .flags          = CLOCK_IN_OMAP243X,
2373         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2374         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2375         .recalc         = &followparent_recalc,
2376 };
2377
2378 static struct clk mmchs1_ick = {
2379         .name           = "mmchs_ick",
2380         .id             = 1,
2381         .parent         = &l4_ck,
2382         .flags          = CLOCK_IN_OMAP243X,
2383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2384         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk mmchs1_fck = {
2389         .name           = "mmchs_fck",
2390         .id             = 1,
2391         .parent         = &func_96m_ck,
2392         .flags          = CLOCK_IN_OMAP243X,
2393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2394         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk mmchs2_ick = {
2399         .name           = "mmchs_ick",
2400         .id             = 2,
2401         .parent         = &l4_ck,
2402         .flags          = CLOCK_IN_OMAP243X,
2403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2404         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk mmchs2_fck = {
2409         .name           = "mmchs_fck",
2410         .id             = 2,
2411         .parent         = &func_96m_ck,
2412         .flags          = CLOCK_IN_OMAP243X,
2413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2414         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk gpio5_ick = {
2419         .name           = "gpio5_ick",
2420         .parent         = &l4_ck,
2421         .flags          = CLOCK_IN_OMAP243X,
2422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2423         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk gpio5_fck = {
2428         .name           = "gpio5_fck",
2429         .parent         = &func_32k_ck,
2430         .flags          = CLOCK_IN_OMAP243X,
2431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2432         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk mdm_intc_ick = {
2437         .name           = "mdm_intc_ick",
2438         .parent         = &l4_ck,
2439         .flags          = CLOCK_IN_OMAP243X,
2440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2441         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445 static struct clk mmchsdb1_fck = {
2446         .name           = "mmchsdb_fck",
2447         .id             = 1,
2448         .parent         = &func_32k_ck,
2449         .flags          = CLOCK_IN_OMAP243X,
2450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2451         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2452         .recalc         = &followparent_recalc,
2453 };
2454
2455 static struct clk mmchsdb2_fck = {
2456         .name           = "mmchsdb_fck",
2457         .id             = 2,
2458         .parent         = &func_32k_ck,
2459         .flags          = CLOCK_IN_OMAP243X,
2460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2461         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2462         .recalc         = &followparent_recalc,
2463 };
2464
2465 /*
2466  * This clock is a composite clock which does entire set changes then
2467  * forces a rebalance. It keys on the MPU speed, but it really could
2468  * be any key speed part of a set in the rate table.
2469  *
2470  * to really change a set, you need memory table sets which get changed
2471  * in sram, pre-notifiers & post notifiers, changing the top set, without
2472  * having low level display recalc's won't work... this is why dpm notifiers
2473  * work, isr's off, walk a list of clocks already _off_ and not messing with
2474  * the bus.
2475  *
2476  * This clock should have no parent. It embodies the entire upper level
2477  * active set. A parent will mess up some of the init also.
2478  */
2479 static struct clk virt_prcm_set = {
2480         .name           = "virt_prcm_set",
2481         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2482                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2483         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2484         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2485         .set_rate       = &omap2_select_table_rate,
2486         .round_rate     = &omap2_round_to_table_rate,
2487 };
2488
2489 static struct clk *onchip_24xx_clks[] __initdata = {
2490         /* external root sources */
2491         &func_32k_ck,
2492         &osc_ck,
2493         &sys_ck,
2494         &alt_ck,
2495         /* internal analog sources */
2496         &dpll_ck,
2497         &apll96_ck,
2498         &apll54_ck,
2499         /* internal prcm root sources */
2500         &func_54m_ck,
2501         &core_ck,
2502         &func_96m_ck,
2503         &func_48m_ck,
2504         &func_12m_ck,
2505         &wdt1_osc_ck,
2506         &sys_clkout_src,
2507         &sys_clkout,
2508         &sys_clkout2_src,
2509         &sys_clkout2,
2510         &emul_ck,
2511         /* mpu domain clocks */
2512         &mpu_ck,
2513         /* dsp domain clocks */
2514         &dsp_fck,
2515         &dsp_irate_ick,
2516         &dsp_ick,               /* 242x */
2517         &iva2_1_ick,            /* 243x */
2518         &iva1_ifck,             /* 242x */
2519         &iva1_mpu_int_ifck,     /* 242x */
2520         /* GFX domain clocks */
2521         &gfx_3d_fck,
2522         &gfx_2d_fck,
2523         &gfx_ick,
2524         /* Modem domain clocks */
2525         &mdm_ick,
2526         &mdm_osc_ck,
2527         /* DSS domain clocks */
2528         &dss_ick,
2529         &dss1_fck,
2530         &dss2_fck,
2531         &dss_54m_fck,
2532         /* L3 domain clocks */
2533         &core_l3_ck,
2534         &ssi_ssr_sst_fck,
2535         &usb_l4_ick,
2536         /* L4 domain clocks */
2537         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2538         &ssi_l4_ick,
2539         /* virtual meta-group clock */
2540         &virt_prcm_set,
2541         /* general l4 interface ck, multi-parent functional clk */
2542         &gpt1_ick,
2543         &gpt1_fck,
2544         &gpt2_ick,
2545         &gpt2_fck,
2546         &gpt3_ick,
2547         &gpt3_fck,
2548         &gpt4_ick,
2549         &gpt4_fck,
2550         &gpt5_ick,
2551         &gpt5_fck,
2552         &gpt6_ick,
2553         &gpt6_fck,
2554         &gpt7_ick,
2555         &gpt7_fck,
2556         &gpt8_ick,
2557         &gpt8_fck,
2558         &gpt9_ick,
2559         &gpt9_fck,
2560         &gpt10_ick,
2561         &gpt10_fck,
2562         &gpt11_ick,
2563         &gpt11_fck,
2564         &gpt12_ick,
2565         &gpt12_fck,
2566         &mcbsp1_ick,
2567         &mcbsp1_fck,
2568         &mcbsp2_ick,
2569         &mcbsp2_fck,
2570         &mcbsp3_ick,
2571         &mcbsp3_fck,
2572         &mcbsp4_ick,
2573         &mcbsp4_fck,
2574         &mcbsp5_ick,
2575         &mcbsp5_fck,
2576         &mcspi1_ick,
2577         &mcspi1_fck,
2578         &mcspi2_ick,
2579         &mcspi2_fck,
2580         &mcspi3_ick,
2581         &mcspi3_fck,
2582         &uart1_ick,
2583         &uart1_fck,
2584         &uart2_ick,
2585         &uart2_fck,
2586         &uart3_ick,
2587         &uart3_fck,
2588         &gpios_ick,
2589         &gpios_fck,
2590         &mpu_wdt_ick,
2591         &mpu_wdt_fck,
2592         &sync_32k_ick,
2593         &wdt1_ick,
2594         &omapctrl_ick,
2595         &icr_ick,
2596         &cam_fck,
2597         &cam_ick,
2598         &mailboxes_ick,
2599         &wdt4_ick,
2600         &wdt4_fck,
2601         &wdt3_ick,
2602         &wdt3_fck,
2603         &mspro_ick,
2604         &mspro_fck,
2605         &mmc_ick,
2606         &mmc_fck,
2607         &fac_ick,
2608         &fac_fck,
2609         &eac_ick,
2610         &eac_fck,
2611         &hdq_ick,
2612         &hdq_fck,
2613         &i2c1_ick,
2614         &i2c1_fck,
2615         &i2chs1_fck,
2616         &i2c2_ick,
2617         &i2c2_fck,
2618         &i2chs2_fck,
2619         &gpmc_fck,
2620         &sdma_fck,
2621         &sdma_ick,
2622         &vlynq_ick,
2623         &vlynq_fck,
2624         &sdrc_ick,
2625         &des_ick,
2626         &sha_ick,
2627         &rng_ick,
2628         &aes_ick,
2629         &pka_ick,
2630         &usb_fck,
2631         &usbhs_ick,
2632         &mmchs1_ick,
2633         &mmchs1_fck,
2634         &mmchs2_ick,
2635         &mmchs2_fck,
2636         &gpio5_ick,
2637         &gpio5_fck,
2638         &mdm_intc_ick,
2639         &mmchsdb1_fck,
2640         &mmchsdb2_fck,
2641 };
2642
2643 #endif
2644