ARM: OMAP2: Change 24xx to use shared clock code and new reg access
[linux-2.6.git] / arch / arm / mach-omap2 / clock24xx.h
1 /*
2  *  linux/arch/arm/mach-omap24xx/clock.h
3  *
4  *  Copyright (C) 2005 Texas Instruments Inc.
5  *  Richard Woodruff <r-woodruff2@ti.com>
6  *  Created for OMAP2.
7  *
8  *  Copyright (C) 2004 Nokia corporation
9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16
17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
18 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
19
20 #include "clock.h"
21
22 #include "prm.h"
23 #include "cm.h"
24 #include "prm-regbits-24xx.h"
25 #include "cm-regbits-24xx.h"
26 #include "sdrc.h"
27
28 static void omap2_table_mpu_recalc(struct clk * clk);
29 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
30 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
31 static void omap2_sys_clk_recalc(struct clk * clk);
32 static void omap2_osc_clk_recalc(struct clk * clk);
33 static void omap2_sys_clk_recalc(struct clk * clk);
34 static void omap2_dpll_recalc(struct clk * clk);
35 static int omap2_clk_fixed_enable(struct clk * clk);
36 static void omap2_clk_fixed_disable(struct clk * clk);
37 static int omap2_enable_osc_ck(struct clk * clk);
38 static void omap2_disable_osc_ck(struct clk * clk);
39 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate);
40
41 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
42  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
43  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
44  */
45 struct prcm_config {
46         unsigned long xtal_speed;       /* crystal rate */
47         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
48         unsigned long mpu_speed;        /* speed of MPU */
49         unsigned long cm_clksel_mpu;    /* mpu divider */
50         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
51         unsigned long cm_clksel_gfx;    /* gfx dividers */
52         unsigned long cm_clksel1_core;  /* major subsystem dividers */
53         unsigned long cm_clksel1_pll;   /* m,n */
54         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
55         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
56         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
57         unsigned char flags;
58 };
59
60 /*
61  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
62  * These configurations are characterized by voltage and speed for clocks.
63  * The device is only validated for certain combinations. One way to express
64  * these combinations is via the 'ratio's' which the clocks operate with
65  * respect to each other. These ratio sets are for a given voltage/DPLL
66  * setting. All configurations can be described by a DPLL setting and a ratio
67  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
68  *
69  * 2430 differs from 2420 in that there are no more phase synchronizers used.
70  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
71  * 2430 (iva2.1, NOdsp, mdm)
72  */
73
74 /* Core fields for cm_clksel, not ratio governed */
75 #define RX_CLKSEL_DSS1                  (0x10 << 8)
76 #define RX_CLKSEL_DSS2                  (0x0 << 13)
77 #define RX_CLKSEL_SSI                   (0x5 << 20)
78
79 /*-------------------------------------------------------------------------
80  * Voltage/DPLL ratios
81  *-------------------------------------------------------------------------*/
82
83 /* 2430 Ratio's, 2430-Ratio Config 1 */
84 #define R1_CLKSEL_L3                    (4 << 0)
85 #define R1_CLKSEL_L4                    (2 << 5)
86 #define R1_CLKSEL_USB                   (4 << 25)
87 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
88                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
89                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
90 #define R1_CLKSEL_MPU                   (2 << 0)
91 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
92 #define R1_CLKSEL_DSP                   (2 << 0)
93 #define R1_CLKSEL_DSP_IF                (2 << 5)
94 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
95 #define R1_CLKSEL_GFX                   (2 << 0)
96 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
97 #define R1_CLKSEL_MDM                   (4 << 0)
98 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
99
100 /* 2430-Ratio Config 2 */
101 #define R2_CLKSEL_L3                    (6 << 0)
102 #define R2_CLKSEL_L4                    (2 << 5)
103 #define R2_CLKSEL_USB                   (2 << 25)
104 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
105                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
106                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
107 #define R2_CLKSEL_MPU                   (2 << 0)
108 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
109 #define R2_CLKSEL_DSP                   (2 << 0)
110 #define R2_CLKSEL_DSP_IF                (3 << 5)
111 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
112 #define R2_CLKSEL_GFX                   (2 << 0)
113 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
114 #define R2_CLKSEL_MDM                   (6 << 0)
115 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
116
117 /* 2430-Ratio Bootm (BYPASS) */
118 #define RB_CLKSEL_L3                    (1 << 0)
119 #define RB_CLKSEL_L4                    (1 << 5)
120 #define RB_CLKSEL_USB                   (1 << 25)
121 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
122                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
123                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
124 #define RB_CLKSEL_MPU                   (1 << 0)
125 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
126 #define RB_CLKSEL_DSP                   (1 << 0)
127 #define RB_CLKSEL_DSP_IF                (1 << 5)
128 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
129 #define RB_CLKSEL_GFX                   (1 << 0)
130 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
131 #define RB_CLKSEL_MDM                   (1 << 0)
132 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
133
134 /* 2420 Ratio Equivalents */
135 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
136 #define RXX_CLKSEL_SSI                  (0x8 << 20)
137
138 /* 2420-PRCM III 532MHz core */
139 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
140 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
141 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
142 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
143                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
144                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
145                                         RIII_CLKSEL_L3
146 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
147 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
148 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
149 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
150 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
151 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
152 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
153 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
154                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
155                                         RIII_CLKSEL_DSP
156 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
157 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
158
159 /* 2420-PRCM II 600MHz core */
160 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
161 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
162 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
163 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
164                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
165                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
166                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
167 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
168 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
169 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
170 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
171 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
172 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
173 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
174 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
175                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
176                                         RII_CLKSEL_DSP
177 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
178 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
179
180 /* 2420-PRCM I 660MHz core */
181 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
182 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
183 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
184 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
185                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
186                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
187                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
188 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
189 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
190 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
191 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
192 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
193 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
194 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
195 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
196                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
197                                         RI_CLKSEL_DSP
198 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
199 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
200
201 /* 2420-PRCM VII (boot) */
202 #define RVII_CLKSEL_L3                  (1 << 0)
203 #define RVII_CLKSEL_L4                  (1 << 5)
204 #define RVII_CLKSEL_DSS1                (1 << 8)
205 #define RVII_CLKSEL_DSS2                (0 << 13)
206 #define RVII_CLKSEL_VLYNQ               (1 << 15)
207 #define RVII_CLKSEL_SSI                 (1 << 20)
208 #define RVII_CLKSEL_USB                 (1 << 25)
209
210 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
211                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
212                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
213
214 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
215 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
216
217 #define RVII_CLKSEL_DSP                 (1 << 0)
218 #define RVII_CLKSEL_DSP_IF              (1 << 5)
219 #define RVII_SYNC_DSP                   (0 << 7)
220 #define RVII_CLKSEL_IVA                 (1 << 8)
221 #define RVII_SYNC_IVA                   (0 << 13)
222 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
223                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
224
225 #define RVII_CLKSEL_GFX                 (1 << 0)
226 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
227
228 /*-------------------------------------------------------------------------
229  * 2430 Target modes: Along with each configuration the CPU has several
230  * modes which goes along with them. Modes mainly are the addition of
231  * describe DPLL combinations to go along with a ratio.
232  *-------------------------------------------------------------------------*/
233
234 /* Hardware governed */
235 #define MX_48M_SRC                      (0 << 3)
236 #define MX_54M_SRC                      (0 << 5)
237 #define MX_APLLS_CLIKIN_12              (3 << 23)
238 #define MX_APLLS_CLIKIN_13              (2 << 23)
239 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
240
241 /*
242  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
243  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
244  */
245 #define M5A_DPLL_MULT_12                (133 << 12)
246 #define M5A_DPLL_DIV_12                 (5 << 8)
247 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
248                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
249                                         MX_APLLS_CLIKIN_12
250 #define M5A_DPLL_MULT_13                (61 << 12)
251 #define M5A_DPLL_DIV_13                 (2 << 8)
252 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
253                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
254                                         MX_APLLS_CLIKIN_13
255 #define M5A_DPLL_MULT_19                (55 << 12)
256 #define M5A_DPLL_DIV_19                 (3 << 8)
257 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
258                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
259                                         MX_APLLS_CLIKIN_19_2
260 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
261 #define M5B_DPLL_MULT_12                (50 << 12)
262 #define M5B_DPLL_DIV_12                 (2 << 8)
263 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
264                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
265                                         MX_APLLS_CLIKIN_12
266 #define M5B_DPLL_MULT_13                (200 << 12)
267 #define M5B_DPLL_DIV_13                 (12 << 8)
268
269 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
270                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
271                                         MX_APLLS_CLIKIN_13
272 #define M5B_DPLL_MULT_19                (125 << 12)
273 #define M5B_DPLL_DIV_19                 (31 << 8)
274 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
275                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
276                                         MX_APLLS_CLIKIN_19_2
277 /*
278  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
279  */
280 #define M4_DPLL_MULT_12                 (133 << 12)
281 #define M4_DPLL_DIV_12                  (3 << 8)
282 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
283                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
284                                         MX_APLLS_CLIKIN_12
285
286 #define M4_DPLL_MULT_13                 (399 << 12)
287 #define M4_DPLL_DIV_13                  (12 << 8)
288 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
289                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
290                                         MX_APLLS_CLIKIN_13
291
292 #define M4_DPLL_MULT_19                 (145 << 12)
293 #define M4_DPLL_DIV_19                  (6 << 8)
294 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
295                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
296                                         MX_APLLS_CLIKIN_19_2
297
298 /*
299  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
300  */
301 #define M3_DPLL_MULT_12                 (55 << 12)
302 #define M3_DPLL_DIV_12                  (1 << 8)
303 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
304                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
305                                         MX_APLLS_CLIKIN_12
306 #define M3_DPLL_MULT_13                 (76 << 12)
307 #define M3_DPLL_DIV_13                  (2 << 8)
308 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
309                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
310                                         MX_APLLS_CLIKIN_13
311 #define M3_DPLL_MULT_19                 (17 << 12)
312 #define M3_DPLL_DIV_19                  (0 << 8)
313 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
314                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
315                                         MX_APLLS_CLIKIN_19_2
316
317 /*
318  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
319  */
320 #define M2_DPLL_MULT_12                 (55 << 12)
321 #define M2_DPLL_DIV_12                  (1 << 8)
322 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
323                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
324                                         MX_APLLS_CLIKIN_12
325
326 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
327  * relock time issue */
328 /* Core frequency changed from 330/165 to 329/164 MHz*/
329 #define M2_DPLL_MULT_13                 (76 << 12)
330 #define M2_DPLL_DIV_13                  (2 << 8)
331 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
332                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
333                                         MX_APLLS_CLIKIN_13
334
335 #define M2_DPLL_MULT_19                 (17 << 12)
336 #define M2_DPLL_DIV_19                  (0 << 8)
337 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
338                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
339                                         MX_APLLS_CLIKIN_19_2
340
341 /* boot (boot) */
342 #define MB_DPLL_MULT                    (1 << 12)
343 #define MB_DPLL_DIV                     (0 << 8)
344 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
345                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
346
347 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
348                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
349
350 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
351                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
352
353 /*
354  * 2430 - chassis (sedna)
355  * 165 (ratio1) same as above #2
356  * 150 (ratio1)
357  * 133 (ratio2) same as above #4
358  * 110 (ratio2) same as above #3
359  * 104 (ratio2)
360  * boot (boot)
361  */
362
363 /* PRCM I target DPLL = 2*330MHz = 660MHz */
364 #define MI_DPLL_MULT_12                 (55 << 12)
365 #define MI_DPLL_DIV_12                  (1 << 8)
366 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
367                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
368                                         MX_APLLS_CLIKIN_12
369
370 /*
371  * 2420 Equivalent - mode registers
372  * PRCM II , target DPLL = 2*300MHz = 600MHz
373  */
374 #define MII_DPLL_MULT_12                (50 << 12)
375 #define MII_DPLL_DIV_12                 (1 << 8)
376 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
377                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
378                                         MX_APLLS_CLIKIN_12
379 #define MII_DPLL_MULT_13                (300 << 12)
380 #define MII_DPLL_DIV_13                 (12 << 8)
381 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
382                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
383                                         MX_APLLS_CLIKIN_13
384
385 /* PRCM III target DPLL = 2*266 = 532MHz*/
386 #define MIII_DPLL_MULT_12               (133 << 12)
387 #define MIII_DPLL_DIV_12                (5 << 8)
388 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
389                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
390                                         MX_APLLS_CLIKIN_12
391 #define MIII_DPLL_MULT_13               (266 << 12)
392 #define MIII_DPLL_DIV_13                (12 << 8)
393 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
394                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
395                                         MX_APLLS_CLIKIN_13
396
397 /* PRCM VII (boot bypass) */
398 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
399 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
400
401 /* High and low operation value */
402 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
403 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
404
405 /* MPU speed defines */
406 #define S12M    12000000
407 #define S13M    13000000
408 #define S19M    19200000
409 #define S26M    26000000
410 #define S100M   100000000
411 #define S133M   133000000
412 #define S150M   150000000
413 #define S164M   164000000
414 #define S165M   165000000
415 #define S199M   199000000
416 #define S200M   200000000
417 #define S266M   266000000
418 #define S300M   300000000
419 #define S329M   329000000
420 #define S330M   330000000
421 #define S399M   399000000
422 #define S400M   400000000
423 #define S532M   532000000
424 #define S600M   600000000
425 #define S658M   658000000
426 #define S660M   660000000
427 #define S798M   798000000
428
429 /*-------------------------------------------------------------------------
430  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
431  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
432  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
433  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
434  *
435  * Filling in table based on H4 boards and 2430-SDPs variants available.
436  * There are quite a few more rates combinations which could be defined.
437  *
438  * When multiple values are defined the start up will try and choose the
439  * fastest one. If a 'fast' value is defined, then automatically, the /2
440  * one should be included as it can be used.    Generally having more that
441  * one fast set does not make sense, as static timings need to be changed
442  * to change the set.    The exception is the bypass setting which is
443  * availble for low power bypass.
444  *
445  * Note: This table needs to be sorted, fastest to slowest.
446  *-------------------------------------------------------------------------*/
447 static struct prcm_config rate_table[] = {
448         /* PRCM I - FAST */
449         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
450                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
451                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
452                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
453                 RATE_IN_242X},
454
455         /* PRCM II - FAST */
456         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
457                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
458                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
459                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
460                 RATE_IN_242X},
461
462         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
463                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
464                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
465                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
466                 RATE_IN_242X},
467
468         /* PRCM III - FAST */
469         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
470                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
471                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
472                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
473                 RATE_IN_242X},
474
475         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
476                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
477                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
478                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
479                 RATE_IN_242X},
480
481         /* PRCM II - SLOW */
482         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
483                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
484                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
485                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
486                 RATE_IN_242X},
487
488         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
489                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
490                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
491                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
492                 RATE_IN_242X},
493
494         /* PRCM III - SLOW */
495         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
496                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
497                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
498                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
499                 RATE_IN_242X},
500
501         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
502                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
503                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
504                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
505                 RATE_IN_242X},
506
507         /* PRCM-VII (boot-bypass) */
508         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
509                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
510                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
511                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
512                 RATE_IN_242X},
513
514         /* PRCM-VII (boot-bypass) */
515         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
516                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
517                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
518                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
519                 RATE_IN_242X},
520
521         /* PRCM #4 - ratio2 (ES2.1) - FAST */
522         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
523                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
524                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
525                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
526                 SDRC_RFR_CTRL_133MHz,
527                 RATE_IN_243X},
528
529         /* PRCM #2 - ratio1 (ES2) - FAST */
530         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
531                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
532                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
533                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
534                 SDRC_RFR_CTRL_165MHz,
535                 RATE_IN_243X},
536
537         /* PRCM #5a - ratio1 - FAST */
538         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
539                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
540                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
541                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
542                 SDRC_RFR_CTRL_133MHz,
543                 RATE_IN_243X},
544
545         /* PRCM #5b - ratio1 - FAST */
546         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
547                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
548                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
549                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
550                 SDRC_RFR_CTRL_100MHz,
551                 RATE_IN_243X},
552
553         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
554         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
555                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
556                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
557                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
558                 SDRC_RFR_CTRL_133MHz,
559                 RATE_IN_243X},
560
561         /* PRCM #2 - ratio1 (ES2) - SLOW */
562         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
563                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
564                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
565                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
566                 SDRC_RFR_CTRL_165MHz,
567                 RATE_IN_243X},
568
569         /* PRCM #5a - ratio1 - SLOW */
570         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
571                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
572                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
573                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
574                 SDRC_RFR_CTRL_133MHz,
575                 RATE_IN_243X},
576
577         /* PRCM #5b - ratio1 - SLOW*/
578         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
579                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
580                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
581                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
582                 SDRC_RFR_CTRL_100MHz,
583                 RATE_IN_243X},
584
585         /* PRCM-boot/bypass */
586         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
587                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
588                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
589                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
590                 SDRC_RFR_CTRL_BYPASS,
591                 RATE_IN_243X},
592
593         /* PRCM-boot/bypass */
594         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
595                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
596                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
597                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
598                 SDRC_RFR_CTRL_BYPASS,
599                 RATE_IN_243X},
600
601         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
602 };
603
604 /*-------------------------------------------------------------------------
605  * 24xx clock tree.
606  *
607  * NOTE:In many cases here we are assigning a 'default' parent. In many
608  *      cases the parent is selectable. The get/set parent calls will also
609  *      switch sources.
610  *
611  *      Many some clocks say always_enabled, but they can be auto idled for
612  *      power savings. They will always be available upon clock request.
613  *
614  *      Several sources are given initial rates which may be wrong, this will
615  *      be fixed up in the init func.
616  *
617  *      Things are broadly separated below by clock domains. It is
618  *      noteworthy that most periferals have dependencies on multiple clock
619  *      domains. Many get their interface clocks from the L4 domain, but get
620  *      functional clocks from fixed sources or other core domain derived
621  *      clocks.
622  *-------------------------------------------------------------------------*/
623
624 #ifdef OLD_CK
625 /* Base external input clocks */
626 static struct clk func_32k_ck = {
627         .name           = "func_32k_ck",
628         .rate           = 32000,
629         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
630                                 RATE_FIXED | ALWAYS_ENABLED,
631 };
632 #endif  /* OLD_CK */
633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
635         .name           = "osc_ck",
636         .rate           = 26000000,             /* fixed up in clock init */
637         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
638                                 RATE_FIXED | RATE_PROPAGATES,
639 };
640
641 /* With out modem likely 12MHz, with modem likely 13MHz */
642 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
643         .name           = "sys_ck",             /* ~ ref_clk also */
644         .parent         = &osc_ck,
645         .rate           = 13000000,
646         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
647                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
648         .recalc         = &omap2_sys_clk_recalc,
649 };
650 #ifdef OLD_CK
651 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
652         .name           = "alt_ck",
653         .rate           = 54000000,
654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
655                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
656         .recalc         = &omap2_propagate_rate,
657 };
658 #endif  /* OLD_CK */
659 /*
660  * Analog domain root source clocks
661  */
662
663 /* dpll_ck, is broken out in to special cases through clksel */
664 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
665  * deal with this
666  */
667
668 static const struct dpll_data dpll_dd = {
669         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
670         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
671         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
672 };
673
674 static struct clk dpll_ck = {
675         .name           = "dpll_ck",
676         .parent         = &sys_ck,              /* Can be func_32k also */
677         .dpll_data      = &dpll_dd,
678         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679                                 RATE_PROPAGATES | ALWAYS_ENABLED,
680         .recalc         = &omap2_dpll_recalc,
681         .set_rate       = &omap2_reprogram_dpll,
682 };
683
684 static struct clk apll96_ck = {
685         .name           = "apll96_ck",
686         .parent         = &sys_ck,
687         .rate           = 96000000,
688         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
689                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
690         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
691         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
692         .enable         = &omap2_clk_fixed_enable,
693         .disable        = &omap2_clk_fixed_disable,
694         .recalc         = &propagate_rate,
695 };
696
697 static struct clk apll54_ck = {
698         .name           = "apll54_ck",
699         .parent         = &sys_ck,
700         .rate           = 54000000,
701         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
702                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
703         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
705         .enable         = &omap2_clk_fixed_enable,
706         .disable        = &omap2_clk_fixed_disable,
707         .recalc         = &propagate_rate,
708 };
709
710 /*
711  * PRCM digital base sources
712  */
713 #ifdef OLD_CK
714 static struct clk func_54m_ck = {
715         .name           = "func_54m_ck",
716         .parent         = &apll54_ck,   /* can also be alt_clk */
717         .rate           = 54000000,
718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
719                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
720         .src_offset     = 5,
721         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
722         .enable_bit     = 0xff,
723         .recalc         = &omap2_propagate_rate,
724 };
725 #endif  /* OLD_CK */
726 static struct clk core_ck = {
727         .name           = "core_ck",
728         .parent         = &dpll_ck,             /* can also be 32k */
729         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
730                                 ALWAYS_ENABLED | RATE_PROPAGATES,
731         .recalc         = &followparent_recalc,
732 };
733 #ifdef OLD_CK
734 static struct clk sleep_ck = {          /* sys_clk or 32k */
735         .name           = "sleep_ck",
736         .parent         = &func_32k_ck,
737         .rate           = 32000,
738         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
739         .recalc         = &omap2_propagate_rate,
740 };
741
742 static struct clk func_96m_ck = {
743         .name           = "func_96m_ck",
744         .parent         = &apll96_ck,
745         .rate           = 96000000,
746         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
747                                 RATE_FIXED | RATE_PROPAGATES,
748         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
749         .enable_bit     = 0xff,
750         .recalc         = &omap2_propagate_rate,
751 };
752
753 static struct clk func_48m_ck = {
754         .name           = "func_48m_ck",
755         .parent         = &apll96_ck,    /* 96M or Alt */
756         .rate           = 48000000,
757         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
758                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
759         .src_offset     = 3,
760         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
761         .enable_bit     = 0xff,
762         .recalc         = &omap2_propagate_rate,
763 };
764
765 static struct clk func_12m_ck = {
766         .name           = "func_12m_ck",
767         .parent         = &func_48m_ck,
768         .rate           = 12000000,
769         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
770                                 RATE_FIXED | RATE_PROPAGATES,
771         .recalc         = &omap2_propagate_rate,
772         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
773         .enable_bit     = 0xff,
774 };
775
776 /* Secure timer, only available in secure mode */
777 static struct clk wdt1_osc_ck = {
778         .name           = "ck_wdt1_osc",
779         .parent         = &osc_ck,
780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
781         .recalc         = &omap2_followparent_recalc,
782 };
783
784 static struct clk sys_clkout = {
785         .name           = "sys_clkout",
786         .parent         = &func_54m_ck,
787         .rate           = 54000000,
788         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
789                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
790         .src_offset     = 0,
791         .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
792         .enable_bit     = 7,
793         .rate_offset    = 3,
794         .recalc         = &omap2_clksel_recalc,
795 };
796
797 /* In 2430, new in 2420 ES2 */
798 static struct clk sys_clkout2 = {
799         .name           = "sys_clkout2",
800         .parent         = &func_54m_ck,
801         .rate           = 54000000,
802         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
803                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
804         .src_offset     = 8,
805         .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
806         .enable_bit     = 15,
807         .rate_offset    = 11,
808         .recalc         = &omap2_clksel_recalc,
809 };
810
811 static struct clk emul_ck = {
812         .name           = "emul_ck",
813         .parent         = &func_54m_ck,
814         .flags          = CLOCK_IN_OMAP242X,
815         .enable_reg     = (void __iomem *)&PRCM_CLKEMUL_CTRL,
816         .enable_bit     = 0,
817         .recalc         = &omap2_propagate_rate,
818
819 };
820 #endif  /* OLD_CK */
821 /*
822  * MPU clock domain
823  *      Clocks:
824  *              MPU_FCLK, MPU_ICLK
825  *              INT_M_FCLK, INT_M_I_CLK
826  *
827  * - Individual clocks are hardware managed.
828  * - Base divider comes from: CM_CLKSEL_MPU
829  *
830  */
831 static struct clk mpu_ck = {    /* Control cpu */
832         .name           = "mpu_ck",
833         .parent         = &core_ck,
834         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
835                                 ALWAYS_ENABLED | DELAYED_APP |
836                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
837         .init           = &omap2_init_clksel_parent,
838         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
839         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
840         .recalc         = &omap2_clksel_recalc,
841         .round_rate     = &omap2_clksel_round_rate,
842         .set_rate       = &omap2_clksel_set_rate
843 };
844 #ifdef OLD_CK
845 /*
846  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
847  * Clocks:
848  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
849  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
850  */
851 static struct clk iva2_1_fck = {
852         .name           = "iva2_1_fck",
853         .parent         = &core_ck,
854         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
855                                 DELAYED_APP | RATE_PROPAGATES |
856                                 CONFIG_PARTICIPANT,
857         .rate_offset    = 0,
858         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
859         .enable_bit     = 0,
860         .recalc         = &omap2_clksel_recalc,
861 };
862
863 static struct clk iva2_1_ick = {
864         .name           = "iva2_1_ick",
865         .parent         = &iva2_1_fck,
866         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
867                                 DELAYED_APP | CONFIG_PARTICIPANT,
868         .rate_offset    = 5,
869         .recalc         = &omap2_clksel_recalc,
870 };
871
872 /*
873  * Won't be too specific here. The core clock comes into this block
874  * it is divided then tee'ed. One branch goes directly to xyz enable
875  * controls. The other branch gets further divided by 2 then possibly
876  * routed into a synchronizer and out of clocks abc.
877  */
878 static struct clk dsp_fck = {
879         .name           = "dsp_fck",
880         .parent         = &core_ck,
881         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
882                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
883         .rate_offset    = 0,
884         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
885         .enable_bit     = 0,
886         .recalc         = &omap2_clksel_recalc,
887 };
888
889 static struct clk dsp_ick = {
890         .name           = "dsp_ick",     /* apparently ipi and isp */
891         .parent         = &dsp_fck,
892         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
893                                 DELAYED_APP | CONFIG_PARTICIPANT,
894         .rate_offset = 5,
895         .enable_reg     = (void __iomem *)&CM_ICLKEN_DSP,
896         .enable_bit     = 1,            /* for ipi */
897         .recalc         = &omap2_clksel_recalc,
898 };
899
900 static struct clk iva1_ifck = {
901         .name           = "iva1_ifck",
902         .parent         = &core_ck,
903         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
904                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
905         .rate_offset= 8,
906         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
907         .enable_bit     = 10,
908         .recalc         = &omap2_clksel_recalc,
909 };
910
911 /* IVA1 mpu/int/i/f clocks are /2 of parent */
912 static struct clk iva1_mpu_int_ifck = {
913         .name           = "iva1_mpu_int_ifck",
914         .parent         = &iva1_ifck,
915         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
916         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
917         .enable_bit     = 8,
918         .recalc         = &omap2_clksel_recalc,
919 };
920
921 /*
922  * L3 clock domain
923  * L3 clocks are used for both interface and functional clocks to
924  * multiple entities. Some of these clocks are completely managed
925  * by hardware, and some others allow software control. Hardware
926  * managed ones general are based on directly CLK_REQ signals and
927  * various auto idle settings. The functional spec sets many of these
928  * as 'tie-high' for their enables.
929  *
930  * I-CLOCKS:
931  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
932  *      CAM, HS-USB.
933  * F-CLOCK
934  *      SSI.
935  *
936  * GPMC memories and SDRC have timing and clock sensitive registers which
937  * may very well need notification when the clock changes. Currently for low
938  * operating points, these are taken care of in sleep.S.
939  */
940 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
941         .name           = "core_l3_ck",
942         .parent         = &core_ck,
943         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
944                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
945                                 DELAYED_APP | CONFIG_PARTICIPANT |
946                                 RATE_PROPAGATES,
947         .rate_offset    = 0,
948         .recalc         = &omap2_clksel_recalc,
949 };
950
951 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
952         .name           = "usb_l4_ick",
953         .parent         = &core_l3_ck,
954         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
955                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
956                                 CONFIG_PARTICIPANT,
957         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
958         .enable_bit     = 0,
959         .rate_offset = 25,
960         .recalc         = &omap2_clksel_recalc,
961 };
962
963 /*
964  * SSI is in L3 management domain, its direct parent is core not l3,
965  * many core power domain entities are grouped into the L3 clock
966  * domain.
967  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
968  *
969  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
970  */
971 static struct clk ssi_ssr_sst_fck = {
972         .name           = "ssi_fck",
973         .parent         = &core_ck,
974         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
975                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
976         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,     /* bit 1 */
977         .enable_bit     = 1,
978         .rate_offset = 20,
979         .recalc         = &omap2_clksel_recalc,
980 };
981
982 /*
983  * GFX clock domain
984  *      Clocks:
985  * GFX_FCLK, GFX_ICLK
986  * GFX_CG1(2d), GFX_CG2(3d)
987  *
988  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
989  * The 2d and 3d clocks run at a hardware determined
990  * divided value of fclk.
991  *
992  */
993 static struct clk gfx_3d_fck = {
994         .name           = "gfx_3d_fck",
995         .parent         = &core_l3_ck,
996         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
997                                 RATE_CKCTL | CM_GFX_SEL1,
998         .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
999         .enable_bit     = 2,
1000         .rate_offset= 0,
1001         .recalc         = &omap2_clksel_recalc,
1002 };
1003
1004 static struct clk gfx_2d_fck = {
1005         .name           = "gfx_2d_fck",
1006         .parent         = &core_l3_ck,
1007         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1008                                 RATE_CKCTL | CM_GFX_SEL1,
1009         .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
1010         .enable_bit     = 1,
1011         .rate_offset= 0,
1012         .recalc         = &omap2_clksel_recalc,
1013 };
1014
1015 static struct clk gfx_ick = {
1016         .name           = "gfx_ick",            /* From l3 */
1017         .parent         = &core_l3_ck,
1018         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1019                                 RATE_CKCTL,
1020         .enable_reg     = (void __iomem *)&CM_ICLKEN_GFX,       /* bit 0 */
1021         .enable_bit     = 0,
1022         .recalc         = &omap2_followparent_recalc,
1023 };
1024
1025 /*
1026  * Modem clock domain (2430)
1027  *      CLOCKS:
1028  *              MDM_OSC_CLK
1029  *              MDM_ICLK
1030  */
1031 static struct clk mdm_ick = {           /* used both as a ick and fck */
1032         .name           = "mdm_ick",
1033         .parent         = &core_ck,
1034         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
1035                                 DELAYED_APP | CONFIG_PARTICIPANT,
1036         .rate_offset    = 0,
1037         .enable_reg     = (void __iomem *)&CM_ICLKEN_MDM,
1038         .enable_bit     = 0,
1039         .recalc         = &omap2_clksel_recalc,
1040 };
1041
1042 static struct clk mdm_osc_ck = {
1043         .name           = "mdm_osc_ck",
1044         .rate           = 26000000,
1045         .parent         = &osc_ck,
1046         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
1047         .enable_reg     = (void __iomem *)&CM_FCLKEN_MDM,
1048         .enable_bit     = 1,
1049         .recalc         = &omap2_followparent_recalc,
1050 };
1051
1052 /*
1053  * L4 clock management domain
1054  *
1055  * This domain contains lots of interface clocks from the L4 interface, some
1056  * functional clocks.   Fixed APLL functional source clocks are managed in
1057  * this domain.
1058  */
1059 static struct clk l4_ck = {             /* used both as an ick and fck */
1060         .name           = "l4_ck",
1061         .parent         = &core_l3_ck,
1062         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1063                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1064                                 DELAYED_APP | RATE_PROPAGATES,
1065         .rate_offset    = 5,
1066         .recalc         = &omap2_clksel_recalc,
1067 };
1068
1069 static struct clk ssi_l4_ick = {
1070         .name           = "ssi_l4_ick",
1071         .parent         = &l4_ck,
1072         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1073         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,     /* bit 1 */
1074         .enable_bit     = 1,
1075         .recalc         = &omap2_followparent_recalc,
1076 };
1077
1078 /*
1079  * DSS clock domain
1080  * CLOCKs:
1081  * DSS_L4_ICLK, DSS_L3_ICLK,
1082  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1083  *
1084  * DSS is both initiator and target.
1085  */
1086 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1087         .name           = "dss_ick",
1088         .parent         = &l4_ck,       /* really both l3 and l4 */
1089         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1090         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1091         .enable_bit     = 0,
1092         .recalc         = &omap2_followparent_recalc,
1093 };
1094
1095 static struct clk dss1_fck = {
1096         .name           = "dss1_fck",
1097         .parent         = &core_ck,             /* Core or sys */
1098         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1099                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1100         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1101         .enable_bit     = 0,
1102         .rate_offset    = 8,
1103         .src_offset     = 8,
1104         .recalc         = &omap2_clksel_recalc,
1105 };
1106
1107 static struct clk dss2_fck = {          /* Alt clk used in power management */
1108         .name           = "dss2_fck",
1109         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1110         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1111                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1112                                 DELAYED_APP,
1113         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1114         .enable_bit     = 1,
1115         .src_offset     = 13,
1116         .recalc         = &omap2_followparent_recalc,
1117 };
1118
1119 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1120         .name           = "dss_54m_fck",        /* 54m tv clk */
1121         .parent         = &func_54m_ck,
1122         .rate           = 54000000,
1123         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1124                                 RATE_FIXED | RATE_PROPAGATES,
1125         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1126         .enable_bit     = 2,
1127         .recalc         = &omap2_propagate_rate,
1128 };
1129
1130 /*
1131  * CORE power domain ICLK & FCLK defines.
1132  * Many of the these can have more than one possible parent. Entries
1133  * here will likely have an L4 interface parent, and may have multiple
1134  * functional clock parents.
1135  */
1136 static struct clk gpt1_ick = {
1137         .name           = "gpt1_ick",
1138         .parent         = &l4_ck,
1139         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1140         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,      /* Bit0 */
1141         .enable_bit     = 0,
1142         .recalc         = &omap2_followparent_recalc,
1143 };
1144
1145 static struct clk gpt1_fck = {
1146         .name           = "gpt1_fck",
1147         .parent         = &func_32k_ck,
1148         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1149                                 CM_WKUP_SEL1,
1150         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,      /* Bit0 */
1151         .enable_bit     = 0,
1152         .src_offset     = 0,
1153         .recalc         = &omap2_followparent_recalc,
1154 };
1155
1156 static struct clk gpt2_ick = {
1157         .name           = "gpt2_ick",
1158         .parent         = &l4_ck,
1159         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1160         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit4 */
1161         .enable_bit     = 4,
1162         .recalc         = &omap2_followparent_recalc,
1163 };
1164
1165 static struct clk gpt2_fck = {
1166         .name           = "gpt2_fck",
1167         .parent         = &func_32k_ck,
1168         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1169                                 CM_CORE_SEL2,
1170         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1171         .enable_bit     = 4,
1172         .src_offset     = 2,
1173         .recalc         = &omap2_followparent_recalc,
1174 };
1175
1176 static struct clk gpt3_ick = {
1177         .name           = "gpt3_ick",
1178         .parent         = &l4_ck,
1179         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1180         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit5 */
1181         .enable_bit     = 5,
1182         .recalc         = &omap2_followparent_recalc,
1183 };
1184
1185 static struct clk gpt3_fck = {
1186         .name           = "gpt3_fck",
1187         .parent         = &func_32k_ck,
1188         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1189                                 CM_CORE_SEL2,
1190         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1191         .enable_bit     = 5,
1192         .src_offset     = 4,
1193         .recalc         = &omap2_followparent_recalc,
1194 };
1195
1196 static struct clk gpt4_ick = {
1197         .name           = "gpt4_ick",
1198         .parent         = &l4_ck,
1199         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1200         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit6 */
1201         .enable_bit     = 6,
1202         .recalc         = &omap2_followparent_recalc,
1203 };
1204
1205 static struct clk gpt4_fck = {
1206         .name           = "gpt4_fck",
1207         .parent         = &func_32k_ck,
1208         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1209                                 CM_CORE_SEL2,
1210         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1211         .enable_bit     = 6,
1212         .src_offset     = 6,
1213         .recalc         = &omap2_followparent_recalc,
1214 };
1215
1216 static struct clk gpt5_ick = {
1217         .name           = "gpt5_ick",
1218         .parent         = &l4_ck,
1219         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1220         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* Bit7 */
1221         .enable_bit     = 7,
1222         .recalc         = &omap2_followparent_recalc,
1223 };
1224
1225 static struct clk gpt5_fck = {
1226         .name           = "gpt5_fck",
1227         .parent         = &func_32k_ck,
1228         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1229                                 CM_CORE_SEL2,
1230         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1231         .enable_bit     = 7,
1232         .src_offset     = 8,
1233         .recalc         = &omap2_followparent_recalc,
1234 };
1235
1236 static struct clk gpt6_ick = {
1237         .name           = "gpt6_ick",
1238         .parent         = &l4_ck,
1239         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1240         .enable_bit     = 8,
1241         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit8 */
1242         .recalc         = &omap2_followparent_recalc,
1243 };
1244
1245 static struct clk gpt6_fck = {
1246         .name           = "gpt6_fck",
1247         .parent         = &func_32k_ck,
1248         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1249                                 CM_CORE_SEL2,
1250         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1251         .enable_bit     = 8,
1252         .src_offset     = 10,
1253         .recalc         = &omap2_followparent_recalc,
1254 };
1255
1256 static struct clk gpt7_ick = {
1257         .name           = "gpt7_ick",
1258         .parent         = &l4_ck,
1259         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1260         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit9 */
1261         .enable_bit     = 9,
1262         .recalc         = &omap2_followparent_recalc,
1263 };
1264
1265 static struct clk gpt7_fck = {
1266         .name           = "gpt7_fck",
1267         .parent         = &func_32k_ck,
1268         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1269                                 CM_CORE_SEL2,
1270         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1271         .enable_bit     = 9,
1272         .src_offset     = 12,
1273         .recalc         = &omap2_followparent_recalc,
1274 };
1275
1276 static struct clk gpt8_ick = {
1277         .name           = "gpt8_ick",
1278         .parent         = &l4_ck,
1279         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1280         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit10 */
1281         .enable_bit     = 10,
1282         .recalc         = &omap2_followparent_recalc,
1283 };
1284
1285 static struct clk gpt8_fck = {
1286         .name           = "gpt8_fck",
1287         .parent         = &func_32k_ck,
1288         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1289                                 CM_CORE_SEL2,
1290         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1291         .enable_bit     = 10,
1292         .src_offset     = 14,
1293         .recalc         = &omap2_followparent_recalc,
1294 };
1295
1296 static struct clk gpt9_ick = {
1297         .name           = "gpt9_ick",
1298         .parent         = &l4_ck,
1299         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1300         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1301         .enable_bit     = 11,
1302         .recalc         = &omap2_followparent_recalc,
1303 };
1304
1305 static struct clk gpt9_fck = {
1306         .name           = "gpt9_fck",
1307         .parent         = &func_32k_ck,
1308         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1309                                         CM_CORE_SEL2,
1310         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1311         .enable_bit     = 11,
1312         .src_offset     = 16,
1313         .recalc         = &omap2_followparent_recalc,
1314 };
1315
1316 static struct clk gpt10_ick = {
1317         .name           = "gpt10_ick",
1318         .parent         = &l4_ck,
1319         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1320         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1321         .enable_bit     = 12,
1322         .recalc         = &omap2_followparent_recalc,
1323 };
1324
1325 static struct clk gpt10_fck = {
1326         .name           = "gpt10_fck",
1327         .parent         = &func_32k_ck,
1328         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1329                                         CM_CORE_SEL2,
1330         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1331         .enable_bit     = 12,
1332         .src_offset     = 18,
1333         .recalc         = &omap2_followparent_recalc,
1334 };
1335
1336 static struct clk gpt11_ick = {
1337         .name           = "gpt11_ick",
1338         .parent         = &l4_ck,
1339         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1340         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1341         .enable_bit     = 13,
1342         .recalc         = &omap2_followparent_recalc,
1343 };
1344
1345 static struct clk gpt11_fck = {
1346         .name           = "gpt11_fck",
1347         .parent         = &func_32k_ck,
1348         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1349                                         CM_CORE_SEL2,
1350         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1351         .enable_bit     = 13,
1352         .src_offset     = 20,
1353         .recalc         = &omap2_followparent_recalc,
1354 };
1355
1356 static struct clk gpt12_ick = {
1357         .name           = "gpt12_ick",
1358         .parent         = &l4_ck,
1359         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1360         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit14 */
1361         .enable_bit     = 14,
1362         .recalc         = &omap2_followparent_recalc,
1363 };
1364
1365 static struct clk gpt12_fck = {
1366         .name           = "gpt12_fck",
1367         .parent         = &func_32k_ck,
1368         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1369                                         CM_CORE_SEL2,
1370         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1371         .enable_bit     = 14,
1372         .src_offset     = 22,
1373         .recalc         = &omap2_followparent_recalc,
1374 };
1375
1376 static struct clk mcbsp1_ick = {
1377         .name           = "mcbsp1_ick",
1378         .parent         = &l4_ck,
1379         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1380         .enable_bit     = 15,
1381         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit16 */
1382         .recalc         = &omap2_followparent_recalc,
1383 };
1384
1385 static struct clk mcbsp1_fck = {
1386         .name           = "mcbsp1_fck",
1387         .parent         = &func_96m_ck,
1388         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1389         .enable_bit     = 15,
1390         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1391         .recalc         = &omap2_followparent_recalc,
1392 };
1393
1394 static struct clk mcbsp2_ick = {
1395         .name           = "mcbsp2_ick",
1396         .parent         = &l4_ck,
1397         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1398         .enable_bit     = 16,
1399         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1400         .recalc         = &omap2_followparent_recalc,
1401 };
1402
1403 static struct clk mcbsp2_fck = {
1404         .name           = "mcbsp2_fck",
1405         .parent         = &func_96m_ck,
1406         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1407         .enable_bit     = 16,
1408         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1409         .recalc         = &omap2_followparent_recalc,
1410 };
1411
1412 static struct clk mcbsp3_ick = {
1413         .name           = "mcbsp3_ick",
1414         .parent         = &l4_ck,
1415         .flags          = CLOCK_IN_OMAP243X,
1416         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1417         .enable_bit     = 3,
1418         .recalc         = &omap2_followparent_recalc,
1419 };
1420
1421 static struct clk mcbsp3_fck = {
1422         .name           = "mcbsp3_fck",
1423         .parent         = &func_96m_ck,
1424         .flags          = CLOCK_IN_OMAP243X,
1425         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1426         .enable_bit     = 3,
1427         .recalc         = &omap2_followparent_recalc,
1428 };
1429
1430 static struct clk mcbsp4_ick = {
1431         .name           = "mcbsp4_ick",
1432         .parent         = &l4_ck,
1433         .flags          = CLOCK_IN_OMAP243X,
1434         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1435         .enable_bit     = 4,
1436         .recalc         = &omap2_followparent_recalc,
1437 };
1438
1439 static struct clk mcbsp4_fck = {
1440         .name           = "mcbsp4_fck",
1441         .parent         = &func_96m_ck,
1442         .flags          = CLOCK_IN_OMAP243X,
1443         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1444         .enable_bit     = 4,
1445         .recalc         = &omap2_followparent_recalc,
1446 };
1447
1448 static struct clk mcbsp5_ick = {
1449         .name           = "mcbsp5_ick",
1450         .parent         = &l4_ck,
1451         .flags          = CLOCK_IN_OMAP243X,
1452         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1453         .enable_bit     = 5,
1454         .recalc         = &omap2_followparent_recalc,
1455 };
1456
1457 static struct clk mcbsp5_fck = {
1458         .name           = "mcbsp5_fck",
1459         .parent         = &func_96m_ck,
1460         .flags          = CLOCK_IN_OMAP243X,
1461         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1462         .enable_bit     = 5,
1463         .recalc         = &omap2_followparent_recalc,
1464 };
1465
1466 static struct clk mcspi1_ick = {
1467         .name           = "mcspi_ick",
1468         .id             = 1,
1469         .parent         = &l4_ck,
1470         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1471         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1472         .enable_bit     = 17,
1473         .recalc         = &omap2_followparent_recalc,
1474 };
1475
1476 static struct clk mcspi1_fck = {
1477         .name           = "mcspi_fck",
1478         .id             = 1,
1479         .parent         = &func_48m_ck,
1480         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1481         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1482         .enable_bit     = 17,
1483         .recalc         = &omap2_followparent_recalc,
1484 };
1485
1486 static struct clk mcspi2_ick = {
1487         .name           = "mcspi_ick",
1488         .id             = 2,
1489         .parent         = &l4_ck,
1490         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1491         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1492         .enable_bit     = 18,
1493         .recalc         = &omap2_followparent_recalc,
1494 };
1495
1496 static struct clk mcspi2_fck = {
1497         .name           = "mcspi_fck",
1498         .id             = 2,
1499         .parent         = &func_48m_ck,
1500         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1501         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1502         .enable_bit     = 18,
1503         .recalc         = &omap2_followparent_recalc,
1504 };
1505
1506 static struct clk mcspi3_ick = {
1507         .name           = "mcspi_ick",
1508         .id             = 3,
1509         .parent         = &l4_ck,
1510         .flags          = CLOCK_IN_OMAP243X,
1511         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1512         .enable_bit     = 9,
1513         .recalc         = &omap2_followparent_recalc,
1514 };
1515
1516 static struct clk mcspi3_fck = {
1517         .name           = "mcspi_fck",
1518         .id             = 3,
1519         .parent         = &func_48m_ck,
1520         .flags          = CLOCK_IN_OMAP243X,
1521         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1522         .enable_bit     = 9,
1523         .recalc         = &omap2_followparent_recalc,
1524 };
1525
1526 static struct clk uart1_ick = {
1527         .name           = "uart1_ick",
1528         .parent         = &l4_ck,
1529         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1530         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1531         .enable_bit     = 21,
1532         .recalc         = &omap2_followparent_recalc,
1533 };
1534
1535 static struct clk uart1_fck = {
1536         .name           = "uart1_fck",
1537         .parent         = &func_48m_ck,
1538         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1539         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1540         .enable_bit     = 21,
1541         .recalc         = &omap2_followparent_recalc,
1542 };
1543
1544 static struct clk uart2_ick = {
1545         .name           = "uart2_ick",
1546         .parent         = &l4_ck,
1547         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1548         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1549         .enable_bit     = 22,
1550         .recalc         = &omap2_followparent_recalc,
1551 };
1552
1553 static struct clk uart2_fck = {
1554         .name           = "uart2_fck",
1555         .parent         = &func_48m_ck,
1556         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1558         .enable_bit     = 22,
1559         .recalc         = &omap2_followparent_recalc,
1560 };
1561
1562 static struct clk uart3_ick = {
1563         .name           = "uart3_ick",
1564         .parent         = &l4_ck,
1565         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1566         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1567         .enable_bit     = 2,
1568         .recalc         = &omap2_followparent_recalc,
1569 };
1570
1571 static struct clk uart3_fck = {
1572         .name           = "uart3_fck",
1573         .parent         = &func_48m_ck,
1574         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1575         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1576         .enable_bit     = 2,
1577         .recalc         = &omap2_followparent_recalc,
1578 };
1579
1580 static struct clk gpios_ick = {
1581         .name           = "gpios_ick",
1582         .parent         = &l4_ck,
1583         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1584         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1585         .enable_bit     = 2,
1586         .recalc         = &omap2_followparent_recalc,
1587 };
1588
1589 static struct clk gpios_fck = {
1590         .name           = "gpios_fck",
1591         .parent         = &func_32k_ck,
1592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1593         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
1594         .enable_bit     = 2,
1595         .recalc         = &omap2_followparent_recalc,
1596 };
1597
1598 static struct clk mpu_wdt_ick = {
1599         .name           = "mpu_wdt_ick",
1600         .parent         = &l4_ck,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1603         .enable_bit     = 3,
1604         .recalc         = &omap2_followparent_recalc,
1605 };
1606
1607 static struct clk mpu_wdt_fck = {
1608         .name           = "mpu_wdt_fck",
1609         .parent         = &func_32k_ck,
1610         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
1612         .enable_bit     = 3,
1613         .recalc         = &omap2_followparent_recalc,
1614 };
1615
1616 static struct clk sync_32k_ick = {
1617         .name           = "sync_32k_ick",
1618         .parent         = &l4_ck,
1619         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1620         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1621         .enable_bit     = 1,
1622         .recalc         = &omap2_followparent_recalc,
1623 };
1624 static struct clk wdt1_ick = {
1625         .name           = "wdt1_ick",
1626         .parent         = &l4_ck,
1627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1628         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1629         .enable_bit     = 4,
1630         .recalc         = &omap2_followparent_recalc,
1631 };
1632 static struct clk omapctrl_ick = {
1633         .name           = "omapctrl_ick",
1634         .parent         = &l4_ck,
1635         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1636         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1637         .enable_bit     = 5,
1638         .recalc         = &omap2_followparent_recalc,
1639 };
1640 static struct clk icr_ick = {
1641         .name           = "icr_ick",
1642         .parent         = &l4_ck,
1643         .flags          = CLOCK_IN_OMAP243X,
1644         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1645         .enable_bit     = 6,
1646         .recalc         = &omap2_followparent_recalc,
1647 };
1648
1649 static struct clk cam_ick = {
1650         .name           = "cam_ick",
1651         .parent         = &l4_ck,
1652         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1654         .enable_bit     = 31,
1655         .recalc         = &omap2_followparent_recalc,
1656 };
1657
1658 static struct clk cam_fck = {
1659         .name           = "cam_fck",
1660         .parent         = &func_96m_ck,
1661         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1662         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1663         .enable_bit     = 31,
1664         .recalc         = &omap2_followparent_recalc,
1665 };
1666
1667 static struct clk mailboxes_ick = {
1668         .name           = "mailboxes_ick",
1669         .parent         = &l4_ck,
1670         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1671         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1672         .enable_bit     = 30,
1673         .recalc         = &omap2_followparent_recalc,
1674 };
1675
1676 static struct clk wdt4_ick = {
1677         .name           = "wdt4_ick",
1678         .parent         = &l4_ck,
1679         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1680         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1681         .enable_bit     = 29,
1682         .recalc         = &omap2_followparent_recalc,
1683 };
1684
1685 static struct clk wdt4_fck = {
1686         .name           = "wdt4_fck",
1687         .parent         = &func_32k_ck,
1688         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1689         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1690         .enable_bit     = 29,
1691         .recalc         = &omap2_followparent_recalc,
1692 };
1693
1694 static struct clk wdt3_ick = {
1695         .name           = "wdt3_ick",
1696         .parent         = &l4_ck,
1697         .flags          = CLOCK_IN_OMAP242X,
1698         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1699         .enable_bit     = 28,
1700         .recalc         = &omap2_followparent_recalc,
1701 };
1702
1703 static struct clk wdt3_fck = {
1704         .name           = "wdt3_fck",
1705         .parent         = &func_32k_ck,
1706         .flags          = CLOCK_IN_OMAP242X,
1707         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1708         .enable_bit     = 28,
1709         .recalc         = &omap2_followparent_recalc,
1710 };
1711
1712 static struct clk mspro_ick = {
1713         .name           = "mspro_ick",
1714         .parent         = &l4_ck,
1715         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1717         .enable_bit     = 27,
1718         .recalc         = &omap2_followparent_recalc,
1719 };
1720
1721 static struct clk mspro_fck = {
1722         .name           = "mspro_fck",
1723         .parent         = &func_96m_ck,
1724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1726         .enable_bit     = 27,
1727         .recalc         = &omap2_followparent_recalc,
1728 };
1729
1730 static struct clk mmc_ick = {
1731         .name           = "mmc_ick",
1732         .parent         = &l4_ck,
1733         .flags          = CLOCK_IN_OMAP242X,
1734         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1735         .enable_bit     = 26,
1736         .recalc         = &omap2_followparent_recalc,
1737 };
1738
1739 static struct clk mmc_fck = {
1740         .name           = "mmc_fck",
1741         .parent         = &func_96m_ck,
1742         .flags          = CLOCK_IN_OMAP242X,
1743         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1744         .enable_bit     = 26,
1745         .recalc         = &omap2_followparent_recalc,
1746 };
1747
1748 static struct clk fac_ick = {
1749         .name           = "fac_ick",
1750         .parent         = &l4_ck,
1751         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1752         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1753         .enable_bit     = 25,
1754         .recalc         = &omap2_followparent_recalc,
1755 };
1756
1757 static struct clk fac_fck = {
1758         .name           = "fac_fck",
1759         .parent         = &func_12m_ck,
1760         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1761         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1762         .enable_bit     = 25,
1763         .recalc         = &omap2_followparent_recalc,
1764 };
1765
1766 static struct clk eac_ick = {
1767         .name           = "eac_ick",
1768         .parent         = &l4_ck,
1769         .flags          = CLOCK_IN_OMAP242X,
1770         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1771         .enable_bit     = 24,
1772         .recalc         = &omap2_followparent_recalc,
1773 };
1774
1775 static struct clk eac_fck = {
1776         .name           = "eac_fck",
1777         .parent         = &func_96m_ck,
1778         .flags          = CLOCK_IN_OMAP242X,
1779         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1780         .enable_bit     = 24,
1781         .recalc         = &omap2_followparent_recalc,
1782 };
1783
1784 static struct clk hdq_ick = {
1785         .name           = "hdq_ick",
1786         .parent         = &l4_ck,
1787         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1789         .enable_bit     = 23,
1790         .recalc         = &omap2_followparent_recalc,
1791 };
1792
1793 static struct clk hdq_fck = {
1794         .name           = "hdq_fck",
1795         .parent         = &func_12m_ck,
1796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1797         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1798         .enable_bit     = 23,
1799         .recalc         = &omap2_followparent_recalc,
1800 };
1801
1802 static struct clk i2c2_ick = {
1803         .name           = "i2c_ick",
1804         .id             = 2,
1805         .parent         = &l4_ck,
1806         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1807         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1808         .enable_bit     = 20,
1809         .recalc         = &omap2_followparent_recalc,
1810 };
1811
1812 static struct clk i2c2_fck = {
1813         .name           = "i2c_fck",
1814         .id             = 2,
1815         .parent         = &func_12m_ck,
1816         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1817         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1818         .enable_bit     = 20,
1819         .recalc         = &omap2_followparent_recalc,
1820 };
1821
1822 static struct clk i2chs2_fck = {
1823         .name           = "i2chs2_fck",
1824         .parent         = &func_96m_ck,
1825         .flags          = CLOCK_IN_OMAP243X,
1826         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1827         .enable_bit     = 20,
1828         .recalc         = &omap2_followparent_recalc,
1829 };
1830
1831 static struct clk i2c1_ick = {
1832         .name           = "i2c_ick",
1833         .id             = 1,
1834         .parent         = &l4_ck,
1835         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1836         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1837         .enable_bit     = 19,
1838         .recalc         = &omap2_followparent_recalc,
1839 };
1840
1841 static struct clk i2c1_fck = {
1842         .name           = "i2c_fck",
1843         .id             = 1,
1844         .parent         = &func_12m_ck,
1845         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1847         .enable_bit     = 19,
1848         .recalc         = &omap2_followparent_recalc,
1849 };
1850
1851 static struct clk i2chs1_fck = {
1852         .name           = "i2chs1_fck",
1853         .parent         = &func_96m_ck,
1854         .flags          = CLOCK_IN_OMAP243X,
1855         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1856         .enable_bit     = 19,
1857         .recalc         = &omap2_followparent_recalc,
1858 };
1859
1860 static struct clk vlynq_ick = {
1861         .name           = "vlynq_ick",
1862         .parent         = &core_l3_ck,
1863         .flags          = CLOCK_IN_OMAP242X,
1864         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1865         .enable_bit     = 3,
1866         .recalc         = &omap2_followparent_recalc,
1867 };
1868
1869 static struct clk vlynq_fck = {
1870         .name           = "vlynq_fck",
1871         .parent         = &func_96m_ck,
1872         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1873         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1874         .enable_bit     = 3,
1875         .src_offset     = 15,
1876         .recalc         = &omap2_followparent_recalc,
1877 };
1878
1879 static struct clk sdrc_ick = {
1880         .name           = "sdrc_ick",
1881         .parent         = &l4_ck,
1882         .flags          = CLOCK_IN_OMAP243X,
1883         .enable_reg     = (void __iomem *)&CM_ICLKEN3_CORE,
1884         .enable_bit     = 2,
1885         .recalc         = &omap2_followparent_recalc,
1886 };
1887
1888 static struct clk des_ick = {
1889         .name           = "des_ick",
1890         .parent         = &l4_ck,
1891         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1892         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1893         .enable_bit     = 0,
1894         .recalc         = &omap2_followparent_recalc,
1895 };
1896
1897 static struct clk sha_ick = {
1898         .name           = "sha_ick",
1899         .parent         = &l4_ck,
1900         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1901         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1902         .enable_bit     = 1,
1903         .recalc         = &omap2_followparent_recalc,
1904 };
1905
1906 static struct clk rng_ick = {
1907         .name           = "rng_ick",
1908         .parent         = &l4_ck,
1909         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1910         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1911         .enable_bit     = 2,
1912         .recalc         = &omap2_followparent_recalc,
1913 };
1914
1915 static struct clk aes_ick = {
1916         .name           = "aes_ick",
1917         .parent         = &l4_ck,
1918         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1919         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1920         .enable_bit     = 3,
1921         .recalc         = &omap2_followparent_recalc,
1922 };
1923
1924 static struct clk pka_ick = {
1925         .name           = "pka_ick",
1926         .parent         = &l4_ck,
1927         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1928         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1929         .enable_bit     = 4,
1930         .recalc         = &omap2_followparent_recalc,
1931 };
1932
1933 static struct clk usb_fck = {
1934         .name           = "usb_fck",
1935         .parent         = &func_48m_ck,
1936         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1937         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1938         .enable_bit     = 0,
1939         .recalc         = &omap2_followparent_recalc,
1940 };
1941
1942 static struct clk usbhs_ick = {
1943         .name           = "usbhs_ick",
1944         .parent         = &core_l3_ck,
1945         .flags          = CLOCK_IN_OMAP243X,
1946         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1947         .enable_bit     = 6,
1948         .recalc         = &omap2_followparent_recalc,
1949 };
1950
1951 static struct clk mmchs1_ick = {
1952         .name           = "mmchs1_ick",
1953         .parent         = &l4_ck,
1954         .flags          = CLOCK_IN_OMAP243X,
1955         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1956         .enable_bit     = 7,
1957         .recalc         = &omap2_followparent_recalc,
1958 };
1959
1960 static struct clk mmchs1_fck = {
1961         .name           = "mmchs1_fck",
1962         .parent         = &func_96m_ck,
1963         .flags          = CLOCK_IN_OMAP243X,
1964         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1965         .enable_bit     = 7,
1966         .recalc         = &omap2_followparent_recalc,
1967 };
1968
1969 static struct clk mmchs2_ick = {
1970         .name           = "mmchs2_ick",
1971         .parent         = &l4_ck,
1972         .flags          = CLOCK_IN_OMAP243X,
1973         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1974         .enable_bit     = 8,
1975         .recalc         = &omap2_followparent_recalc,
1976 };
1977
1978 static struct clk mmchs2_fck = {
1979         .name           = "mmchs2_fck",
1980         .parent         = &func_96m_ck,
1981         .flags          = CLOCK_IN_OMAP243X,
1982         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1983         .enable_bit     = 8,
1984         .recalc         = &omap2_followparent_recalc,
1985 };
1986
1987 static struct clk gpio5_ick = {
1988         .name           = "gpio5_ick",
1989         .parent         = &l4_ck,
1990         .flags          = CLOCK_IN_OMAP243X,
1991         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1992         .enable_bit     = 10,
1993         .recalc         = &omap2_followparent_recalc,
1994 };
1995
1996 static struct clk gpio5_fck = {
1997         .name           = "gpio5_fck",
1998         .parent         = &func_32k_ck,
1999         .flags          = CLOCK_IN_OMAP243X,
2000         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
2001         .enable_bit     = 10,
2002         .recalc         = &omap2_followparent_recalc,
2003 };
2004
2005 static struct clk mdm_intc_ick = {
2006         .name           = "mdm_intc_ick",
2007         .parent         = &l4_ck,
2008         .flags          = CLOCK_IN_OMAP243X,
2009         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
2010         .enable_bit     = 11,
2011         .recalc         = &omap2_followparent_recalc,
2012 };
2013
2014 static struct clk mmchsdb1_fck = {
2015         .name           = "mmchsdb1_fck",
2016         .parent         = &func_32k_ck,
2017         .flags          = CLOCK_IN_OMAP243X,
2018         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
2019         .enable_bit     = 16,
2020         .recalc         = &omap2_followparent_recalc,
2021 };
2022
2023 static struct clk mmchsdb2_fck = {
2024         .name           = "mmchsdb2_fck",
2025         .parent         = &func_32k_ck,
2026         .flags          = CLOCK_IN_OMAP243X,
2027         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
2028         .enable_bit     = 17,
2029         .recalc         = &omap2_followparent_recalc,
2030 };
2031 #endif  /* OLD_CK */
2032 /*
2033  * This clock is a composite clock which does entire set changes then
2034  * forces a rebalance. It keys on the MPU speed, but it really could
2035  * be any key speed part of a set in the rate table.
2036  *
2037  * to really change a set, you need memory table sets which get changed
2038  * in sram, pre-notifiers & post notifiers, changing the top set, without
2039  * having low level display recalc's won't work... this is why dpm notifiers
2040  * work, isr's off, walk a list of clocks already _off_ and not messing with
2041  * the bus.
2042  *
2043  * This clock should have no parent. It embodies the entire upper level
2044  * active set. A parent will mess up some of the init also.
2045  */
2046 static struct clk virt_prcm_set = {
2047         .name           = "virt_prcm_set",
2048         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2049                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2050         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2051         .set_rate       = &omap2_select_table_rate,
2052         .round_rate     = &omap2_round_to_table_rate,
2053 };
2054 #ifdef OLD_CK
2055 static struct clk *onchip_clks[] = {
2056         /* external root sources */
2057         &func_32k_ck,
2058         &osc_ck,
2059         &sys_ck,
2060         &alt_ck,
2061         /* internal analog sources */
2062         &dpll_ck,
2063         &apll96_ck,
2064         &apll54_ck,
2065         /* internal prcm root sources */
2066         &func_54m_ck,
2067         &core_ck,
2068         &sleep_ck,
2069         &func_96m_ck,
2070         &func_48m_ck,
2071         &func_12m_ck,
2072         &wdt1_osc_ck,
2073         &sys_clkout,
2074         &sys_clkout2,
2075         &emul_ck,
2076         /* mpu domain clocks */
2077         &mpu_ck,
2078         /* dsp domain clocks */
2079         &iva2_1_fck,            /* 2430 */
2080         &iva2_1_ick,
2081         &dsp_ick,               /* 2420 */
2082         &dsp_fck,
2083         &iva1_ifck,
2084         &iva1_mpu_int_ifck,
2085         /* GFX domain clocks */
2086         &gfx_3d_fck,
2087         &gfx_2d_fck,
2088         &gfx_ick,
2089         /* Modem domain clocks */
2090         &mdm_ick,
2091         &mdm_osc_ck,
2092         /* DSS domain clocks */
2093         &dss_ick,
2094         &dss1_fck,
2095         &dss2_fck,
2096         &dss_54m_fck,
2097         /* L3 domain clocks */
2098         &core_l3_ck,
2099         &ssi_ssr_sst_fck,
2100         &usb_l4_ick,
2101         /* L4 domain clocks */
2102         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2103         &ssi_l4_ick,
2104         /* virtual meta-group clock */
2105         &virt_prcm_set,
2106         /* general l4 interface ck, multi-parent functional clk */
2107         &gpt1_ick,
2108         &gpt1_fck,
2109         &gpt2_ick,
2110         &gpt2_fck,
2111         &gpt3_ick,
2112         &gpt3_fck,
2113         &gpt4_ick,
2114         &gpt4_fck,
2115         &gpt5_ick,
2116         &gpt5_fck,
2117         &gpt6_ick,
2118         &gpt6_fck,
2119         &gpt7_ick,
2120         &gpt7_fck,
2121         &gpt8_ick,
2122         &gpt8_fck,
2123         &gpt9_ick,
2124         &gpt9_fck,
2125         &gpt10_ick,
2126         &gpt10_fck,
2127         &gpt11_ick,
2128         &gpt11_fck,
2129         &gpt12_ick,
2130         &gpt12_fck,
2131         &mcbsp1_ick,
2132         &mcbsp1_fck,
2133         &mcbsp2_ick,
2134         &mcbsp2_fck,
2135         &mcbsp3_ick,
2136         &mcbsp3_fck,
2137         &mcbsp4_ick,
2138         &mcbsp4_fck,
2139         &mcbsp5_ick,
2140         &mcbsp5_fck,
2141         &mcspi1_ick,
2142         &mcspi1_fck,
2143         &mcspi2_ick,
2144         &mcspi2_fck,
2145         &mcspi3_ick,
2146         &mcspi3_fck,
2147         &uart1_ick,
2148         &uart1_fck,
2149         &uart2_ick,
2150         &uart2_fck,
2151         &uart3_ick,
2152         &uart3_fck,
2153         &gpios_ick,
2154         &gpios_fck,
2155         &mpu_wdt_ick,
2156         &mpu_wdt_fck,
2157         &sync_32k_ick,
2158         &wdt1_ick,
2159         &omapctrl_ick,
2160         &icr_ick,
2161         &cam_fck,
2162         &cam_ick,
2163         &mailboxes_ick,
2164         &wdt4_ick,
2165         &wdt4_fck,
2166         &wdt3_ick,
2167         &wdt3_fck,
2168         &mspro_ick,
2169         &mspro_fck,
2170         &mmc_ick,
2171         &mmc_fck,
2172         &fac_ick,
2173         &fac_fck,
2174         &eac_ick,
2175         &eac_fck,
2176         &hdq_ick,
2177         &hdq_fck,
2178         &i2c1_ick,
2179         &i2c1_fck,
2180         &i2chs1_fck,
2181         &i2c2_ick,
2182         &i2c2_fck,
2183         &i2chs2_fck,
2184         &vlynq_ick,
2185         &vlynq_fck,
2186         &sdrc_ick,
2187         &des_ick,
2188         &sha_ick,
2189         &rng_ick,
2190         &aes_ick,
2191         &pka_ick,
2192         &usb_fck,
2193         &usbhs_ick,
2194         &mmchs1_ick,
2195         &mmchs1_fck,
2196         &mmchs2_ick,
2197         &mmchs2_fck,
2198         &gpio5_ick,
2199         &gpio5_fck,
2200         &mdm_intc_ick,
2201         &mmchsdb1_fck,
2202         &mmchsdb2_fck,
2203 };
2204 #endif  /* OLD_CK */
2205
2206 static struct clk *onchip_24xx_clks[] __initdata = {
2207         /* external root sources */
2208         &osc_ck,
2209         &sys_ck,
2210         /* internal analog sources */
2211         &dpll_ck,
2212         &apll96_ck,
2213         &apll54_ck,
2214 };
2215
2216 #endif
2217