2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/clkdev.h>
22 #include <asm/mach-types.h>
26 #include <plat/clock.h>
27 #include <plat/sram.h>
28 #include <plat/clkdev_omap.h>
30 #include <mach/hardware.h>
36 __u32 arm_idlect1_mask;
37 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
40 * Omap1 specific clock functions
43 unsigned long omap1_uart_recalc(struct clk *clk)
45 unsigned int val = __raw_readl(clk->enable_reg);
46 return val & clk->enable_bit ? 48000000 : 12000000;
49 unsigned long omap1_sossi_recalc(struct clk *clk)
51 u32 div = omap_readl(MOD_CONF_CTRL_1);
53 div = (div >> 17) & 0x7;
56 return clk->parent->rate / div;
59 static void omap1_clk_allow_idle(struct clk *clk)
61 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
63 if (!(clk->flags & CLOCK_IDLE_CONTROL))
66 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
67 arm_idlect1_mask |= 1 << iclk->idlect_shift;
70 static void omap1_clk_deny_idle(struct clk *clk)
72 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
74 if (!(clk->flags & CLOCK_IDLE_CONTROL))
77 if (iclk->no_idle_count++ == 0)
78 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
81 static __u16 verify_ckctl_value(__u16 newval)
83 /* This function checks for following limitations set
84 * by the hardware (all conditions must be true):
85 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
90 * In addition following rules are enforced:
94 * However, maximum frequencies are not checked for!
103 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
104 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
105 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
106 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
107 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
108 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
110 if (dspmmu_exp < dsp_exp)
111 dspmmu_exp = dsp_exp;
112 if (dspmmu_exp > dsp_exp+1)
113 dspmmu_exp = dsp_exp+1;
114 if (tc_exp < arm_exp)
116 if (tc_exp < dspmmu_exp)
118 if (tc_exp > lcd_exp)
120 if (tc_exp > per_exp)
124 newval |= per_exp << CKCTL_PERDIV_OFFSET;
125 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
126 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
127 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
128 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
129 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
134 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
136 /* Note: If target frequency is too low, this function will return 4,
137 * which is invalid value. Caller must check for this value and act
140 * Note: This function does not check for following limitations set
141 * by the hardware (all conditions must be true):
142 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
147 unsigned long realrate;
151 parent = clk->parent;
152 if (unlikely(parent == NULL))
155 realrate = parent->rate;
156 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
157 if (realrate <= rate)
166 unsigned long omap1_ckctl_recalc(struct clk *clk)
168 /* Calculate divisor encoded as 2-bit exponent */
169 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
171 return clk->parent->rate / dsor;
174 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
178 /* Calculate divisor encoded as 2-bit exponent
180 * The clock control bits are in DSP domain,
181 * so api_ck is needed for access.
182 * Note that DSP_CKCTL virt addr = phys addr, so
183 * we must use __raw_readw() instead of omap_readw().
185 omap1_clk_enable(api_ck_p);
186 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
187 omap1_clk_disable(api_ck_p);
189 return clk->parent->rate / dsor;
192 /* MPU virtual clock functions */
193 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
195 /* Find the highest supported frequency <= rate and switch to it */
196 struct mpu_rate * ptr;
197 unsigned long dpll1_rate, ref_rate;
199 dpll1_rate = ck_dpll1_p->rate;
200 ref_rate = ck_ref_p->rate;
202 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
203 if (!(ptr->flags & cpu_mask))
206 if (ptr->xtal != ref_rate)
209 /* Can check only after xtal frequency check */
210 if (ptr->rate <= rate)
218 * In most cases we should not need to reprogram DPLL.
219 * Reprogramming the DPLL is tricky, it must be done from SRAM.
221 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
223 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
224 ck_dpll1_p->rate = ptr->pll_rate;
229 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
234 dsor_exp = calc_dsor_exp(clk, rate);
240 regval = __raw_readw(DSP_CKCTL);
241 regval &= ~(3 << clk->rate_offset);
242 regval |= dsor_exp << clk->rate_offset;
243 __raw_writew(regval, DSP_CKCTL);
244 clk->rate = clk->parent->rate / (1 << dsor_exp);
249 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
251 int dsor_exp = calc_dsor_exp(clk, rate);
256 return clk->parent->rate / (1 << dsor_exp);
259 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
264 dsor_exp = calc_dsor_exp(clk, rate);
270 regval = omap_readw(ARM_CKCTL);
271 regval &= ~(3 << clk->rate_offset);
272 regval |= dsor_exp << clk->rate_offset;
273 regval = verify_ckctl_value(regval);
274 omap_writew(regval, ARM_CKCTL);
275 clk->rate = clk->parent->rate / (1 << dsor_exp);
279 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
281 /* Find the highest supported frequency <= rate */
282 struct mpu_rate * ptr;
284 unsigned long ref_rate;
286 ref_rate = ck_ref_p->rate;
288 highest_rate = -EINVAL;
290 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
291 if (!(ptr->flags & cpu_mask))
294 if (ptr->xtal != ref_rate)
297 highest_rate = ptr->rate;
299 /* Can check only after xtal frequency check */
300 if (ptr->rate <= rate)
307 static unsigned calc_ext_dsor(unsigned long rate)
311 /* MCLK and BCLK divisor selection is not linear:
312 * freq = 96MHz / dsor
314 * RATIO_SEL range: dsor <-> RATIO_SEL
315 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
316 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
317 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
320 for (dsor = 2; dsor < 96; ++dsor) {
321 if ((dsor & 1) && dsor > 8)
323 if (rate >= 96000000 / dsor)
329 /* XXX Only needed on 1510 */
330 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
334 val = __raw_readl(clk->enable_reg);
335 if (rate == 12000000)
336 val &= ~(1 << clk->enable_bit);
337 else if (rate == 48000000)
338 val |= (1 << clk->enable_bit);
341 __raw_writel(val, clk->enable_reg);
347 /* External clock (MCLK & BCLK) functions */
348 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
353 dsor = calc_ext_dsor(rate);
354 clk->rate = 96000000 / dsor;
356 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
358 ratio_bits = (dsor - 2) << 2;
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
361 __raw_writew(ratio_bits, clk->enable_reg);
366 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
370 unsigned long p_rate;
372 p_rate = clk->parent->rate;
373 /* Round towards slower frequency */
374 div = (p_rate + rate - 1) / rate;
376 if (div < 0 || div > 7)
379 l = omap_readl(MOD_CONF_CTRL_1);
382 omap_writel(l, MOD_CONF_CTRL_1);
384 clk->rate = p_rate / (div + 1);
389 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
391 return 96000000 / calc_ext_dsor(rate);
394 void omap1_init_ext_clk(struct clk *clk)
399 /* Determine current rate and ensure clock is based on 96MHz APLL */
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
401 __raw_writew(ratio_bits, clk->enable_reg);
403 ratio_bits = (ratio_bits & 0xfc) >> 2;
405 dsor = (ratio_bits - 6) * 2 + 8;
407 dsor = ratio_bits + 2;
409 clk-> rate = 96000000 / dsor;
412 int omap1_clk_enable(struct clk *clk)
416 if (clk->usecount++ == 0) {
418 ret = omap1_clk_enable(clk->parent);
422 if (clk->flags & CLOCK_NO_IDLE_PARENT)
423 omap1_clk_deny_idle(clk->parent);
426 ret = clk->ops->enable(clk);
429 omap1_clk_disable(clk->parent);
440 void omap1_clk_disable(struct clk *clk)
442 if (clk->usecount > 0 && !(--clk->usecount)) {
443 clk->ops->disable(clk);
444 if (likely(clk->parent)) {
445 omap1_clk_disable(clk->parent);
446 if (clk->flags & CLOCK_NO_IDLE_PARENT)
447 omap1_clk_allow_idle(clk->parent);
452 static int omap1_clk_enable_generic(struct clk *clk)
457 if (unlikely(clk->enable_reg == NULL)) {
458 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
463 if (clk->flags & ENABLE_REG_32BIT) {
464 regval32 = __raw_readl(clk->enable_reg);
465 regval32 |= (1 << clk->enable_bit);
466 __raw_writel(regval32, clk->enable_reg);
468 regval16 = __raw_readw(clk->enable_reg);
469 regval16 |= (1 << clk->enable_bit);
470 __raw_writew(regval16, clk->enable_reg);
476 static void omap1_clk_disable_generic(struct clk *clk)
481 if (clk->enable_reg == NULL)
484 if (clk->flags & ENABLE_REG_32BIT) {
485 regval32 = __raw_readl(clk->enable_reg);
486 regval32 &= ~(1 << clk->enable_bit);
487 __raw_writel(regval32, clk->enable_reg);
489 regval16 = __raw_readw(clk->enable_reg);
490 regval16 &= ~(1 << clk->enable_bit);
491 __raw_writew(regval16, clk->enable_reg);
495 const struct clkops clkops_generic = {
496 .enable = omap1_clk_enable_generic,
497 .disable = omap1_clk_disable_generic,
500 static int omap1_clk_enable_dsp_domain(struct clk *clk)
504 retval = omap1_clk_enable(api_ck_p);
506 retval = omap1_clk_enable_generic(clk);
507 omap1_clk_disable(api_ck_p);
513 static void omap1_clk_disable_dsp_domain(struct clk *clk)
515 if (omap1_clk_enable(api_ck_p) == 0) {
516 omap1_clk_disable_generic(clk);
517 omap1_clk_disable(api_ck_p);
521 const struct clkops clkops_dspck = {
522 .enable = omap1_clk_enable_dsp_domain,
523 .disable = omap1_clk_disable_dsp_domain,
526 /* XXX SYSC register handling does not belong in the clock framework */
527 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
530 struct uart_clk *uclk;
532 ret = omap1_clk_enable_generic(clk);
534 /* Set smart idle acknowledgement mode */
535 uclk = (struct uart_clk *)clk;
536 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
543 /* XXX SYSC register handling does not belong in the clock framework */
544 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
546 struct uart_clk *uclk;
548 /* Set force idle acknowledgement mode */
549 uclk = (struct uart_clk *)clk;
550 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
552 omap1_clk_disable_generic(clk);
555 /* XXX SYSC register handling does not belong in the clock framework */
556 const struct clkops clkops_uart_16xx = {
557 .enable = omap1_clk_enable_uart_functional_16xx,
558 .disable = omap1_clk_disable_uart_functional_16xx,
561 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
563 if (clk->round_rate != NULL)
564 return clk->round_rate(clk, rate);
569 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
574 ret = clk->set_rate(clk, rate);
579 * Omap1 clock reset and init functions
582 #ifdef CONFIG_OMAP_RESET_CLOCKS
584 void omap1_clk_disable_unused(struct clk *clk)
588 /* Clocks in the DSP domain need api_ck. Just assume bootloader
589 * has not enabled any DSP clocks */
590 if (clk->enable_reg == DSP_IDLECT2) {
591 printk(KERN_INFO "Skipping reset check for DSP domain "
592 "clock \"%s\"\n", clk->name);
596 /* Is the clock already disabled? */
597 if (clk->flags & ENABLE_REG_32BIT)
598 regval32 = __raw_readl(clk->enable_reg);
600 regval32 = __raw_readw(clk->enable_reg);
602 if ((regval32 & (1 << clk->enable_bit)) == 0)
605 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
606 clk->ops->disable(clk);