Merge branch 'imx/clk' into next/clk
[linux-2.6.git] / arch / arm / mach-mxs / clock-mx28.c
1 /*
2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License along
15  * with this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18
19 #include <linux/mm.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/jiffies.h>
24 #include <linux/clkdev.h>
25
26 #include <asm/clkdev.h>
27 #include <asm/div64.h>
28
29 #include <mach/mx28.h>
30 #include <mach/common.h>
31 #include <mach/clock.h>
32
33 #include "regs-clkctrl-mx28.h"
34
35 #define CLKCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
36 #define DIGCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
37
38 #define PARENT_RATE_SHIFT       8
39
40 static struct clk pll2_clk;
41 static struct clk cpu_clk;
42 static struct clk emi_clk;
43 static struct clk saif0_clk;
44 static struct clk saif1_clk;
45 static struct clk clk32k_clk;
46
47 static int _raw_clk_enable(struct clk *clk)
48 {
49         u32 reg;
50
51         if (clk->enable_reg) {
52                 reg = __raw_readl(clk->enable_reg);
53                 reg &= ~(1 << clk->enable_shift);
54                 __raw_writel(reg, clk->enable_reg);
55         }
56
57         return 0;
58 }
59
60 static void _raw_clk_disable(struct clk *clk)
61 {
62         u32 reg;
63
64         if (clk->enable_reg) {
65                 reg = __raw_readl(clk->enable_reg);
66                 reg |= 1 << clk->enable_shift;
67                 __raw_writel(reg, clk->enable_reg);
68         }
69 }
70
71 /*
72  * ref_xtal_clk
73  */
74 static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
75 {
76         return 24000000;
77 }
78
79 static struct clk ref_xtal_clk = {
80         .get_rate = ref_xtal_clk_get_rate,
81 };
82
83 /*
84  * pll_clk
85  */
86 static unsigned long pll0_clk_get_rate(struct clk *clk)
87 {
88         return 480000000;
89 }
90
91 static unsigned long pll1_clk_get_rate(struct clk *clk)
92 {
93         return 480000000;
94 }
95
96 static unsigned long pll2_clk_get_rate(struct clk *clk)
97 {
98         return 50000000;
99 }
100
101 #define _CLK_ENABLE_PLL(name, r, g)                                     \
102 static int name##_enable(struct clk *clk)                               \
103 {                                                                       \
104         __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
105                      CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET);    \
106         udelay(10);                                                     \
107                                                                         \
108         if (clk == &pll2_clk)                                           \
109                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
110                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
111         else                                                            \
112                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
113                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
114                                                                         \
115         return 0;                                                       \
116 }
117
118 _CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
119 _CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
120 _CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
121
122 #define _CLK_DISABLE_PLL(name, r, g)                                    \
123 static void name##_disable(struct clk *clk)                             \
124 {                                                                       \
125         __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
126                      CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR);    \
127                                                                         \
128         if (clk == &pll2_clk)                                           \
129                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
130                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
131         else                                                            \
132                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
133                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
134                                                                         \
135 }
136
137 _CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
138 _CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
139 _CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
140
141 #define _DEFINE_CLOCK_PLL(name)                                         \
142         static struct clk name = {                                      \
143                 .get_rate       = name##_get_rate,                      \
144                 .enable         = name##_enable,                        \
145                 .disable        = name##_disable,                       \
146                 .parent         = &ref_xtal_clk,                        \
147         }
148
149 _DEFINE_CLOCK_PLL(pll0_clk);
150 _DEFINE_CLOCK_PLL(pll1_clk);
151 _DEFINE_CLOCK_PLL(pll2_clk);
152
153 /*
154  * ref_clk
155  */
156 #define _CLK_GET_RATE_REF(name, sr, ss)                                 \
157 static unsigned long name##_get_rate(struct clk *clk)                   \
158 {                                                                       \
159         unsigned long parent_rate;                                      \
160         u32 reg, div;                                                   \
161                                                                         \
162         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
163         div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
164         parent_rate = clk_get_rate(clk->parent);                        \
165                                                                         \
166         return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
167                         div, PARENT_RATE_SHIFT);                        \
168 }
169
170 _CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
171 _CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
172 _CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
173 _CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
174 _CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
175 _CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
176
177 #define _DEFINE_CLOCK_REF(name, er, es)                                 \
178         static struct clk name = {                                      \
179                 .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
180                 .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
181                 .get_rate       = name##_get_rate,                      \
182                 .enable         = _raw_clk_enable,                      \
183                 .disable        = _raw_clk_disable,                     \
184                 .parent         = &pll0_clk,                            \
185         }
186
187 _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
188 _DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
189 _DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
190 _DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
191 _DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
192 _DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
193
194 /*
195  * General clocks
196  *
197  * clk_get_rate
198  */
199 static unsigned long lradc_clk_get_rate(struct clk *clk)
200 {
201         return clk_get_rate(clk->parent) / 16;
202 }
203
204 static unsigned long rtc_clk_get_rate(struct clk *clk)
205 {
206         /* ref_xtal_clk is implemented as the only parent */
207         return clk_get_rate(clk->parent) / 768;
208 }
209
210 static unsigned long clk32k_clk_get_rate(struct clk *clk)
211 {
212         return clk->parent->get_rate(clk->parent) / 750;
213 }
214
215 static unsigned long spdif_clk_get_rate(struct clk *clk)
216 {
217         return clk_get_rate(clk->parent) / 4;
218 }
219
220 #define _CLK_GET_RATE(name, rs)                                         \
221 static unsigned long name##_get_rate(struct clk *clk)                   \
222 {                                                                       \
223         u32 reg, div;                                                   \
224                                                                         \
225         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
226                                                                         \
227         if (clk->parent == &ref_xtal_clk)                               \
228                 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
229                         BP_CLKCTRL_##rs##_DIV_XTAL;                     \
230         else                                                            \
231                 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
232                         BP_CLKCTRL_##rs##_DIV_##rs;                     \
233                                                                         \
234         if (!div)                                                       \
235                 return -EINVAL;                                         \
236                                                                         \
237         return clk_get_rate(clk->parent) / div;                         \
238 }
239
240 _CLK_GET_RATE(cpu_clk, CPU)
241 _CLK_GET_RATE(emi_clk, EMI)
242
243 #define _CLK_GET_RATE1(name, rs)                                        \
244 static unsigned long name##_get_rate(struct clk *clk)                   \
245 {                                                                       \
246         u32 reg, div;                                                   \
247                                                                         \
248         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
249         div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
250                                                                         \
251         if (!div)                                                       \
252                 return -EINVAL;                                         \
253                                                                         \
254         if (clk == &saif0_clk || clk == &saif1_clk)                     \
255                 return clk_get_rate(clk->parent) >> 16 * div;           \
256         else                                                            \
257                 return clk_get_rate(clk->parent) / div;                 \
258 }
259
260 _CLK_GET_RATE1(hbus_clk, HBUS)
261 _CLK_GET_RATE1(xbus_clk, XBUS)
262 _CLK_GET_RATE1(ssp0_clk, SSP0)
263 _CLK_GET_RATE1(ssp1_clk, SSP1)
264 _CLK_GET_RATE1(ssp2_clk, SSP2)
265 _CLK_GET_RATE1(ssp3_clk, SSP3)
266 _CLK_GET_RATE1(gpmi_clk, GPMI)
267 _CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
268 _CLK_GET_RATE1(saif0_clk, SAIF0)
269 _CLK_GET_RATE1(saif1_clk, SAIF1)
270
271 #define _CLK_GET_RATE_STUB(name)                                        \
272 static unsigned long name##_get_rate(struct clk *clk)                   \
273 {                                                                       \
274         return clk_get_rate(clk->parent);                               \
275 }
276
277 _CLK_GET_RATE_STUB(uart_clk)
278 _CLK_GET_RATE_STUB(pwm_clk)
279 _CLK_GET_RATE_STUB(can0_clk)
280 _CLK_GET_RATE_STUB(can1_clk)
281 _CLK_GET_RATE_STUB(fec_clk)
282
283 /*
284  * clk_set_rate
285  */
286 /* fool compiler */
287 #define BM_CLKCTRL_CPU_DIV      0
288 #define BP_CLKCTRL_CPU_DIV      0
289 #define BM_CLKCTRL_CPU_BUSY     0
290
291 #define _CLK_SET_RATE(name, dr, fr, fs)                                 \
292 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
293 {                                                                       \
294         u32 reg, bm_busy, div_max, d, f, div, frac;                     \
295         unsigned long diff, parent_rate, calc_rate;                     \
296         int i;                                                          \
297                                                                         \
298         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
299         bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
300                                                                         \
301         if (clk->parent == &ref_xtal_clk) {                             \
302                 parent_rate = clk_get_rate(clk->parent);                \
303                 div = DIV_ROUND_UP(parent_rate, rate);                  \
304                 if (clk == &cpu_clk) {                                  \
305                         div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
306                                 BP_CLKCTRL_CPU_DIV_XTAL;                \
307                         bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;         \
308                 }                                                       \
309                 if (div == 0 || div > div_max)                          \
310                         return -EINVAL;                                 \
311         } else {                                                        \
312                 /*                                                      \
313                  * hack alert: this block modifies clk->parent, too,    \
314                  * so the base to use it the grand parent.              \
315                  */                                                     \
316                 parent_rate = clk_get_rate(clk->parent->parent);        \
317                 rate >>= PARENT_RATE_SHIFT;                             \
318                 parent_rate >>= PARENT_RATE_SHIFT;                      \
319                 diff = parent_rate;                                     \
320                 div = frac = 1;                                         \
321                 if (clk == &cpu_clk) {                                  \
322                         div_max = BM_CLKCTRL_CPU_DIV_CPU >>             \
323                                 BP_CLKCTRL_CPU_DIV_CPU;                 \
324                         bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;          \
325                 }                                                       \
326                 for (d = 1; d <= div_max; d++) {                        \
327                         f = parent_rate * 18 / d / rate;                \
328                         if ((parent_rate * 18 / d) % rate)              \
329                                 f++;                                    \
330                         if (f < 18 || f > 35)                           \
331                                 continue;                               \
332                                                                         \
333                         calc_rate = parent_rate * 18 / f / d;           \
334                         if (calc_rate > rate)                           \
335                                 continue;                               \
336                                                                         \
337                         if (rate - calc_rate < diff) {                  \
338                                 frac = f;                               \
339                                 div = d;                                \
340                                 diff = rate - calc_rate;                \
341                         }                                               \
342                                                                         \
343                         if (diff == 0)                                  \
344                                 break;                                  \
345                 }                                                       \
346                                                                         \
347                 if (diff == parent_rate)                                \
348                         return -EINVAL;                                 \
349                                                                         \
350                 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
351                 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
352                 reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC;            \
353                 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
354         }                                                               \
355                                                                         \
356         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
357         if (clk == &cpu_clk) {                                          \
358                 reg &= ~BM_CLKCTRL_CPU_DIV_CPU;                         \
359                 reg |= div << BP_CLKCTRL_CPU_DIV_CPU;                   \
360         } else {                                                        \
361                 reg &= ~BM_CLKCTRL_##dr##_DIV;                          \
362                 reg |= div << BP_CLKCTRL_##dr##_DIV;                    \
363                 if (reg & (1 << clk->enable_shift)) {                   \
364                         pr_err("%s: clock is gated\n", __func__);       \
365                         return -EINVAL;                                 \
366                 }                                                       \
367         }                                                               \
368         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
369                                                                         \
370         for (i = 10000; i; i--)                                         \
371                 if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
372                         HW_CLKCTRL_##dr) & bm_busy))                    \
373                         break;                                          \
374         if (!i) {                                                       \
375                 pr_err("%s: divider writing timeout\n", __func__);      \
376                 return -ETIMEDOUT;                                      \
377         }                                                               \
378                                                                         \
379         return 0;                                                       \
380 }
381
382 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
383 _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
384 _CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
385 _CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
386 _CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
387 _CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
388 _CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
389
390 #define _CLK_SET_RATE1(name, dr)                                        \
391 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
392 {                                                                       \
393         u32 reg, div_max, div;                                          \
394         unsigned long parent_rate;                                      \
395         int i;                                                          \
396                                                                         \
397         parent_rate = clk_get_rate(clk->parent);                        \
398         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
399                                                                         \
400         div = DIV_ROUND_UP(parent_rate, rate);                          \
401         if (div == 0 || div > div_max)                                  \
402                 return -EINVAL;                                         \
403                                                                         \
404         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
405         reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
406         reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
407         if (reg & (1 << clk->enable_shift)) {                           \
408                 pr_err("%s: clock is gated\n", __func__);               \
409                 return -EINVAL;                                         \
410         }                                                               \
411         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
412                                                                         \
413         for (i = 10000; i; i--)                                         \
414                 if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
415                         HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
416                         break;                                          \
417         if (!i) {                                                       \
418                 pr_err("%s: divider writing timeout\n", __func__);      \
419                 return -ETIMEDOUT;                                      \
420         }                                                               \
421                                                                         \
422         return 0;                                                       \
423 }
424
425 _CLK_SET_RATE1(xbus_clk, XBUS)
426
427 /* saif clock uses 16 bits frac div */
428 #define _CLK_SET_RATE_SAIF(name, rs)                                    \
429 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
430 {                                                                       \
431         u16 div;                                                        \
432         u32 reg;                                                        \
433         u64 lrate;                                                      \
434         unsigned long parent_rate;                                      \
435         int i;                                                          \
436                                                                         \
437         parent_rate = clk_get_rate(clk->parent);                        \
438         if (rate > parent_rate)                                         \
439                 return -EINVAL;                                         \
440                                                                         \
441         lrate = (u64)rate << 16;                                        \
442         do_div(lrate, parent_rate);                                     \
443         div = (u16)lrate;                                               \
444                                                                         \
445         if (!div)                                                       \
446                 return -EINVAL;                                         \
447                                                                         \
448         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
449         reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
450         reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
451         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
452                                                                         \
453         for (i = 10000; i; i--)                                         \
454                 if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
455                         HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY))     \
456                         break;                                          \
457         if (!i) {                                                       \
458                 pr_err("%s: divider writing timeout\n", __func__);      \
459                 return -ETIMEDOUT;                                      \
460         }                                                               \
461                                                                         \
462         return 0;                                                       \
463 }
464
465 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
466 _CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
467
468 #define _CLK_SET_RATE_STUB(name)                                        \
469 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
470 {                                                                       \
471         return -EINVAL;                                                 \
472 }
473
474 _CLK_SET_RATE_STUB(emi_clk)
475 _CLK_SET_RATE_STUB(uart_clk)
476 _CLK_SET_RATE_STUB(pwm_clk)
477 _CLK_SET_RATE_STUB(spdif_clk)
478 _CLK_SET_RATE_STUB(clk32k_clk)
479 _CLK_SET_RATE_STUB(can0_clk)
480 _CLK_SET_RATE_STUB(can1_clk)
481 _CLK_SET_RATE_STUB(fec_clk)
482
483 /*
484  * clk_set_parent
485  */
486 #define _CLK_SET_PARENT(name, bit)                                      \
487 static int name##_set_parent(struct clk *clk, struct clk *parent)       \
488 {                                                                       \
489         if (parent != clk->parent) {                                    \
490                 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
491                          CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
492                 clk->parent = parent;                                   \
493         }                                                               \
494                                                                         \
495         return 0;                                                       \
496 }
497
498 _CLK_SET_PARENT(cpu_clk, CPU)
499 _CLK_SET_PARENT(emi_clk, EMI)
500 _CLK_SET_PARENT(ssp0_clk, SSP0)
501 _CLK_SET_PARENT(ssp1_clk, SSP1)
502 _CLK_SET_PARENT(ssp2_clk, SSP2)
503 _CLK_SET_PARENT(ssp3_clk, SSP3)
504 _CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
505 _CLK_SET_PARENT(gpmi_clk, GPMI)
506 _CLK_SET_PARENT(saif0_clk, SAIF0)
507 _CLK_SET_PARENT(saif1_clk, SAIF1)
508
509 #define _CLK_SET_PARENT_STUB(name)                                      \
510 static int name##_set_parent(struct clk *clk, struct clk *parent)       \
511 {                                                                       \
512         if (parent != clk->parent)                                      \
513                 return -EINVAL;                                         \
514         else                                                            \
515                 return 0;                                               \
516 }
517
518 _CLK_SET_PARENT_STUB(pwm_clk)
519 _CLK_SET_PARENT_STUB(uart_clk)
520 _CLK_SET_PARENT_STUB(clk32k_clk)
521 _CLK_SET_PARENT_STUB(spdif_clk)
522 _CLK_SET_PARENT_STUB(fec_clk)
523 _CLK_SET_PARENT_STUB(can0_clk)
524 _CLK_SET_PARENT_STUB(can1_clk)
525
526 /*
527  * clk definition
528  */
529 static struct clk cpu_clk = {
530         .get_rate = cpu_clk_get_rate,
531         .set_rate = cpu_clk_set_rate,
532         .set_parent = cpu_clk_set_parent,
533         .parent = &ref_cpu_clk,
534 };
535
536 static struct clk hbus_clk = {
537         .get_rate = hbus_clk_get_rate,
538         .parent = &cpu_clk,
539 };
540
541 static struct clk xbus_clk = {
542         .get_rate = xbus_clk_get_rate,
543         .set_rate = xbus_clk_set_rate,
544         .parent = &ref_xtal_clk,
545 };
546
547 static struct clk lradc_clk = {
548         .get_rate = lradc_clk_get_rate,
549         .parent = &clk32k_clk,
550 };
551
552 static struct clk rtc_clk = {
553         .get_rate = rtc_clk_get_rate,
554         .parent = &ref_xtal_clk,
555 };
556
557 /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
558 static struct clk usb0_clk = {
559         .enable_reg = DIGCTRL_BASE_ADDR,
560         .enable_shift = 2,
561         .enable = _raw_clk_enable,
562         .disable = _raw_clk_disable,
563         .parent = &pll0_clk,
564 };
565
566 static struct clk usb1_clk = {
567         .enable_reg = DIGCTRL_BASE_ADDR,
568         .enable_shift = 16,
569         .enable = _raw_clk_enable,
570         .disable = _raw_clk_disable,
571         .parent = &pll1_clk,
572 };
573
574 #define _DEFINE_CLOCK(name, er, es, p)                                  \
575         static struct clk name = {                                      \
576                 .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
577                 .enable_shift   = BP_CLKCTRL_##er##_##es,               \
578                 .get_rate       = name##_get_rate,                      \
579                 .set_rate       = name##_set_rate,                      \
580                 .set_parent     = name##_set_parent,                    \
581                 .enable         = _raw_clk_enable,                      \
582                 .disable        = _raw_clk_disable,                     \
583                 .parent         = p,                                    \
584         }
585
586 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
587 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
588 _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
589 _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
590 _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
591 _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
592 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
593 _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
594 _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
595 _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
596 _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
597 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
598 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
599 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
600 _DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
601 _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
602
603 #define _REGISTER_CLOCK(d, n, c) \
604         { \
605                 .dev_id = d, \
606                 .con_id = n, \
607                 .clk = &c, \
608         },
609
610 static struct clk_lookup lookups[] = {
611         /* for amba bus driver */
612         _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
613         /* for amba-pl011 driver */
614         _REGISTER_CLOCK("duart", NULL, uart_clk)
615         _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
616         _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
617         _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
618         _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
619         _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
620         _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
621         _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
622         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
623         _REGISTER_CLOCK("pll2", NULL, pll2_clk)
624         _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
625         _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
626         _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
627         _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
628         _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
629         _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
630         _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
631         _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
632         _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
633         _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
634         _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
635         _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
636         _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
637         _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
638         _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
639         _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
640         _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
641         _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
642         _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
643         _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
644         _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
645 };
646
647 static int clk_misc_init(void)
648 {
649         u32 reg;
650         int i;
651
652         /* Fix up parent per register setting */
653         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
654         cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
655                         &ref_xtal_clk : &ref_cpu_clk;
656         emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
657                         &ref_xtal_clk : &ref_emi_clk;
658         ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
659                         &ref_xtal_clk : &ref_io0_clk;
660         ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
661                         &ref_xtal_clk : &ref_io0_clk;
662         ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
663                         &ref_xtal_clk : &ref_io1_clk;
664         ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
665                         &ref_xtal_clk : &ref_io1_clk;
666         lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
667                         &ref_xtal_clk : &ref_pix_clk;
668         gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
669                         &ref_xtal_clk : &ref_gpmi_clk;
670         saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
671                         &ref_xtal_clk : &pll0_clk;
672         saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
673                         &ref_xtal_clk : &pll0_clk;
674
675         /* Use int div over frac when both are available */
676         __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
677                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
678         __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
679                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
680         __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
681                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
682
683         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
684         reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
685         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
686
687         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
688         reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
689         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
690
691         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
692         reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
693         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
694
695         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
696         reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
697         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
698
699         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
700         reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
701         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
702
703         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
704         reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
705         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
706
707         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
708         reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
709         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
710
711         /* SAIF has to use frac div for functional operation */
712         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
713         reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
714         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
715
716         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
717         reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
718         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
719
720         /*
721          * Set safe hbus clock divider. A divider of 3 ensure that
722          * the Vddd voltage required for the cpu clock is sufficiently
723          * high for the hbus clock.
724          */
725         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
726         reg &= BM_CLKCTRL_HBUS_DIV;
727         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
728         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
729
730         for (i = 10000; i; i--)
731                 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
732                         HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
733                         break;
734         if (!i) {
735                 pr_err("%s: divider writing timeout\n", __func__);
736                 return -ETIMEDOUT;
737         }
738
739         /* Gate off cpu clock in WFI for power saving */
740         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
741                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
742
743         /*
744          * Extra fec clock setting
745          * The DENX M28 uses an external clock source
746          * and the clock output must not be enabled
747          */
748         if (!machine_is_m28evk()) {
749                 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
750                 reg &= ~BM_CLKCTRL_ENET_SLEEP;
751                 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
752                 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
753         }
754
755         /*
756          * 480 MHz seems too high to be ssp clock source directly,
757          * so set frac0 to get a 288 MHz ref_io0.
758          */
759         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
760         reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
761         reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
762         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
763
764         return 0;
765 }
766
767 int __init mx28_clocks_init(void)
768 {
769         clk_misc_init();
770
771         /*
772          * source ssp clock from ref_io0 than ref_xtal,
773          * as ref_xtal only provides 24 MHz as maximum.
774          */
775         clk_set_parent(&ssp0_clk, &ref_io0_clk);
776         clk_set_parent(&ssp1_clk, &ref_io0_clk);
777
778         clk_prepare_enable(&cpu_clk);
779         clk_prepare_enable(&hbus_clk);
780         clk_prepare_enable(&xbus_clk);
781         clk_prepare_enable(&emi_clk);
782         clk_prepare_enable(&uart_clk);
783
784         clk_set_parent(&lcdif_clk, &ref_pix_clk);
785         clk_set_parent(&saif0_clk, &pll0_clk);
786         clk_set_parent(&saif1_clk, &pll0_clk);
787
788         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
789
790         mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
791
792         return 0;
793 }