misc: replace remaining __FUNCTION__ with __func__
[linux-2.6.git] / arch / arm / mach-iop13xx / include / mach / adma.h
1 /*
2  * Copyright(c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc.,
15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16  *
17  */
18 #ifndef _ADMA_H
19 #define _ADMA_H
20 #include <linux/types.h>
21 #include <linux/io.h>
22 #include <mach/hardware.h>
23 #include <asm/hardware/iop_adma.h>
24
25 #define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
26 #define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
27 #define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
28 #define ADMA_IIPCR(chan)        (chan->mmr_base + 0x18)
29 #define ADMA_IIPAR(chan)        (chan->mmr_base + 0x1c)
30 #define ADMA_IIPUAR(chan)       (chan->mmr_base + 0x20)
31 #define ADMA_ANDAR(chan)        (chan->mmr_base + 0x24)
32 #define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
33 #define ADMA_CARMD(chan)        (chan->mmr_base + 0x2c)
34 #define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
35 #define ADMA_DLADR(chan)        (chan->mmr_base + 0x34)
36 #define ADMA_DUADR(chan)        (chan->mmr_base + 0x38)
37 #define ADMA_SLAR(src, chan)    (chan->mmr_base + (0x3c + (src << 3)))
38 #define ADMA_SUAR(src, chan)    (chan->mmr_base + (0x40 + (src << 3)))
39
40 struct iop13xx_adma_src {
41         u32 src_addr;
42         union {
43                 u32 upper_src_addr;
44                 struct {
45                         unsigned int pq_upper_src_addr:24;
46                         unsigned int pq_dmlt:8;
47                 };
48         };
49 };
50
51 struct iop13xx_adma_desc_ctrl {
52         unsigned int int_en:1;
53         unsigned int xfer_dir:2;
54         unsigned int src_select:4;
55         unsigned int zero_result:1;
56         unsigned int block_fill_en:1;
57         unsigned int crc_gen_en:1;
58         unsigned int crc_xfer_dis:1;
59         unsigned int crc_seed_fetch_dis:1;
60         unsigned int status_write_back_en:1;
61         unsigned int endian_swap_en:1;
62         unsigned int reserved0:2;
63         unsigned int pq_update_xfer_en:1;
64         unsigned int dual_xor_en:1;
65         unsigned int pq_xfer_en:1;
66         unsigned int p_xfer_dis:1;
67         unsigned int reserved1:10;
68         unsigned int relax_order_en:1;
69         unsigned int no_snoop_en:1;
70 };
71
72 struct iop13xx_adma_byte_count {
73         unsigned int byte_count:24;
74         unsigned int host_if:3;
75         unsigned int reserved:2;
76         unsigned int zero_result_err_q:1;
77         unsigned int zero_result_err:1;
78         unsigned int tx_complete:1;
79 };
80
81 struct iop13xx_adma_desc_hw {
82         u32 next_desc;
83         union {
84                 u32 desc_ctrl;
85                 struct iop13xx_adma_desc_ctrl desc_ctrl_field;
86         };
87         union {
88                 u32 crc_addr;
89                 u32 block_fill_data;
90                 u32 q_dest_addr;
91         };
92         union {
93                 u32 byte_count;
94                 struct iop13xx_adma_byte_count byte_count_field;
95         };
96         union {
97                 u32 dest_addr;
98                 u32 p_dest_addr;
99         };
100         union {
101                 u32 upper_dest_addr;
102                 u32 pq_upper_dest_addr;
103         };
104         struct iop13xx_adma_src src[1];
105 };
106
107 struct iop13xx_adma_desc_dual_xor {
108         u32 next_desc;
109         u32 desc_ctrl;
110         u32 reserved;
111         u32 byte_count;
112         u32 h_dest_addr;
113         u32 h_upper_dest_addr;
114         u32 src0_addr;
115         u32 upper_src0_addr;
116         u32 src1_addr;
117         u32 upper_src1_addr;
118         u32 h_src_addr;
119         u32 h_upper_src_addr;
120         u32 d_src_addr;
121         u32 d_upper_src_addr;
122         u32 d_dest_addr;
123         u32 d_upper_dest_addr;
124 };
125
126 struct iop13xx_adma_desc_pq_update {
127         u32 next_desc;
128         u32 desc_ctrl;
129         u32 reserved;
130         u32 byte_count;
131         u32 p_dest_addr;
132         u32 p_upper_dest_addr;
133         u32 src0_addr;
134         u32 upper_src0_addr;
135         u32 src1_addr;
136         u32 upper_src1_addr;
137         u32 p_src_addr;
138         u32 p_upper_src_addr;
139         u32 q_src_addr;
140         struct {
141                 unsigned int q_upper_src_addr:24;
142                 unsigned int q_dmlt:8;
143         };
144         u32 q_dest_addr;
145         u32 q_upper_dest_addr;
146 };
147
148 static inline int iop_adma_get_max_xor(void)
149 {
150         return 16;
151 }
152
153 static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
154 {
155         return __raw_readl(ADMA_ADAR(chan));
156 }
157
158 static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
159                                                 u32 next_desc_addr)
160 {
161         __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
162 }
163
164 #define ADMA_STATUS_BUSY (1 << 13)
165
166 static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
167 {
168         if (__raw_readl(ADMA_ACSR(chan)) &
169                 ADMA_STATUS_BUSY)
170                 return 1;
171         else
172                 return 0;
173 }
174
175 static inline int
176 iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
177 {
178         return 1;
179 }
180 #define iop_desc_is_aligned(x, y) 1
181
182 static inline int
183 iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
184 {
185         *slots_per_op = 1;
186         return 1;
187 }
188
189 #define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
190
191 static inline int
192 iop_chan_memset_slot_count(size_t len, int *slots_per_op)
193 {
194         *slots_per_op = 1;
195         return 1;
196 }
197
198 static inline int
199 iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
200 {
201         static const char slot_count_table[] = { 1, 2, 2, 2,
202                                                  2, 3, 3, 3,
203                                                  3, 4, 4, 4,
204                                                  4, 5, 5, 5,
205                                                 };
206         *slots_per_op = slot_count_table[src_cnt - 1];
207         return *slots_per_op;
208 }
209
210 #define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
211 #define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
212 #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
213 #define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
214 #define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
215
216 static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
217                                         struct iop_adma_chan *chan)
218 {
219         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
220         return hw_desc->dest_addr;
221 }
222
223 static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
224                                         struct iop_adma_chan *chan)
225 {
226         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
227         return hw_desc->byte_count_field.byte_count;
228 }
229
230 static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
231                                         struct iop_adma_chan *chan,
232                                         int src_idx)
233 {
234         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
235         return hw_desc->src[src_idx].src_addr;
236 }
237
238 static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
239                                         struct iop_adma_chan *chan)
240 {
241         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
242         return hw_desc->desc_ctrl_field.src_select + 1;
243 }
244
245 static inline void
246 iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
247 {
248         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
249         union {
250                 u32 value;
251                 struct iop13xx_adma_desc_ctrl field;
252         } u_desc_ctrl;
253
254         u_desc_ctrl.value = 0;
255         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
256         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
257         hw_desc->desc_ctrl = u_desc_ctrl.value;
258         hw_desc->crc_addr = 0;
259 }
260
261 static inline void
262 iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
263 {
264         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
265         union {
266                 u32 value;
267                 struct iop13xx_adma_desc_ctrl field;
268         } u_desc_ctrl;
269
270         u_desc_ctrl.value = 0;
271         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
272         u_desc_ctrl.field.block_fill_en = 1;
273         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
274         hw_desc->desc_ctrl = u_desc_ctrl.value;
275         hw_desc->crc_addr = 0;
276 }
277
278 /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
279 static inline void
280 iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
281                   unsigned long flags)
282 {
283         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
284         union {
285                 u32 value;
286                 struct iop13xx_adma_desc_ctrl field;
287         } u_desc_ctrl;
288
289         u_desc_ctrl.value = 0;
290         u_desc_ctrl.field.src_select = src_cnt - 1;
291         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
292         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
293         hw_desc->desc_ctrl = u_desc_ctrl.value;
294         hw_desc->crc_addr = 0;
295
296 }
297 #define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
298
299 /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
300 static inline int
301 iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
302                        unsigned long flags)
303 {
304         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
305         union {
306                 u32 value;
307                 struct iop13xx_adma_desc_ctrl field;
308         } u_desc_ctrl;
309
310         u_desc_ctrl.value = 0;
311         u_desc_ctrl.field.src_select = src_cnt - 1;
312         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
313         u_desc_ctrl.field.zero_result = 1;
314         u_desc_ctrl.field.status_write_back_en = 1;
315         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
316         hw_desc->desc_ctrl = u_desc_ctrl.value;
317         hw_desc->crc_addr = 0;
318
319         return 1;
320 }
321
322 static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
323                                         struct iop_adma_chan *chan,
324                                         u32 byte_count)
325 {
326         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
327         hw_desc->byte_count = byte_count;
328 }
329
330 static inline void
331 iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
332 {
333         int slots_per_op = desc->slots_per_op;
334         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
335         int i = 0;
336
337         if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
338                 hw_desc->byte_count = len;
339         } else {
340                 do {
341                         iter = iop_hw_desc_slot_idx(hw_desc, i);
342                         iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
343                         len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
344                         i += slots_per_op;
345                 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
346
347                 if (len) {
348                         iter = iop_hw_desc_slot_idx(hw_desc, i);
349                         iter->byte_count = len;
350                 }
351         }
352 }
353
354
355 static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
356                                         struct iop_adma_chan *chan,
357                                         dma_addr_t addr)
358 {
359         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
360         hw_desc->dest_addr = addr;
361         hw_desc->upper_dest_addr = 0;
362 }
363
364 static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
365                                         dma_addr_t addr)
366 {
367         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
368         hw_desc->src[0].src_addr = addr;
369         hw_desc->src[0].upper_src_addr = 0;
370 }
371
372 static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
373                                         int src_idx, dma_addr_t addr)
374 {
375         int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
376         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
377         int i = 0;
378
379         do {
380                 iter = iop_hw_desc_slot_idx(hw_desc, i);
381                 iter->src[src_idx].src_addr = addr;
382                 iter->src[src_idx].upper_src_addr = 0;
383                 slot_cnt -= slots_per_op;
384                 if (slot_cnt) {
385                         i += slots_per_op;
386                         addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
387                 }
388         } while (slot_cnt);
389 }
390
391 static inline void
392 iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
393         struct iop_adma_chan *chan)
394 {
395         iop_desc_init_memcpy(desc, 1);
396         iop_desc_set_byte_count(desc, chan, 0);
397         iop_desc_set_dest_addr(desc, chan, 0);
398         iop_desc_set_memcpy_src_addr(desc, 0);
399 }
400
401 #define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
402
403 static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
404                                         u32 next_desc_addr)
405 {
406         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
407         BUG_ON(hw_desc->next_desc);
408         hw_desc->next_desc = next_desc_addr;
409 }
410
411 static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
412 {
413         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
414         return hw_desc->next_desc;
415 }
416
417 static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
418 {
419         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
420         hw_desc->next_desc = 0;
421 }
422
423 static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
424                                                 u32 val)
425 {
426         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
427         hw_desc->block_fill_data = val;
428 }
429
430 static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
431 {
432         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
433         struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
434         struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
435
436         BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
437
438         if (desc_ctrl.pq_xfer_en)
439                 return byte_count.zero_result_err_q;
440         else
441                 return byte_count.zero_result_err;
442 }
443
444 static inline void iop_chan_append(struct iop_adma_chan *chan)
445 {
446         u32 adma_accr;
447
448         adma_accr = __raw_readl(ADMA_ACCR(chan));
449         adma_accr |= 0x2;
450         __raw_writel(adma_accr, ADMA_ACCR(chan));
451 }
452
453 static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
454 {
455         return __raw_readl(ADMA_ACSR(chan));
456 }
457
458 static inline void iop_chan_disable(struct iop_adma_chan *chan)
459 {
460         u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
461         adma_chan_ctrl &= ~0x1;
462         __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
463 }
464
465 static inline void iop_chan_enable(struct iop_adma_chan *chan)
466 {
467         u32 adma_chan_ctrl;
468
469         adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
470         adma_chan_ctrl |= 0x1;
471         __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
472 }
473
474 static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
475 {
476         u32 status = __raw_readl(ADMA_ACSR(chan));
477         status &= (1 << 12);
478         __raw_writel(status, ADMA_ACSR(chan));
479 }
480
481 static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
482 {
483         u32 status = __raw_readl(ADMA_ACSR(chan));
484         status &= (1 << 11);
485         __raw_writel(status, ADMA_ACSR(chan));
486 }
487
488 static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
489 {
490         u32 status = __raw_readl(ADMA_ACSR(chan));
491         status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
492         __raw_writel(status, ADMA_ACSR(chan));
493 }
494
495 static inline int
496 iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
497 {
498         return test_bit(9, &status);
499 }
500
501 static inline int
502 iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
503 {
504         return test_bit(5, &status);
505 }
506
507 static inline int
508 iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
509 {
510         return test_bit(4, &status);
511 }
512
513 static inline int
514 iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
515 {
516         return test_bit(3, &status);
517 }
518
519 static inline int
520 iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
521 {
522         return 0;
523 }
524
525 static inline int
526 iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
527 {
528         return 0;
529 }
530
531 static inline int
532 iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
533 {
534         return 0;
535 }
536
537 #endif /* _ADMA_H */