c48cb1e1c46cd02a536e83a9a1acb49b439fa531
[linux-2.6.git] / arch / arm / include / asm / hardware / cache-l2x0.h
1 /*
2  * arch/arm/include/asm/hardware/cache-l2x0.h
3  *
4  * Copyright (C) 2007 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19
20 #ifndef __ASM_ARM_HARDWARE_L2X0_H
21 #define __ASM_ARM_HARDWARE_L2X0_H
22
23 #define L2X0_CACHE_ID                   0x000
24 #define L2X0_CACHE_TYPE                 0x004
25 #define L2X0_CTRL                       0x100
26 #define L2X0_AUX_CTRL                   0x104
27 #define L2X0_TAG_LATENCY_CTRL           0x108
28 #define L2X0_DATA_LATENCY_CTRL          0x10C
29 #define L2X0_EVENT_CNT_CTRL             0x200
30 #define L2X0_EVENT_CNT1_CFG             0x204
31 #define L2X0_EVENT_CNT0_CFG             0x208
32 #define L2X0_EVENT_CNT1_VAL             0x20C
33 #define L2X0_EVENT_CNT0_VAL             0x210
34 #define L2X0_INTR_MASK                  0x214
35 #define L2X0_MASKED_INTR_STAT           0x218
36 #define L2X0_RAW_INTR_STAT              0x21C
37 #define L2X0_INTR_CLEAR                 0x220
38 #define L2X0_CACHE_SYNC                 0x730
39 #define L2X0_DUMMY_REG                  0x740
40 #define L2X0_INV_LINE_PA                0x770
41 #define L2X0_INV_WAY                    0x77C
42 #define L2X0_CLEAN_LINE_PA              0x7B0
43 #define L2X0_CLEAN_LINE_IDX             0x7B8
44 #define L2X0_CLEAN_WAY                  0x7BC
45 #define L2X0_CLEAN_INV_LINE_PA          0x7F0
46 #define L2X0_CLEAN_INV_LINE_IDX         0x7F8
47 #define L2X0_CLEAN_INV_WAY              0x7FC
48 /*
49  * The lockdown registers repeat 8 times for L310, the L210 has only one
50  * D and one I lockdown register at 0x0900 and 0x0904.
51  */
52 #define L2X0_LOCKDOWN_WAY_D_BASE        0x900
53 #define L2X0_LOCKDOWN_WAY_I_BASE        0x904
54 #define L2X0_LOCKDOWN_STRIDE            0x08
55 #define L2X0_ADDR_FILTER_START          0xC00
56 #define L2X0_ADDR_FILTER_END            0xC04
57 #define L2X0_TEST_OPERATION             0xF00
58 #define L2X0_LINE_DATA                  0xF10
59 #define L2X0_LINE_TAG                   0xF30
60 #define L2X0_DEBUG_CTRL                 0xF40
61 #define L2X0_PREFETCH_CTRL              0xF60
62 #define L2X0_POWER_CTRL                 0xF80
63 #define   L2X0_DYNAMIC_CLK_GATING_EN    (1 << 1)
64 #define   L2X0_STNDBY_MODE_EN           (1 << 0)
65
66 /* Registers shifts and masks */
67 #define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
68 #define L2X0_CACHE_ID_PART_L210         (1 << 6)
69 #define L2X0_CACHE_ID_PART_L310         (3 << 6)
70
71 #define L2X0_AUX_CTRL_MASK                      0xc0000fff
72 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT     0
73 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK      0x7
74 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT     3
75 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK      (0x7 << 3)
76 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT         6
77 #define L2X0_AUX_CTRL_TAG_LATENCY_MASK          (0x7 << 6)
78 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT       9
79 #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK        (0x7 << 9)
80 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT       16
81 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT            17
82 #define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x7 << 17)
83 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT      22
84 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT         26
85 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT         27
86 #define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT       28
87 #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT      29
88 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT         30
89
90 #define L2X0_LATENCY_CTRL_SETUP_SHIFT   0
91 #define L2X0_LATENCY_CTRL_RD_SHIFT      4
92 #define L2X0_LATENCY_CTRL_WR_SHIFT      8
93
94 #define L2X0_ADDR_FILTER_EN             1
95
96 #ifndef __ASSEMBLY__
97 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
98 extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
99 #endif
100
101 #endif