1 Asynchronous Transfers/Transforms API
8 3.1 General format of the API
9 3.2 Supported operations
10 3.3 Descriptor management
11 3.4 When does the operation execute?
12 3.5 When does the operation complete?
16 4 DMAENGINE DRIVER DEVELOPER NOTES
17 4.1 Conformance points
18 4.2 "My application needs exclusive control of hardware channels"
26 The async_tx API provides methods for describing a chain of asynchronous
27 bulk memory transfers/transforms with support for inter-transactional
28 dependencies. It is implemented as a dmaengine client that smooths over
29 the details of different hardware offload engine implementations. Code
30 that is written to the API can optimize for asynchronous operation and
31 the API will fit the chain of operations to the available offload
36 The API was initially designed to offload the memory copy and
37 xor-parity-calculations of the md-raid5 driver using the offload engines
38 present in the Intel(R) Xscale series of I/O processors. It also built
39 on the 'dmaengine' layer developed for offloading memory copies in the
40 network stack using Intel(R) I/OAT engines. The following design
41 features surfaced as a result:
42 1/ implicit synchronous path: users of the API do not need to know if
43 the platform they are running on has offload capabilities. The
44 operation will be offloaded when an engine is available and carried out
45 in software otherwise.
46 2/ cross channel dependency chains: the API allows a chain of dependent
47 operations to be submitted, like xor->copy->xor in the raid5 case. The
48 API automatically handles cases where the transition from one operation
49 to another implies a hardware channel switch.
50 3/ dmaengine extensions to support multiple clients and operation types
55 3.1 General format of the API:
56 struct dma_async_tx_descriptor *
57 async_<operation>(<op specific parameters>, struct async_submit ctl *submit)
59 3.2 Supported operations:
60 memcpy - memory copy between a source and a destination buffer
61 memset - fill a destination buffer with a byte value
62 xor - xor a series of source buffers and write the result to a
64 xor_val - xor a series of source buffers and set a flag if the
65 result is zero. The implementation attempts to prevent
67 pq - generate the p+q (raid6 syndrome) from a series of source buffers
68 pq_val - validate that a p and or q buffer are in sync with a given series of
71 3.3 Descriptor management:
72 The return value is non-NULL and points to a 'descriptor' when the operation
73 has been queued to execute asynchronously. Descriptors are recycled
74 resources, under control of the offload engine driver, to be reused as
75 operations complete. When an application needs to submit a chain of
76 operations it must guarantee that the descriptor is not automatically recycled
77 before the dependency is submitted. This requires that all descriptors be
78 acknowledged by the application before the offload engine driver is allowed to
79 recycle (or free) the descriptor. A descriptor can be acked by one of the
81 1/ setting the ASYNC_TX_ACK flag if no child operations are to be submitted
82 2/ submitting an unacknowledged descriptor as a dependency to another
83 async_tx call will implicitly set the acknowledged state.
84 3/ calling async_tx_ack() on the descriptor.
86 3.4 When does the operation execute?
87 Operations do not immediately issue after return from the
88 async_<operation> call. Offload engine drivers batch operations to
89 improve performance by reducing the number of mmio cycles needed to
90 manage the channel. Once a driver-specific threshold is met the driver
91 automatically issues pending operations. An application can force this
92 event by calling async_tx_issue_pending_all(). This operates on all
93 channels since the application has no knowledge of channel to operation
96 3.5 When does the operation complete?
97 There are two methods for an application to learn about the completion
99 1/ Call dma_wait_for_async_tx(). This call causes the CPU to spin while
100 it polls for the completion of the operation. It handles dependency
101 chains and issuing pending operations.
102 2/ Specify a completion callback. The callback routine runs in tasklet
103 context if the offload engine driver supports interrupts, or it is
104 called in application context if the operation is carried out
105 synchronously in software. The callback can be set in the call to
106 async_<operation>, or when the application needs to submit a chain of
107 unknown length it can use the async_trigger_callback() routine to set a
108 completion interrupt/callback at the end of the chain.
111 1/ Calls to async_<operation> are not permitted in IRQ context. Other
112 contexts are permitted provided constraint #2 is not violated.
113 2/ Completion callback routines cannot submit new operations. This
114 results in recursion in the synchronous case and spin_locks being
115 acquired twice in the asynchronous case.
118 Perform a xor->copy->xor operation where each operation depends on the
119 result from the previous operation:
121 void callback(void *param)
123 struct completion *cmp = param;
128 void run_xor_copy_xor(struct page **xor_srcs,
130 struct page *xor_dest,
132 struct page *copy_src,
133 struct page *copy_dest,
136 struct dma_async_tx_descriptor *tx;
137 addr_conv_t addr_conv[xor_src_cnt];
138 struct async_submit_ctl submit;
139 addr_conv_t addr_conv[NDISKS];
140 struct completion cmp;
142 init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL,
144 tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit)
146 submit->depend_tx = tx;
147 tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit);
149 init_completion(&cmp);
150 init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx,
151 callback, &cmp, addr_conv);
152 tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit);
154 async_tx_issue_pending_all();
156 wait_for_completion(&cmp);
159 See include/linux/async_tx.h for more information on the flags. See the
160 ops_run_* and ops_complete_* routines in drivers/md/raid5.c for more
161 implementation examples.
163 4 DRIVER DEVELOPMENT NOTES
165 4.1 Conformance points:
166 There are a few conformance points required in dmaengine drivers to
167 accommodate assumptions made by applications using the async_tx API:
168 1/ Completion callbacks are expected to happen in tasklet context
169 2/ dma_async_tx_descriptor fields are never manipulated in IRQ context
170 3/ Use async_tx_run_dependencies() in the descriptor clean up path to
171 handle submission of dependent operations
173 4.2 "My application needs exclusive control of hardware channels"
174 Primarily this requirement arises from cases where a DMA engine driver
175 is being used to support device-to-memory operations. A channel that is
176 performing these operations cannot, for many platform specific reasons,
177 be shared. For these cases the dma_request_channel() interface is
181 struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
182 dma_filter_fn filter_fn,
185 Where dma_filter_fn is defined as:
186 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
188 When the optional 'filter_fn' parameter is set to NULL
189 dma_request_channel simply returns the first channel that satisfies the
190 capability mask. Otherwise, when the mask parameter is insufficient for
191 specifying the necessary channel, the filter_fn routine can be used to
192 disposition the available channels in the system. The filter_fn routine
193 is called once for each free channel in the system. Upon seeing a
194 suitable channel filter_fn returns DMA_ACK which flags that channel to
195 be the return value from dma_request_channel. A channel allocated via
196 this interface is exclusive to the caller, until dma_release_channel()
199 The DMA_PRIVATE capability flag is used to tag dma devices that should
200 not be used by the general-purpose allocator. It can be set at
201 initialization time if it is known that a channel will always be
202 private. Alternatively, it is set when dma_request_channel() finds an
203 unused "public" channel.
205 A couple caveats to note when implementing a driver and consumer:
206 1/ Once a channel has been privately allocated it will no longer be
207 considered by the general-purpose allocator even after a call to
208 dma_release_channel().
209 2/ Since capabilities are specified at the device level a dma_device
210 with multiple channels will either have all channels public, or all
215 include/linux/dmaengine.h: core header file for DMA drivers and api users
216 drivers/dma/dmaengine.c: offload engine channel management routines
217 drivers/dma/: location for offload engine drivers
218 include/linux/async_tx.h: core header file for the async_tx api
219 crypto/async_tx/async_tx.c: async_tx interface to dmaengine and common code
220 crypto/async_tx/async_memcpy.c: copy offload
221 crypto/async_tx/async_memset.c: memory fill offload
222 crypto/async_tx/async_xor.c: xor and xor zero sum offload