6 years agoARM: tegra: t12x: add SATA support in T124
venkatajagadish [Thu, 25 Jul 2013 06:08:40 +0000]
ARM: tegra: t12x: add SATA support in T124

Bug 1246727
Bug 1249588

Change-Id: If615946cd3dc51b1071c73ecbf6748ffc9ad7c21
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/253237
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Chetan Hooli <chooli@nvidia.com>
Tested-by: Chetan Hooli <chooli@nvidia.com>

6 years agoARM: tegra: t124: add SATA support
venkatajagadish [Thu, 25 Jul 2013 06:05:13 +0000]
ARM: tegra: t124: add SATA support

Register sata device for tegra 124 boards

Bug 1246727
Bug 1249588

Change-Id: I07c2b035171bfcebe888412e29edef65d92acd23
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/253236
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: uncompress: detect FPGA at runtime
Jeff Smith [Thu, 10 Jan 2013 08:25:44 +0000]
arm: tegra: uncompress: detect FPGA at runtime

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ic3126a3e436fcc3971a379fc0ce0bb8a0a4bf3b3
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252558
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra: macallan: update edp estates
Charlie Huang [Tue, 18 Jun 2013 18:47:05 +0000]
ARM: tegra: macallan: update edp estates

to enable edp support on the as3648 flash device.

ported from http://git-master/r/#change,236031, which was submitted
already but cannot be simply cherry picked due to other differences.

bug 1299134

Change-Id: I2bad97db30cbd56caa8a450f40e5c260eca74c76
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/239841
(cherry picked from commit 1845e4d9bd3886b67f927b4582c33fe63408a209)
Reviewed-on: http://git-master/r/250878
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>

6 years agovideo: tegra: gk20a: support thermal throttling
Hyungwoo Yang [Thu, 1 Aug 2013 17:20:52 +0000]
video: tegra: gk20a: support thermal throttling

Add functions supporting thermal throttling

gk20a_clk_get_max() which returns the max frequency that GPU supports
gk20a_clk_get_cap_thermal() which returns GPU cap freq from thermal throttling
gk20a_clk_set_cap_thermal() which sets GPU cap freq from thermal throttling

Bug 1315460

Change-Id: Ic0460a658a40c5664de01738924731ae1f867e5e
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/256925
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: Update emc dvfs in clock resume
Alex Frid [Thu, 13 Jun 2013 05:28:16 +0000]
ARM: tegra11: clock: Update emc dvfs in clock resume

Added emc dvfs update in clock resume in case when emc parent has been
changed across suspend (this update would also happen automatically
during resume of any driver with emc shared user, so this change is
"just in case" there is no driver that resumes emc shared users).

Change-Id: I4d4cf8092df52752c2f574e100b7128387dfad13
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238333
(cherry picked from commit 478e56f18b9ff058f06c81dc8f70f5fa5c72a4ed)
Reviewed-on: http://git-master/r/240862
(cherry picked from commit a6e5077f40146a9325c91c7c21ae43b624190afa)
Reviewed-on: http://git-master/r/260243
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: clock: Restore CPU clock source after LP1
Alex Frid [Fri, 21 Jun 2013 06:57:12 +0000]
ARM: tegra: clock: Restore CPU clock source after LP1

Restore CPU clock source after LP1 early - before CPU context (before
this commit CPU run on oscillator until clock resume syscore call).

Bug 1292094

Change-Id: Ida0d92f4744578e0fd6b32edacff109ae6bff42b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241176
(cherry picked from commit 5d7e97404d356ac6714dcf42a6e8361e72015375)

Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: Ic6322d8e0950f6f93aa719eebce8f76e444721ba
Reviewed-on: http://git-master/r/260242
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra114: tegra148: Remove the wrong EMC_REFRESH write.
Bo Yan [Thu, 6 Jun 2013 23:31:46 +0000]
ARM: tegra114: tegra148: Remove the wrong EMC_REFRESH write.

'1' is written into EMC_REFRESH in SDRAM self-refresh exit sequence.
This is wrong. Remove it.

bug 1270351

Change-Id: I0180f5d36e5605f3c91905cdde4149a9b01b453a
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/236471
(cherry picked from commit ae3635ce3f0123988d6bcd7ebedb6c7d9295d90e)
Reviewed-on: http://git-master/r/241175
(cherry picked from commit ea132d04a9098fe3687c7e88df11358e3359fb2a)
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/260241
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Update T40DC Vmin in PLL mode
Alex Frid [Sun, 16 Jun 2013 06:32:42 +0000]
ARM: tegra11: dvfs: Update T40DC Vmin in PLL mode

Minimum voltage in PLL mode for T40DC sku is different (0.9V4) from
other skus (0.9V) that share the same cpu dvfs tables. Updated T40DC
Vmin respectively.

Bug 1161126

Change-Id: Ibea2c32bbfa2dd44256d2a344aca4a3b852e17e7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239141
(cherry picked from commit e0a0856921e0edd399007e9e1406a229dbf1a46a)
Reviewed-on: http://git-master/r/241234
(cherry picked from commit 2510c077b060bd23bb8a136c8581207dca376422)
Reviewed-on: http://git-master/r/260236
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: power: Update core edp error reporting
Alex Frid [Fri, 7 Jun 2013 02:52:40 +0000]
ARM: tegra11: power: Update core edp error reporting

Bug 1200217

Change-Id: Ib4057f921651b4aa7cc17c073088bd9f98d53384
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/236557
(cherry picked from commit 95e99aab993d05c477a567dae7670a89b953377c)
Reviewed-on: http://git-master/r/240859
(cherry picked from commit 1a47ac5c95867eff8b313acb3530e5218c66df14)
Reviewed-on: http://git-master/r/260235
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: power: Add AP40 core edp tables
Alex Frid [Fri, 7 Jun 2013 02:26:17 +0000]
ARM: tegra11: power: Add AP40 core edp tables

Bug 1200217

Change-Id: Ib68414030e932d75ba4275aec19ceff34e90329d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/236556
(cherry picked from commit 04e884cd66dbba374b9fceccfaab513239b42dbe)
Reviewed-on: http://git-master/r/240858
(cherry picked from commit 83bb0996a1ea2d5f24dd30dcdf067bbfbe2daea6)
Reviewed-on: http://git-master/r/260234
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: power: Add T40S core edp tables
Alex Frid [Fri, 7 Jun 2013 02:10:58 +0000]
ARM: tegra11: power: Add T40S core edp tables

Bug 1200217

Change-Id: Ia4b38122fb1e52ef01e41c117be1db431b178dad
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/236555
(cherry picked from commit fdaf92c9e94d9508d3775a58a5e156f8a9366a22)
Reviewed-on: http://git-master/r/240857
(cherry picked from commit 6c88f504f3c3452be02efda0de1c642b470f873e)
Reviewed-on: http://git-master/r/260233
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: power: Update T40X core edp tables
Alex Frid [Wed, 5 Jun 2013 06:35:51 +0000]
ARM: tegra11: power: Update T40X core edp tables

Bug 1200217

Change-Id: I8e19fd426538f853293fd392e69f3ac2d3189ba6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/236554
(cherry picked from commit b36a38668735c273c371840680cfbda4c9022fee)
Reviewed-on: http://git-master/r/240856
(cherry picked from commit 2c797e703d332808be601fc82a9a96087894b6dd)
Reviewed-on: http://git-master/r/260232
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: power: Use process id to select core edp table
Alex Frid [Wed, 5 Jun 2013 06:09:53 +0000]
ARM: tegra11: power: Use process id to select core edp table

Bug 1200217

Change-Id: Icb6ab1ac7d2fa5bd8fb63bafa337d1493488e6c0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/236553
(cherry picked from commit a80843eca98c524ccc4d7a363389e7feafa2a009)
Reviewed-on: http://git-master/r/240855
(cherry picked from commit 2c35ae96df457922227df18da7baa0cbc9e414aa)
Reviewed-on: http://git-master/r/260231
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: dvfs: Enable DFLL/PLL auto-switch by default
Alex Frid [Sat, 18 May 2013 00:55:38 +0000]
ARM: tegra11: dvfs: Enable DFLL/PLL auto-switch by default

Bug 1291764

Change-Id: Idab2e02b60fee56a2af2b11c9121af2ca6b15dda
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/230032
(cherry picked from commit 23e6ff0a2bccc1c3f9e9c6ffe6de6124ebc8411f)
Reviewed-on: http://git-master/r/240017
(cherry picked from commit fc88ed35c6df5b31a5620901b53773e110850b2b)
Reviewed-on: http://git-master/r/260230
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: dvfs: Update DFLL calibration
Alex Frid [Tue, 18 Jun 2013 02:01:27 +0000]
ARM: tegra: dvfs: Update DFLL calibration

- Increased upper band for DVCO minimum rate calibration in DFLL mode
(tripled it from 8 CL-DVFS rate steps /~200MHz to 24 steps /~600MHz).
Removed restriction of one step per sample for calibration upwards.
These changes together allow jump up to the measured rate in a single
calibration sample.

- Prevented calibration down below minimum rate in safe dvfs table.
Kept one step per sample restriction for calibration down intact.

- When DFLL voltage floor is changes with temperature used last
calibrated at that temperature DVCO minimum rate to start calibration
again (instead of starting from rate estimate based on safe dvfs
table).

Change-Id: I28002d7884c14a30a5142dfd5553ac7c2d7e18ca
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239976
(cherry picked from commit 02c63bade6873820ed180e70789d4f64ca7f6793)
Reviewed-on: http://git-master/r/260229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoiommu/tegra: smmu: Disable SDMMC ordered
Hiroshi Doyu [Fri, 9 Aug 2013 07:54:16 +0000]
iommu/tegra: smmu: Disable SDMMC ordered

SDMMC controller doesn't need to ORDERED client of SMMU otherwise
there is the possible expense of perf hit. SDMMC controller indicates
the status bit after the read/writes from/to DRAM are acked by MC,
There is no need to enable ORDRED for SDMMC. The framework itself is
left for the later use.

Bug 1338987

Change-Id: I7b90ccec5b9bc5dc9e76657205bf1fda0cc0863f
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/259994
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Skip "No map" for tegra_smmu
Hiroshi Doyu [Wed, 7 Aug 2013 12:50:10 +0000]
iommu/tegra: smmu: Skip "No map" for tegra_smmu

No need this message for SMMU device itself.

Bug 1321436

Change-Id: Ia12508285b529dcbaac7eabbbecddf2cf31a0e87
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/259220
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoxhci: tegra: fix a race during usb2 remote wakeup
Henry Lin [Fri, 12 Jul 2013 03:36:55 +0000]
xhci: tegra: fix a race during usb2 remote wakeup

For usb2 devices, a race condition between remote and host wake was
observed during remote wake from LP0. If usb2 remote wake's port status
change event interrupt happens while the hub driver is resuming the same
usb2 port for host wake, the hub driver may disconnect the usb2 port
and cause the resuming_ports flag for usb2 remote wake not cleared properly.
Then, the system cannot go to LP0 with "xhci_bus_suspend failed -16"
error message.

This patch fix the race by letting remote wake being completed
before hub driver performs host resume for usb2 port.

Bug 1318548

Change-Id: I59c032527f9adf02a6e4f589f022033940b1d494
Reviewed-on: http://git-master/r/248179
(cherry picked from commit 93eb2637dae56488d6e3dc980c04f0020239b3be)
Signed-off-by: Henry Lin <henryl@nvidia.com>
Reviewed-on: http://git-master/r/259063
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: laguna: Remove mpu9250 register from PM363
Hayden Du [Tue, 6 Aug 2013 08:15:20 +0000]
arm: tegra: laguna: Remove mpu9250 register from PM363

Change-Id: I4a180f2cdd31f33186163faaddfb5fcb5586e9c4
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/258619
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm:tegra14: keep PLL-C ON if needed on voice call
Greg Heinrich [Thu, 25 Jul 2013 08:09:13 +0000]
arm:tegra14: keep PLL-C ON if needed on voice call

The LP1BB entry logic that checks the EMC source to determine
if PLL-C must be ON in LP1BB must also apply to the case when
there is an ongoing voice call. Failing to do so results in
PLL-C being cut unconditionally, which may result in baseband
crashes.

bug 1331131

Change-Id: Iee416b3f1f1e030ae3f578f216ea372827271c94
Signed-off-by: Greg Heinrich <gheinrich@nvidia.com>
Reviewed-on: http://git-master/r/253280
(cherry picked from commit f69519fcaff3a615335f2630620d8ec3b8f22d49)
Reviewed-on: http://git-master/r/258607
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Configurable flush_all debugfs
Hiroshi Doyu [Mon, 5 Aug 2013 07:28:59 +0000]
iommu/tegra: smmu: Configurable flush_all debugfs

Set PTC/TLB flush all parameter as configurable. By default it's 512 pages.

Bug 1338987

Change-Id: I8dc4f85952d20969ec584e840b48a86981b70adf
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258581
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Fix flush_all TH for map_sg
Hiroshi Doyu [Mon, 5 Aug 2013 07:15:26 +0000]
iommu/tegra: smmu: Fix flush_all TH for map_sg

Unit of flush_all threshold is number of pages. This would
improve some throughput performance.

Bug 1338987

Change-Id: I77fd8a8a4d9294a70be056636bde8287f70f3e71
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258580
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Fix PTC flush size for T124
Hiroshi Doyu [Wed, 31 Jul 2013 10:14:41 +0000]
iommu/tegra: smmu: Fix PTC flush size for T124

Fix PTC flush unit size from 16KB to 32KB for T124.

Bug 1338987

Change-Id: I9cb3e084d26b254d15e42cf7fabe3b770d54e2b3
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258579
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Fix refcount for L2 table
Hiroshi Doyu [Wed, 31 Jul 2013 07:25:07 +0000]
iommu/tegra: smmu: Fix refcount for L2 table

With CONFIG_TEGRA_IOMMU_SMMU_LINEAR enable, l2 pagetable refcount is
incorret. This patch fixes this refcount. Without
CONFIG_TEGRA_IOMMU_SMMU_LINEAR, no problem, though.

Bug 1338987

Change-Id: Ieb749a694b19952e57e8f2acce4ea574af69e496
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258578
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Preserve asid_securiy for T124
Hiroshi Doyu [Tue, 30 Jul 2013 11:44:05 +0000]
iommu/tegra: smmu: Preserve asid_securiy for T124

T124 has more asid_securiy than the previous Tegra SoC.

Bug 1338987

Change-Id: I7f1eaa4ba317acf79e3a5aa9ec2d24263e448cfd
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258577
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Fix translation_enable per SoC
Hiroshi Doyu [Mon, 1 Jul 2013 05:51:40 +0000]
iommu/tegra: smmu: Fix translation_enable per SoC

Only T124 uses 4th translation_enable.

Bug 1338987
Bug 1320358
Bug 1315906

Change-Id: Id87d81f9e1fa05e0ecbdc62f251d766d257e4d15
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258576
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Move readback after loop
Hiroshi Doyu [Tue, 30 Jul 2013 11:03:47 +0000]
iommu/tegra: smmu: Move readback after loop

micro optimization, move SMMU register readback after loop.

With the prefix "__", the PTC/TLB accessors doesn't include the SMMU
register readback, and the caller is expected to call the SMMU
register readback by itself.

Bug 1338987

Change-Id: I7de35a58227cb2996b598ab9d8b2c91f8f7cc117
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258575
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoiommu/tegra: smmu: Map linear at attach
Hiroshi Doyu [Tue, 6 Aug 2013 08:25:15 +0000]
iommu/tegra: smmu: Map linear at attach

Support to map linear mapping at attach if any. This would set up a
linear mapping when H/W is configured IOMMU'able without any gap, and
would allow H/W continue to access older mapping(linear).

Bug 1297607

Change-Id: I96caa8b4e2af9ee0861f7c8eccf94b8ad64a23ac
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/258190
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: add GPU frequency capping
Hyungwoo Yang [Thu, 1 Aug 2013 19:19:40 +0000]
ARM: tegra: add GPU frequency capping

add GPU frequency capping into balanced cooling device

In this chagne, GPU frequency capping is done by directly using gk20a driver.
This part will be removed when GPU clock tree is available in Linux Clock
Framework.

Bug 1315460

Change-Id: Ia6927eb3522875417d5a081d98f0ddde4927cfab
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/256975
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: tegra12: clock: add cap clocks for thermal throttling
Hyungwoo Yang [Thu, 1 Aug 2013 18:54:53 +0000]
ARM: tegra12: clock: add cap clocks for thermal throttling

Add clocks for capping frequencies while thermal throttling.

Bug 1315460

Change-Id: I1942226f00a6ff4c7bcdd0a04b5d57395d169f5e
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/256962
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agousb: xhci: tegra: use dma_map_linear_attrs
Ajay Gupta [Fri, 9 Aug 2013 21:47:01 +0000]
usb: xhci: tegra: use dma_map_linear_attrs

Bug 1345518

Change-Id: I2ed920e553666a143db267bda6b563cd8b1376e3
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/260151
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: remove t114 simulation platform support
Bo Yan [Wed, 7 Aug 2013 21:59:12 +0000]
ARM: tegra: remove t114 simulation platform support

This is no longer needed.

Change-Id: I8b5f70ed9437875f7665edcb495c8c307a71212e
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/259328
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: dalmore: clear fb if bl fb not defined.
Jong Kim [Mon, 1 Jul 2013 20:40:32 +0000]
ARM: tegra: dalmore: clear fb if bl fb not defined.

Clear primary framebuffer if bootloader framebuffer is not defined.
(Some bootloader such as u-boot may not support LCD display and not
supporting LCD in bootloader is purely customer's choice and the
kernel display driver should survive such configuration).

bug 1301464
bug 1264520

Change-Id: Ia37f1f9db08166509bf02673268180f277286dc2
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/243977
(cherry picked from commit 6e713daa1b729e341f682568a12bd0ef0249be72)
Reviewed-on: http://git-master/r/259254
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoARM: tegra: pcie: Fix T124 Hotplug functionality
Jay Agarwal [Tue, 6 Aug 2013 12:20:18 +0000]
ARM: tegra: pcie: Fix T124 Hotplug functionality

1. Put work handler into right section to avoid
   kernel panic
2. Do prsnt map override in poweroff after all
   pcie devices has been removed from pci_dev

Bug 1332184

Change-Id: I8d1fe2ea89a58e9a53e01d7103e2c5304e87165c
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/258702
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra12: speedo: read gpu speedo info
Prashant Malani [Tue, 6 Aug 2013 03:32:38 +0000]
ARM: tegra12: speedo: read gpu speedo info

Populate gpu process id information based on
gpu speedo value. Also add threshold to
determine process id.

Bug 1329868

Change-Id: I05ca0bfb7acdac0eaa0ed91867738b51214e3db8
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/258459
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: enable soc timers for cpu events
Seshendra Gadagottu [Wed, 24 Jul 2013 00:35:18 +0000]
ARM: tegra: enable soc timers for cpu events

When TEGRA_SOC_TIMERS is enabled use SOC timers
instead of ARM core private timers for cpu clock events.

Bug 1314282

Change-Id: Ie8c43f7e2215b4450b62a98922ab167d366fe053
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/252669
(cherry picked from commit 530946bacdc91069f4284748bf0edf67a8748831)
Reviewed-on: http://git-master/r/256961
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: Add kernel config for TEGRA_SOC_TIMERS
Seshendra Gadagottu [Wed, 24 Jul 2013 00:15:23 +0000]
ARM: tegra: Add kernel config for TEGRA_SOC_TIMERS

Add kernel configuration to enable TEGRA_SOC_TIMERS.
When this feature is enabled CPU clock events will
use SOC timers instead of ARM private timers.

Bug 1314282

Change-Id: Ifb6c74106a7420e9badddefa8b58ce0861f7c1eb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/252667
(cherry picked from commit efa2c28692444a69506d803c62a2b6b45c0c05b2)
Reviewed-on: http://git-master/r/256959
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoEDP: tegra: add psy emulator mode
Sivaram Nair [Tue, 23 Jul 2013 10:19:14 +0000]
EDP: tegra: add psy emulator mode

Add an emulator mode to the psy depletion client so that we can emulate
different depletion states. This mode requires the board to specify a
valid { capacity, OCV } lut.

Bug 1293353

Change-Id: Ie4f83ee70cec3575ee42a8edea4524d0a33da0fb
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/255648
(cherry picked from commit db1d75dc8dfaec9d0c906413d9b1eaf1df9c1e64)
Reviewed-on: http://git-master/r/256830
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agopower: palmas: add OVC_ALARM programming
Sivaram Nair [Wed, 24 Jul 2013 14:00:22 +0000]
power: palmas: add OVC_ALARM programming

Added changes for monitoring battery over current and generating alarm.

Bug 1328317

Change-Id: I4650815e8b0ca7083b9168cccc61f877a4e31df5
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/252941
(cherry picked from commit ca564d5e2f8ba91510059d548dd2839fff9cda45)
Reviewed-on: http://git-master/r/256828
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra: cputimer: reset IRQ affinity during cpu_disable
Seshendra Gadagottu [Sat, 29 Jun 2013 06:58:45 +0000]
ARM: tegra: cputimer: reset IRQ affinity during cpu_disable

(Original patch written by Paul Walmsley <pwalmsley@nvidia.com>)

Switch the CPU affinity of the Tegra cputimer IRQ to CPU0 much later
in the hot-unplug process - after sched_cpu_inactive() runs.

The code originally added by commit
6012d7167f715f91a43f0bf826aae00de0e5f860 ("ARM: tegra: fix warning
related to soc timer irq affinity") switched the CPU affinity of the Tegra
cputimer IRQ during the CPU_DOWN_DISABLE phase of the cpu_notifier.
This is the same phase used by sched_cpu_inactive() to mark the CPU as
unavailable to the scheduler, as well as by cpufreq_cpu_callback().
The call to sched_cpu_inactive() must take place before the CPU
affinity of the cputimer IRQ is reset.  Unfortunately there's no easy
and clean way to enforce ordering inside this notifier chain.

This could result in the following attempted notifier callback sequence:

1. Tegra cputimer hotplug_notify()
   -> CPU1 no longer receives scheduler ticks from its local timer

2. cpufreq_cpu_callback()
   -> eventually winds up in schedule() - but cannot make progress because
      the scheduler tick is never received
   -> HANG

3. sched_cpu_inactive()

To work correctly, the CPU affinity of the Tegra cputimer IRQ must
only be switched after sched_cpu_inactive() runs.

The initial approach attempted was to move the affinity switch to the
CPU_DYING cpu_notifier event.  This causes warnings to be logged to
the kernel console by the ARM migrate_irqs() code, which does not
expect an IRQ to have an affinity to a downed CPU.  So instead, we
move the affinity switch to the Tegra-specific callback for the
cpu_disable() smp_ops function pointer.  This is called between the
CPU_DOWN and CPU_DYING cpu_notifier events.

Bug 1309706
Bug 1317133

Change-Id: I2756843917c77ac1405c35bd726a7294f947e406
[sgadagottu@nvidia.com: removed EXPERIMENTAL notations; removed
Cc: lines; wrapped references to tegra_cputimer_reset_irq_affinity()
 in #ifdefs; updated copyrights]
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/243683
(cherry picked from commit dbd37f36c6793377e59a9d69a12542fd32ca224f)
Reviewed-on: http://git-master/r/247335
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra14: Support for clkgt_at_vmin
Seshendra Gadagottu [Thu, 30 May 2013 21:55:03 +0000]
ARM: tegra14: Support for clkgt_at_vmin

Added support for clkgt_at_vmin power gating mode.
This is applicable for fast CPU0 when running on DFLL.
This feature is disabled by default through debug node.

Bug 1235084

Change-Id: Ic60d67abe025a1e1cbcd054110214547e081f0c8
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/241058
(cherry picked from commit 15b5040b9caa32b31e34ad2e65b5a24e31f950b5)
Reviewed-on: http://git-master/r/247334
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years ago ARM: tegra14: Add support for new fuse values
Seshendra Gadagottu [Thu, 27 Jun 2013 18:09:54 +0000]
 ARM: tegra14: Add support for new fuse values

 Bug 1246952

Change-Id: I4b7fc994daf654057d352ae4ce246c864bc86026
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/242989
(cherry picked from commit 68ddaa53d9c3da1bc3ece1f80329c0f4b2a24a86)
Reviewed-on: http://git-master/r/247333
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra14: dvfs: Update thermal vdd_cpu tables
Seshendra Gadagottu [Thu, 20 Jun 2013 01:27:05 +0000]
ARM: tegra14: dvfs: Update thermal vdd_cpu tables

Update thermal vdd_cpu min based on new silicon validation
data released on 06/15

Bug 1246952

Change-Id: I1b74dd0e94af1e8358bfa8848b968f971b0a51dc
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/240416
(cherry picked from commit 9b19cae667bd228d164d93804eb32aef81175600)
Reviewed-on: http://git-master/r/247331
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoregulator: tps51632: add support for GPIO to control rails
Laxman Dewangan [Tue, 6 Aug 2013 09:59:18 +0000]
regulator: tps51632: add support for GPIO to control rails

The TPS51632 regulator is externally controlled by default and
this can be connected to the GPIO on some system.

Add support to pass the GPIO number to control the rail through
GPIOs.

Change-Id: I602a6a3e5c489b54dc9ead75476429c0d44f76d0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/258664

6 years agoARM: tegra12: config: enable AS3722_ADC_EXTCON config
Laxman Dewangan [Fri, 2 Aug 2013 10:57:04 +0000]
ARM: tegra12: config: enable AS3722_ADC_EXTCON config

Enable AS3722_ADC_EXTCON config to enable continuous scanning in
AMS3722 ADC channel.

Change-Id: Iaf44d0b1504cdbc07a65c48e9917a597203ae470
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/257488
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra12: ardbeg: provide as3722 ADC platform data
Laxman Dewangan [Fri, 2 Aug 2013 10:54:56 +0000]
ARM: tegra12: ardbeg: provide as3722 ADC platform data

Change-Id: I0c0a16e4adb0b66ebe3200e3aa9d54fb4e2b0642
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/257487
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agomfd: as3722: register adc driver
Mallikarjun Kasoju [Fri, 2 Aug 2013 10:53:57 +0000]
mfd: as3722: register adc driver

Register adc driver as mfd sub device and provide IRQ number
through IRQ resource.

Change-Id: I25b86a4b3f2dc896dae57b02811f74726575a878
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/257486
Reviewed-by: Automatic_Commit_Validation_User

6 years agostaging: iio: as3722: implement continuous scanning for channel
Laxman Dewangan [Fri, 2 Aug 2013 10:49:44 +0000]
staging: iio: as3722: implement continuous scanning for channel

Implement continuous scanning of channel and notify the event
through extcon if high or low threshold crosses.

Change-Id: I60b46b8d30cced8ab4de8f9365ebd5d8a14265af
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/257485

6 years agoregulator: as3722: do not enable external control interrupt
Mallikarjun Kasoju [Mon, 22 Jul 2013 13:23:03 +0000]
regulator: as3722: do not enable external control interrupt

Bug 1330228

Change-Id: I8dba97f1d1cc6632e4c98d4cdf764b4eff36955c
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/257484

6 years agoarm: mm: dma-mapping: don't let prefetch page mapping fail
Konsta Holtta [Wed, 31 Jul 2013 06:58:36 +0000]
arm: mm: dma-mapping: don't let prefetch page mapping fail

Require also the prefetch page to map in pg_iommu_map*(): return error
if either it or the requested buffer fail to map.

Bug 1303110
Bug 1338469

Change-Id: I57f59207fb547390d87a24d7c4c7faec23a61768
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/256163
(cherry picked from commit b6fe2c18b9528a112943a054866a452f1fff3425)
Reviewed-on: http://git-master/r/259519
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

6 years agovideo: tegra: host: gk20a add comp tag flushing
Ken Adams [Fri, 9 Aug 2013 00:57:09 +0000]
video: tegra: host: gk20a add comp tag flushing

We need to flush the compression tag cache any time
we're flushing the "fb."  E.g.: right before power
gating.  Note: this technique probably does enough
to flush "fb" all by itself.  So we may remove the
later state of manual fb flush after further testing.

bug 1331831

Change-Id: Ibc7df2a7decf17a1485602e7b888c35f356912ca
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/259851
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agovideo: tegra: host: simplify gk20a pte loop
Ken Adams [Thu, 8 Aug 2013 02:07:31 +0000]
video: tegra: host: simplify gk20a pte loop

Removes some extraneous work from the gmmu pte update loop.
Removes some unused vars.
Coalesces a few different info prints into one per pte.

bug 1328042

Change-Id: I7e87faf5845dbf7f5d3d3c65af12b224186600d5
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/259429
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

6 years agovideo: tegra: gk20a: GPCPLL SW shadow register
Kaz Fukuoka [Wed, 7 Aug 2013 23:18:10 +0000]
video: tegra: gk20a: GPCPLL SW shadow register

Implement software shadow register for M, N, and PL values
to allow changing rate while GPU is power gated,
and to use the values when GPU is power ungated next time.

- Keep GPCPLL register M, N, and PL value in software.
- Removed gpc_initial_freq which was duplicated initialization.
- Skip writing registers if GPU is powergated.

bug 1344073

Change-Id: I1ab15704f7117e79f4b7c1ad9378cfebe517e6d2
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/259352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoxhci: tegra: support HSIC ports
JC Kuo [Thu, 1 Aug 2013 15:03:55 +0000]
xhci: tegra: support HSIC ports

This change add HSIC ports support to tegra XHCI host controller.
HSIC hub can be enumerated by XHCI host successfully.

Wakes from U3/ELPG/LP0 by either host or device initiated resume
signaling are also working.

bug 1301838

Change-Id: Id7e6fd949194489c6c7d0f212c659f11de85417e
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/256882
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: T12x wake table add UHSIC wake events
JC Kuo [Wed, 31 Jul 2013 07:37:06 +0000]
ARM: tegra: T12x wake table add UHSIC wake events

Add UHSIC wakes to T12x wake table so that UHSIC line wake events can
wake system from LP0.

bug 1301838

Change-Id: I6d3345eab316cdc0f7d54837f1ae564f4b821fdb
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/256881
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Joy Wang <joyw@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agousb: xhci: tegra: enable clock after unpowergate
joyw [Tue, 6 Aug 2013 08:28:42 +0000]
usb: xhci: tegra: enable clock after unpowergate

Follow PG, enable host partition clock after unpowergate
host partition.

Bug 1333946

Change-Id: I47d7bfaedded3d8ca07edd9c1315ade2cccdc579
Signed-off-by: joyw <joyw@nvidia.com>
Reviewed-on: http://git-master/r/258633
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agoARM: configs: Enable SMP for bonaire_sim
Alex Van Brunt [Mon, 5 Aug 2013 23:16:49 +0000]
ARM: configs: Enable SMP for bonaire_sim

Change-Id: Ic1c0f457daa7b242c4e7ac557c718c6c4c5ad489
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/258380
Reviewed-by: Automatic_Commit_Validation_User

6 years agovideo: tegra: nvmap: Fix compile error in nvmap.h
Alex Waterman [Mon, 5 Aug 2013 23:04:44 +0000]
video: tegra: nvmap: Fix compile error in nvmap.h

When page pools are disabled an inline function gets compiled that
has no default return. This generates a warning and causes main to
fail compilation.

Bug 1343106

Change-Id: I8ac23e43e7832c4cedff73d0a8735b51f0760af2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/258377
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoARM: tegra14: clock: Allow G CPU min rate same as LP backup
Alex Frid [Mon, 17 Jun 2013 23:30:47 +0000]
ARM: tegra14: clock: Allow G CPU min rate same as LP backup

Changed cpufreq table generation to support G CPU minimum rate as low
as LP CPU back-up rate.

Bug 1262597

Change-Id: I590e01b6a52b6d1bc61a84c77bffe05f54a3d1d6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239452
(cherry picked from commit 8d402bfcf48ad96cf5a588148144877de5674dd5)
Reviewed-on: http://git-master/r/258310
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra14: power: Save clock configuration on LP1BB entry
Alex Frid [Mon, 17 Jun 2013 22:03:40 +0000]
ARM: tegra14: power: Save clock configuration on LP1BB entry

Change-Id: If8ca43f947005187ebe03b49ccc22387db21885d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239434
(cherry picked from commit 3871cdd921a315c5c69395d9350dc975c1526c8c)
Reviewed-on: http://git-master/r/258309
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra14: clock: Add interface to set LP CPU idle rate
Alex Frid [Sun, 12 May 2013 05:56:45 +0000]
ARM: tegra14: clock: Add interface to set LP CPU idle rate

Added interface to set LP CPU idle rate by direct (i.e., underneath
cpufreq governor) backup PLL rate control. This interface is not used
by cpu idle governor, yet.

Change-Id: I26a6c1a0169d08e0881799f36433a362d2f1c8aa
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238754
(cherry picked from commit 5cb065936ac0cd32a039e3406e053dcd3f9fcf5e)
Reviewed-on: http://git-master/r/258308
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra14: clock: Boost CPU rate for EMC bus update
Alex Frid [Sun, 12 May 2013 04:50:33 +0000]
ARM: tegra14: clock: Boost CPU rate for EMC bus update

Set CPU rate to backup rate during EMC clock bus update on LP CPU.
This would allow to reduce the worst case of EMC clock update latency
when CPU is running on LP cluster at sub-backup rates.

Since backup rate is guaranteed to be safe at minimum voltage boosting
and restoring rate can be done underneath dvfs and cpufreq governor.
Used sequence counter mechanism to make sure new governor rate setting
(that may happen during EMC bus update) is not overwritten when backup
rate is restored.

Bug 1278984

Change-Id: Ic66a5d50139c61dba4457425002f10b0aabaffeb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238753
(cherry picked from commit 6b107a7da43c87ce21b182b50805e1602b5d8cac)
Reviewed-on: http://git-master/r/258307
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra14: clock: Re-factor and expand host1x bus
Alex Frid [Sun, 9 Jun 2013 03:27:44 +0000]
ARM: tegra14: clock: Re-factor and expand host1x bus

- Set host1x dev_id = "host1x" and con_id = NULL (these definitions
were used before conversion of host1x to shared bus; during conversion
ids were inadvertently swapped - restored now)

- Add cap, and floor, shared users to host1x bus. Attached cap user to
core cap interface.

Change-Id: I7a9823889ca9e0a8d18856aef4470e0c2e7318c5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238748
(cherry picked from commit eb9fcb97e0220af42b732713885967252ba32164)
Reviewed-on: http://git-master/r/258306
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: clock: Re-factor and expand host1x bus
Alex Frid [Sat, 8 Jun 2013 06:42:11 +0000]
ARM: tegra11: clock: Re-factor and expand host1x bus

- Set host1x dev_id = "host1x" and con_id = NULL (these definitions
were used before conversion of host1x to shared bus; during conversion
ids were inadvertently swapped - restored now)

- Add cap, and floor, shared users to host1x bus. Attached cap user to
core cap interface.

Change-Id: I75d73964fc8f74558ba4ac555a2b018bc554e88a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238746
(cherry picked from commit 0da8b11f8d90bc1a00ab1e62f36f184bf64db66f)
Reviewed-on: http://git-master/r/258305
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: clock: Turn Off memory PLLs in resume
Alex Frid [Thu, 13 Jun 2013 04:10:13 +0000]
ARM: tegra11: clock: Turn Off memory PLLs in resume

Turned Off memory PLLs (PLLM or PLLC) in clock resume if they are left
enabled by LP0 or LP1 exit code, but not used as EMC clock sources.

Change-Id: I017e79007873d8d4b918853e08e0cc27a424e310
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238745
(cherry picked from commit ab02ca044fe93aceb6e32f7daa24ab5d9dcb2fd1)
Reviewed-on: http://git-master/r/258304
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: dvfs: Increase number of rail stats bins
Alex Frid [Tue, 14 May 2013 21:55:14 +0000]
ARM: tegra: dvfs: Increase number of rail stats bins

Change-Id: Ia18237f06e407f14b9ab10758fc9eb16fb483cb9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/228510
(cherry picked from commit 26f1e60b69ce8fe4b2202df1c358d38a92bc226d)
Reviewed-on: http://git-master/r/240016
(cherry picked from commit 525569c6658f12e528d38bca11c510a00ec59a64)
Reviewed-on: http://git-master/r/258272
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: clock: Show ISO/BW marginal rates in clock tree
Alex Frid [Thu, 23 May 2013 02:35:53 +0000]
ARM: tegra: clock: Show ISO/BW marginal rates in clock tree

Change-Id: I8b1b55dc5684e95d7074f84f667d4242410a29f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238750
(cherry-picked from commit a8556ee16c8da597a399fb592f41c4b3ba7f5c8f)
Reviewed-on: http://git-master/r/258271
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: dvfs: Separate dvfs rail safe steps up/down
Alex Frid [Sun, 16 Jun 2013 00:52:40 +0000]
ARM: tegra: dvfs: Separate dvfs rail safe steps up/down

Separated safe voltage steps definitions for dvfs rail transitions
up and down. For now keep steps the same on all tegra platforms.

Bug 1306654

Change-Id: Ica06149577d42ea8c30aa15f642642ebe552de1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239133
(cherry picked from commit 7f0789482589fa1de8e6bf6f800032fb6b87b58f)
Reviewed-on: http://git-master/r/258270
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra14: mc: Handle spurious interrupts
Alex Waterman [Fri, 2 Aug 2013 00:24:08 +0000]
ARM: tegra14: mc: Handle spurious interrupts

T114 is not the only chip that appears to generate spurious MC
interrupts. This patch expands the ability to handle such
interrupts to all chips.

Bug 1325378

Reviewed-on: http://git-master/r/257181
(cherry picked from commit d9c0356b2d66c57f6978595710ad4d2aed690bba)
Change-Id: I5431f8f11714428c0219a4074a09ae9eeb9e218c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/258254
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoARM: tegra: emc: Derating support
Alex Waterman [Wed, 3 Jul 2013 21:55:14 +0000]
ARM: tegra: emc: Derating support

Add support for derating via keeping two separate sets of EMC tables.
One set is nominal, the other set is derated. Based on the temperature
reported by the DRAM the EMC thermal driver can specify which set of
tables the EMC driver should use when swapping frequencies.

This patch also adds support for a more graduated response to rising
temperature. The DRAM reports 3 levels of refresh and derating
requirements:

  0x4: Refresh x2
  0x5: Refresh x4
  0x6: Refresh x4 + derating

The particular combination of refresh modification and derating is now
picked based on the particular level of throttling necessary.

This feature is not imlpemented in older chips. The old approach is
maintained - just a 4x refresh timing for all temperature throttle
states.

Reviewed-on: http://git-master/r/252624
(cherry picked from commit 5073cf9a13344c7e9c35475bce17539615ec4956)
Change-Id: I16f0477a0b0eadc194c9f1f48a66a0bf098b0df3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257646
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra14: emc: Set DATA_SEL_DPD based on freq
Alex Waterman [Tue, 16 Jul 2013 22:49:59 +0000]
ARM: tegra14: emc: Set DATA_SEL_DPD based on freq

For frequencies above 408 MHz, disable DATA_SEL_DPD in the
EMC_SEL_DPD_CTRL register.

Bug 1270473

Reviewed-on: http://git-master/r/249954
(cherry picked from commit 7557508927d2b513dfa7bbb02a12f6e25f24878f)
Change-Id: I24859c57b45f1d072e853907ab2eb77f3c162172
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257645
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: power: Update DFLL bypass start/suspend/resume
Alex Frid [Fri, 2 Aug 2013 05:43:18 +0000]
ARM: tegra: power: Update DFLL bypass start/suspend/resume

- Initialized DFLL before legacy dvfs if DFLL bypass is enabled
(reversed common initialization order: first legacy dvfs - then DFLL,
since  DFLL bypass device is used as regulator by legacy dvfs)

- Isolated DFLL output from voltage supply on entry to any state with
CPU cluster powered down (suspend, cluster idle), and resumed normal
operation on exit. This is necessary to avoid unpredictable effect of
DFLL output on CPU voltage during power transitions.

Bug 1310396

Change-Id: Ie42b92633367337ebc08200ab425baaf9043d133
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257346
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: ardbeg: Add DFLL bypass device
Alex Frid [Thu, 1 Aug 2013 22:28:31 +0000]
ARM: tegra: ardbeg: Add DFLL bypass device

Added dfll bypass regulator definitions for ardbeg board. Since
initial regulator voltage cannot be read, initialize it to nominal
level explicitly.

Bug 1310396

Change-Id: I580c4c7825f1e279b98b73002638a8e9bc5c4aea
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257345
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: dvfs: Add offset to rail alignment
Alex Frid [Fri, 2 Aug 2013 04:02:05 +0000]
ARM: tegra: dvfs: Add offset to rail alignment

With the introduction of analog PWM regulator on Tegra12 platforms,
minimum cpu voltage may not be exactly aligned with PWM steps. The
respective offset is specified by platform data early enough for dvfs
initialization, and accounted for when rounding dvfs cvb voltages.

Bug 1310396

Change-Id: I4ff570a5c0519b85085b3b5e22076b906e95068c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257344
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: dvfs: Add DFLL bypass interfaces
Alex Frid [Tue, 30 Jul 2013 07:15:31 +0000]
ARM: tegra: dvfs: Add DFLL bypass interfaces

When DFLL voltage supply is connected to CL-DVFS control logic via
PWM interface, the respective regulator can be accessed only via
CL-DVFS registers.

This commit has added set/get APIs for direct access to CL-DVFS force
output register to be used by dfll bypass regulator driver. Set API
always updates force value, but applies it only in open loop mode, or
disabled mode. In closed loop mode bypass request is ignored to avoid
interference with automatic voltage control. Get API returns force
value back if it is applied, and returns monitored output, otherwise.
Hence, get value matches real CL-DVFS output in any mode.

The new APIs are not exposed to dfll bypass driver if DFLL supply is
connected by I2C interface, since h/w provides access to the regulator
I2C bus via one of tegra I2C controllers.

Bug 1310396

Change-Id: I90b433cc03cb739cc7b9c89d2d3ef8dbb00cb447
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257343
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

6 years agoARM: tegra: power: Add DFLL bypass regulator driver
Alex Frid [Tue, 30 Jul 2013 01:12:26 +0000]
ARM: tegra: power: Add DFLL bypass regulator driver

In addition to its main function - automatic voltage scaling, Tegra
DFLL can be used in bypass mode to control voltage by s/w. This
commit introduced a simple linear voltage regulator as a wrapper
around DFLL bypass interfaces.

Bug 1310396

Change-Id: I18430b8125de6b6e84d7eee91f2f887d68d96fb5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257342
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

6 years agoarm: mm: cpa: fix compilation errors when nvmap is disabled
Krishna Reddy [Mon, 5 Aug 2013 23:24:51 +0000]
arm: mm: cpa: fix compilation errors when nvmap is disabled

avoid dependency on nvmap defined variables.
set inner cache size threshold correctly between A9 and A15.
fix compilation issue during non-SMP build.
Bug 134220

Change-Id: I65eb0c3a8c11a03b4bf49e7903f91bb74d27a20f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/258385
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

6 years agoarm: tegra: make ahb gizmo writel irq safe
Nitin Kumbhar [Thu, 8 Aug 2013 17:31:32 +0000]
arm: tegra: make ahb gizmo writel irq safe

Bug 1315068

Change-Id: I59566817601a102f95aba5415fb4a7d9ce138bab
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/259701
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

6 years agovideo: tegra: host: Disable gk20a power gating
Terje Bergstrom [Thu, 8 Aug 2013 08:05:25 +0000]
video: tegra: host: Disable gk20a power gating

Power gating causes losing CBC state. Disable it by extending
timeout.

Bug 1331831

Change-Id: I49757cee751e8d17c514a4ad5c9c024679608b10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/259548
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoarm: tegra: disable tskin throttling for board with no skin diode
Diwakar Tundlam [Thu, 8 Aug 2013 00:28:12 +0000]
arm: tegra: disable tskin throttling for board with no skin diode

Disable by raising throttle limit to 200C. Those with skin diode can
manually set it to 50C as needed.

Bug 1345131
Bug 1315460

Change-Id: I1eb14d1f473825c10be3d05e63aedc5d40079e17
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/259385

6 years agovideo: tegra: host: fix gk20a comptag address error
Ken Adams [Wed, 7 Aug 2013 20:00:32 +0000]
video: tegra: host: fix gk20a comptag address error

We were trying to perform a round-up but botched
the comparison.

bug 1331831

Change-Id: Id5426fd97002fea186c011afae96fdceaf14b944
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/259306
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agovideo: tegra: host: Report LTC interrupts
Terje Bergstrom [Mon, 5 Aug 2013 09:58:15 +0000]
video: tegra: host: Report LTC interrupts

Add reporting and clearing of LTC interrupts. This prevents an
interrupt storm if we have an L2 related error.

Change-Id: I24dd596143b69fbab85caca4cdc653f80222e0ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/258151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agovideo: tegra: gk20a: disable ELCG.
Kevin Huang [Tue, 6 Aug 2013 23:46:36 +0000]
video: tegra: gk20a: disable ELCG.

Disable it for stability.

Change-Id: I7abfdb19cddfc5ccaae5852389b2e48cc5e566ea
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/258891
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agodrivers: tegra: gk20a: disable slcg
Prashant Malani [Tue, 6 Aug 2013 21:02:30 +0000]
drivers: tegra: gk20a: disable slcg

Disable slcg graphics and perf load gating.

Change-Id: I5dc4a8869ef14c412469fd49ae5dd4d551fa841e
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/258835
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agodrivers: tegra: gk20a: Disable blcg
Prashant Malani [Tue, 6 Aug 2013 21:00:47 +0000]
drivers: tegra: gk20a: Disable blcg

Change-Id: Ie5c38d16ca2f00cd45ee64844030d4814b9ab0af
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/258834
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: dsi: Fix dsi resume
Animesh Kishore [Mon, 5 Aug 2013 10:44:29 +0000]
video: tegra: dsi: Fix dsi resume

- Support lp-00/lp-11 before panel wakeup.
- Platform flag to enable/disable ulpm.

Bug 1341152

Change-Id: I99b77bd4fd707de1a9a2f452be93610b971f5844
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/258165
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoarm: tegra: dalmore: Fix sharp 25x16 power on/off
Animesh Kishore [Mon, 5 Aug 2013 10:48:53 +0000]
arm: tegra: dalmore: Fix sharp 25x16 power on/off

- lp-00 before wake-up
- disable ulpm.
- add stabilization delays.

Bug 1341152

Change-Id: I8120aba4bd305480a6e1bdaa23c48ac82091ea55
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/258166
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agodma: Add GCOV_PROFILE
Konsta Holtta [Mon, 5 Aug 2013 10:49:54 +0000]
dma: Add GCOV_PROFILE

Include dma in GCOV profiling when enabled by defconfig.

Change-Id: Ia3a55f0d985370c3d4c740039318f9bb5e74b32b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/258178
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra12: actmon: Fix EMC count_weight for T124
Vikas Jain [Wed, 17 Jul 2013 10:53:49 +0000]
ARM: tegra12: actmon: Fix EMC count_weight for T124

T124 will burn 4 emcclks for a request of
any size up to the max request size of 64B,
so for T124 emc-clock-per-atom is 4.

Bug 1326781

Change-Id: I1646cb41f52cb6b879e44998ed49a17d659e8533
Signed-off-by: Vikas Jain <vjain@nvidia.com>
Reviewed-on: http://git-master/r/258073
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dc: Get rid of the 'Unsupported dithering' message
Chao Xu [Fri, 2 Aug 2013 17:51:34 +0000]
video: tegra: dc: Get rid of the 'Unsupported dithering' message

Most panel files do not provide the default dithering mode, which causes
error message of 'unsupported dithering mode'. Set the mode to disable
if not set.

Change-Id: I5daeb6e2d8079f0675e5502e135e568a4c473c40
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/257620
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoinput: touchscreen: raydium v60.2 touch driver
Xiaohui Tao [Fri, 2 Aug 2013 17:09:32 +0000]
input: touchscreen: raydium v60.2 touch driver

raydium code drop

[1] Add additional info for regulator event msg

[2] Add RM_PLATFORM_A010 for Ardbeg AVC sensor

[3] Fix no touch function in Pluto platform with RM31081 from idle mode

[4] Refine Pismo touch direction

[5] Fix idle mode problem with Ardbeg AVC sensor

Bug 1330952

Change-Id: Ib282bec3f07a16eb657314ee5127824f02a89d02
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/257604
Reviewed-by: Mitch Luban <mluban@nvidia.com>

6 years agomisc: nct1008: adjust reported temp via offset table
Diwakar Tundlam [Thu, 25 Jul 2013 01:33:46 +0000]
misc: nct1008: adjust reported temp via offset table

Add support to specify a table of temperature dependent offsets
that will be added to the measured temperature before reporting
it to the thermal zone. Actual temperature is still reported in
'temperature'.  We only adjust the temperature reported to
thermal zone via the xxx_get_temp() API.

This is done only for external sensors as requested.

Bug 1330895

Change-Id: I419aa62b2a69f9a96b1fab401fc53e791386b300
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/257044

6 years agomisc: nct1008: move debug regs to I2C driver dir
Diwakar Tundlam [Wed, 24 Jul 2013 01:16:19 +0000]
misc: nct1008: move debug regs to I2C driver dir

With multiple NCT devices support, we cannot have a single
debugfs node to display device registers. Remove /d/nctxxx and
move it to the I2C device driver directory which exists
separately per device.

Bug 1330895

Change-Id: I92feb281a3eaa599d85ad052e4d2c54609fa42e3
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/257043
Reviewed-by: Automatic_Commit_Validation_User

6 years agovideo: tegra: dc: Update LVDS power up sequence
Chao Xu [Wed, 31 Jul 2013 00:35:26 +0000]
video: tegra: dc: Update LVDS power up sequence

Change-Id: I03f5fa4097b9c3a1979d440b78e7bdcaef505c60
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/257030
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: ardbeg: Change to use the right platform ID
Xiaohui Tao [Thu, 1 Aug 2013 17:03:39 +0000]
ARM: tegra: ardbeg: Change to use the right platform ID

Bug 1330952

Change-Id: I5c177ab7b6e41923a793e95150c35675c0deb89e
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/256923
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoarm: tegra: dalmore: Add sharp 25x16 suspend seq
Animesh Kishore [Thu, 1 Aug 2013 12:59:38 +0000]
arm: tegra: dalmore: Add sharp 25x16 suspend seq

Bug 1341152

Change-Id: I8d98bed73503e2257f0025c2044077b6d6d1ef45
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/256836
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agovideo: tegra: dsi: Fix dsi suspend sequence
Animesh Kishore [Thu, 1 Aug 2013 12:44:43 +0000]
video: tegra: dsi: Fix dsi suspend sequence

- explicitly disable backlight before suspend
- power gate pad after panel power gate

Bug 1341152

Change-Id: Ibf664efc3db371d09ac6f380706528b139eafce5
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/256835
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agoARM: tegra: board:disable the unaligned dma buffer
Rakesh Bodla [Tue, 30 Jul 2013 08:01:40 +0000]
ARM: tegra: board:disable the unaligned dma buffer

Disable usb h/w alignment fix.

Bug 1289107

Change-Id: Ice6c9b6d561bea3ef629e12fe9c5773512a9df04
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/255419
(cherry picked from commit 949ac7681ee99dae5ad75fba6903ece3690700a1)
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/256763
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoarm: tegra: ardbeg board file change for cpu edp init
Xue Dong [Tue, 23 Jul 2013 00:03:11 +0000]
arm: tegra: ardbeg board file change for cpu edp init

bug 1330937

Change-Id: I70216a8cb8007912670b7a403eb1736ad5ee4b9e
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/256487
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>