5 years agoARM: tegra: Enable headsmp.S without CONFIG_SMP
Scott Williams [Tue, 19 Jul 2011 22:08:43 +0000]
ARM: tegra: Enable headsmp.S without CONFIG_SMP

In the current implementation for Tegra2, tegra_resume is required for
low power states, and it's coupled with CONFIG_SMP in headsmp.S. In
the implementation for Tegra3, we'll want to use tegra_resume even
without SMP.

Change-Id: I868eaf1de4f2898d2b1ad220638c0588901384c3
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R25c78e24b79d8bdd244c9cf5df85742047f71291

5 years agoARM: tegra3: Remove FIXME for LP2 timers
Dan Willemsen [Thu, 21 Jul 2011 20:12:34 +0000]
ARM: tegra3: Remove FIXME for LP2 timers

Now that the LP2 timers exist, remove the FIXME

Change-Id: I72e3a5b1aadf79f3adfe40a865ac23c94342cf47
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rceb895f0e2ef1871156a09ff6b582a47907ad3ec

5 years agoARM: tegra2: Add LP2 Timers
Scott Williams [Tue, 19 Jul 2011 00:42:46 +0000]
ARM: tegra2: Add LP2 Timers

Restore the Tegra2 LP2 timers that were dropped in the port to Linux
2.6.39.

Change-Id: Ie3958fa3c89886d5dc5a5858c694400bd1421741
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
DW: Add export.h include
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R63ede668965d11ac2b2114ffa817b690a616205a

5 years agoARM: tegra: Split sleep.S for Tegra2
Scott Williams [Mon, 18 Jul 2011 22:20:56 +0000]
ARM: tegra: Split sleep.S for Tegra2

Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e

5 years agoARM: tegra: Build pm.c even without PM_SLEEP
Scott Williams [Mon, 18 Jul 2011 21:31:04 +0000]
ARM: tegra: Build pm.c even without PM_SLEEP

Change-Id: I13799aa03f86c7d83faf8ffa49954fef15aa0bdc
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ra6e14b10f89a40a1f09169d864dbaa9e62c7280a

5 years agoARM: tegra: Make LP2 require CONFIG_PM_SLEEP
Scott Williams [Mon, 18 Jul 2011 21:19:07 +0000]
ARM: tegra: Make LP2 require CONFIG_PM_SLEEP

Change-Id: Iaaf96375eaf7408f5bedc4196d33a04fb94129ef
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R98567e0d894acbdac770b191f7e46f16592d5d0b

5 years agoARM: tegra2: Move LP2 into cpuidle-t2.c
Scott Williams [Mon, 18 Jul 2011 20:41:32 +0000]
ARM: tegra2: Move LP2 into cpuidle-t2.c

Move Tegra2 SOC-specific CPU idle functionality to cpuidle-t2.c

Change-Id: I26c94ca74d7a78665c52e23571c5058e3da240a7
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R1246e3942623458f5121ccdac3e6d4a1d40ad624

5 years agoARM: tegra: Move Tegra2 idlestats to cpuidle-t2.c
Scott Williams [Mon, 18 Jul 2011 18:34:12 +0000]
ARM: tegra: Move Tegra2 idlestats to cpuidle-t2.c

Change-Id: I2c0814cfefd820626beeba468edd9c462c6be8bb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rbbb70f49af4e731c953315ae81a96480ac25ff4d

5 years agoARM: tegra: Add cpuidle.h
Scott Williams [Fri, 22 Jul 2011 21:49:17 +0000]
ARM: tegra: Add cpuidle.h

Change-Id: I75ec091f9dcd0fa3fa56b1542f58a02006c1a314
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ree5fce2632aff6dc59879817ad7ad3f2b1538244

5 years agoARM: tegra: Finish suspend.h -> pm.h rename
Scott Williams [Mon, 18 Jul 2011 18:51:19 +0000]
ARM: tegra: Finish suspend.h -> pm.h rename

Change-Id: Iad4b8a7c73ebe4b23a24b5986807358d481aac55
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb796a9ffc20dd4fbf9c463bc9cf3c175f4b03f88

5 years agoARM: tegra: update copyrights
Scott Williams [Thu, 21 Jul 2011 21:28:38 +0000]
ARM: tegra: update copyrights

Change-Id: If50d29696867787b38febd909910dda75475cc30
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2275ad736d4dbee0a7b716ee6ea19b1863d8d4f8

5 years agoARM: tegra: fuse: Don't fail when priv not passed in
Dan Willemsen [Wed, 15 Jun 2011 22:25:31 +0000]
ARM: tegra: fuse: Don't fail when priv not passed in

Rebase-Id: R63d06986e871cea59b0eb39d4290fa44b0312024

5 years agoHACKY: timer-t3 updates for K39
Dan Willemsen [Tue, 14 Jun 2011 01:42:28 +0000]
HACKY: timer-t3 updates for K39

Rebase-Id: Re2ca6bafa842d114859a40c7ab19097fd86fc635

5 years agoHACK: allow tegra3 compile without SMP
Dan Willemsen [Tue, 14 Jun 2011 01:42:01 +0000]
HACK: allow tegra3 compile without SMP

Rebase-Id: R2f09e8a42a4fe3622924aa66acb13af0bb124e98

5 years agoARM: tegra: Move tegra_mc_init to arch_initcall
Dan Willemsen [Tue, 14 Jun 2011 00:51:06 +0000]
ARM: tegra: Move tegra_mc_init to arch_initcall

It's current spot, in tegra_early_init, was too early. It was being
called before we could allocate memory.

Rebase-Id: Rff026504107e75b33dccf714c5219d78c0d1dac9

5 years agoget tegra3 compiling
Dan Willemsen [Mon, 13 Jun 2011 20:32:48 +0000]
get tegra3 compiling

Rebase-Id: R03f1fc69f4859a0dc66fbd145eb0df31650de3ac

5 years agoHACK: platsmp.c/pm-t3.c ignore compile errors
Dan Willemsen [Sat, 11 Jun 2011 03:23:16 +0000]
HACK: platsmp.c/pm-t3.c ignore compile errors

Rebase-Id: Ra4550b3ee066c825b3484bac1e928fe8c086e0c4

5 years agoARM: tegra: Disable tegra3_save.S
Dan Willemsen [Fri, 10 Jun 2011 20:57:12 +0000]
ARM: tegra: Disable tegra3_save.S

Rebase-Id: R97ea582dcab2af31a9ea19b5531d5829baacf0c6

5 years agoARM: Tegra: Add T30 audio-related entries in devices.c
Stephen Warren [Tue, 19 Jul 2011 22:26:52 +0000]
ARM: Tegra: Add T30 audio-related entries in devices.c

Also, remove "audio" platform device; it won't be used with the ALSA
driver.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: Rcbe1845a8d41292dfa82d61ff662d2f233b20af2

5 years agoASoC: Tegra: Complete Tegra->Tegra20 renaming
Stephen Warren [Tue, 26 Jul 2011 22:21:08 +0000]
ASoC: Tegra: Complete Tegra->Tegra20 renaming

Rename Tegra20-specific Kconfig variables, module filenames, all internal
symbol names, clocks, and platform devices, to reflect the fact the DAS
and I2S drivers are for a specific HW version.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: Rb2430e3fc84547430d6727fbd6adbf64afd00184

5 years agoARM: Tegra: Rename tegra_das platform device
Stephen Warren [Mon, 20 Jun 2011 17:05:23 +0000]
ARM: Tegra: Rename tegra_das platform device

... to match upstream name, and upstream ASoC driver.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Change-Id: I383aac72853ebc75612a24731f3da4035602a9ed

Rebase-Id: Rf6500c09a312b87caaa52ee3e5ed633eaf81100e

5 years agoARM: tegra: power: Restore LP2 in idle protections
Scott Williams [Wed, 29 Jun 2011 21:57:29 +0000]
ARM: tegra: power: Restore LP2 in idle protections

Restore the code that was dropped in the port to Linux 2.6.39 that
protects against using LP2 mode for idle when the platform suspend
mode has disallowed the use of LP2 mode.

Also cleans up some warning messages.

Change-Id: I357210b8a272c10bf7c1e773342dc864bbddb74e
Reviewed-on: http://git-master/r/40463
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R6a60e3f0f2ebf06ec9701475af41679c24ef80ab

5 years agoARM: tegra: power: Restore tegra_cpuidle_pm_notifier registration
Scott Williams [Wed, 29 Jun 2011 21:24:31 +0000]
ARM: tegra: power: Restore tegra_cpuidle_pm_notifier registration

Restore the registration of the CPU idle power management notifier
callback that was removed when porting to Linux 2.6.39. There is no
reason why individual CPUs should be trying to go into the LP2
state when the system is suspending.

Change-Id: I227948a60fa958b464ceb889d3369fbba2e8c8fd
Reviewed-on: http://git-master/r/40462
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R27753c83d40b0407204090e94e6948cdc6449e5b

5 years agoARM: tegra: power: Prefer movw/movt for loading addresses
Scott Williams [Wed, 29 Jun 2011 18:45:53 +0000]
ARM: tegra: power: Prefer movw/movt for loading addresses

The movw/movt instruction pair (encapsulated by the mov32 macro)
is preferred over literals for loading addresses. The use of literals
for singleton data accesses can cause unnecessary cache misses and
evictions for cache lines that are unlikely to be accessed again in
the near future. Furthermore, certain code sequences must refrain
from using data accesses. Therefore, in general, addresses should
be loaded by mov32.

Change-Id: I9bcc3ee191f882996197ce2edc0eb510d4ff7b4a
Reviewed-on: http://git-master/r/40460
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R7ddd0d9b1e2fc8ab653b9220388acbecdbf4c57f
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PM
Scott Williams [Tue, 28 Jun 2011 20:09:18 +0000]
ARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PM

For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration
parameter to use on Tegra for power management, and not CONFIG_PM.
CONFIG_PM does not have the required dependency on CONFIG_SUSPEND
necessary to pull in the CPU suspend/resume functionality used by
Tegra.

Also fixes compilation errors when CONFIG_PM and by implication
CONFIG_PM_SLEEP are not configured.

Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad
Reviewed-on: http://git-master/r/40458
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648

5 years agoarm: tegra: common: setup of pmuboard option of kernel command
Laxman Dewangan [Tue, 14 Jun 2011 19:18:57 +0000]
arm: tegra: common: setup of pmuboard option of kernel command

Adding setup function for the kernel command option pmuboard.

bug 829846

Change-Id: I227fcab7b805a50945dc39a193ba29d90663b9f8
Reviewed-on: http://git-master/r/36557
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R4830f8818fce3a85e99e75856644c95e4a18f5ab

5 years agoARM: tegra: confiure AHBDMA gizmo setting.
Jay Cheng [Thu, 9 Jun 2011 21:34:35 +0000]
ARM: tegra: confiure AHBDMA gizmo setting.

Bug 820602

Reviewed-on: http://git-master/r/35954
(cherry picked from commit 2d6cac283c1121b9a90b742b5dcf80141422eac6)
Change-Id: I87f725e1d5d90f95157f6bf9e886b415aeccb21f
Reviewed-on: http://git-master/r/36688
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Cho-Che Cheng <jacheng@nvidia.com>

Rebase-Id: R9fc254338ceec9ae0a0a805b8b348db7ad2540da

5 years agoARM: tegra: Change SOC selecton from choice to simple Boolean
Scott Williams [Thu, 9 Jun 2011 18:41:18 +0000]
ARM: tegra: Change SOC selecton from choice to simple Boolean

Change-Id: I0c19d71935a2c84ab51c0e2dcb5277670e1f96f8
Reviewed-on: http://git-master/r/35926
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>

Rebase-Id: Rae317de264f61dac09bed6a1e6c4944b825f86cd

5 years agonvhost: Add checks for # of GPU register sets.
Terje Bergstrom [Fri, 29 Apr 2011 07:45:50 +0000]
nvhost: Add checks for # of GPU register sets.

Checks from a fuse whether we have one or two register sets.

 - fuse.h/fuse.c: Implement tegra_register_sets()

 - nvhost_3dctx.c: Use tegra_register_sets() to determine number of
   sets to save.

 - dev.c: Create entry /sys/module/nvhost/parameters/register_sets to
   return to user space the number of sets.

Change-Id: Ibd9a50cfe77a642335bd85b5814e8fdd8d2c35e6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/29786
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R0a53bbe37d8d83599b85514dad33bcd04a2f67f4

5 years agoARM: tegra: power: Fix warnings when hot reset is not configured
Scott Williams [Thu, 9 Jun 2011 20:04:34 +0000]
ARM: tegra: power: Fix warnings when hot reset is not configured

Change-Id: I6dbc601cde3297e7c6fd63600c588cb3774271b8
Reviewed-on: http://git-master/r/35940
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R18e4758ac88779a5f21c5c1a01663f08bcc35a1f

5 years agoARM: tegra: dvfs: Update DVFS tables with data for T30S
Diwakar Tundlam [Fri, 27 May 2011 23:09:38 +0000]
ARM: tegra: dvfs: Update DVFS tables with data for T30S

Change-Id: I38b9752adc9e927935fe7ffe5590c41577a45809
Reviewed-on: http://git-master/r/34381
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R318f6916f8213c25092110a8800eb506d1718b38

5 years agoARM: tegra: dvfs: Update Tegra3 EMC DFS
Alex Frid [Mon, 6 Jun 2011 22:45:45 +0000]
ARM: tegra: dvfs: Update Tegra3 EMC DFS

Updated Tegra3 EMC clock change procedure with periodic qrst support,
and EMC DFS tables.

Bug 836260

Change-Id: Ia3d7f58bf61ee6e695ab62f934388d4c1b4d2079
Reviewed-on: http://git-master/r/35321
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: Rc4b52e82783d355ec3a600d636b0871119a200d5

5 years agoARM: tegra: remove calls to smp_processor_id()
Peter De Schrijver [Mon, 6 Jun 2011 12:03:16 +0000]
ARM: tegra: remove calls to smp_processor_id()

smp_processor_id() only makes sense if the code can not move to a
different CPU. The tegra clock code runs with IRQs enabled and
preemption on, so it can move to a different CPU.

Bug 827687

Change-Id: I8b3077c71966e535cc6ca2a2ec63eca0d7119777
Reviewed-on: http://git-master/r/35239
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>

Rebase-Id: R9fe292bc81ca5f456f1f54155febfa1e6e4d544e

5 years agoARM: tegra: clock: Change Tegra3 PLLP output frequency
Alex Frid [Sat, 28 May 2011 07:21:30 +0000]
ARM: tegra: clock: Change Tegra3 PLLP output frequency

On Tegra3 fixed PLLP output frequency has been set to 408MHz
(instead of 216MHz). Respectively changed:

- Tegra3 broads setting for UART, and audio clocks
- Tegra3 common clock setting for PLLP output dividers, SDMMC,
  and system buses
- Tegra3 CPU backup configuration to guarantee safe backup at
  any voltage

Bug 829081

Original-Change-Id: Ied0c75204ccb2e4a428f0b8a124f0f3e053aa386
Reviewed-on: http://git-master/r/34813
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb9a445970ed83922394a24a732372c5541d8ef47

5 years agoarm: tegra: devices: entry for security engine
Varun Wadekar [Wed, 8 Jun 2011 06:56:14 +0000]
arm: tegra: devices: entry for security engine

tegra3 has a hardware block which can be used
for encryption/decryption and hashing. add an
entry in the common location so that all the
boards using tegra3 can leverage it.

Bug 835859

Original-Change-Id: I5f3b031f5648fb04f85caa7c42b69b7482c96a7b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/35635
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R7cbf0a98df1bc006a575a4e6728008522bc27788

5 years agoarm: tegra: Add sysfs tegra chip id/revision
Hoang Pham [Wed, 8 Jun 2011 02:19:57 +0000]
arm: tegra: Add sysfs tegra chip id/revision

Original-Change-Id: Ia4437fd1374fd38b0cfaf9869012e9553ea1a156
Reviewed-on: http://git-master/r/35602
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd744a3c83776e1b70f34a3312f323ed534e321ad

5 years agovideo: tegra: host: Work towards enabling 3d power gating
Shashank Garg [Tue, 17 May 2011 11:25:23 +0000]
video: tegra: host: Work towards enabling 3d power gating

Fixed clock enable/disable balance issue. Added code for power gating 3d1.

Power gating still disabled as it won't work for T20 or T30 A01.

Original-Change-Id: Idcc5fd9d21d43c796bbeeac378a46f9eca3ab1c9
Reviewed-on: http://git-master/r/31142
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Shashank Garg <sgarg@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd1a0e542b625f569e33c74c2edcaed4ff2d6fd3e

5 years agovideo: tegra: nvmap: Add support to allocate specific IOVM
vdumpa [Mon, 16 May 2011 02:31:15 +0000]
video: tegra: nvmap: Add support to allocate specific IOVM

Original-Change-Id: I95cdf71e74947d4394e0cfd272a29c47562d4059
Reviewed-on: http://git-master/r/31648
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Rab2b1c591569698c450709be470185b0d2fe9df4

5 years agoarm: tegra: devices: device entry for uart debug ports
Laxman Dewangan [Sat, 4 Jun 2011 02:39:15 +0000]
arm: tegra: devices: device entry for uart debug ports

Adding device entry for the uart port as a debug console.
The device struture will be used in board files to invoke the
debug console driver.

bug 832273

Original-Change-Id: I61c1dbdd946d5c371d7a9b23517119048a7487cb
Reviewed-on: http://git-master/r/34445
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R28de1684d8f7fce67c09d909f7bda51259128c0b

5 years agoARM: tegra: Enable AHB prefetch for USB
Rakesh Bodla [Tue, 31 May 2011 09:48:00 +0000]
ARM: tegra: Enable AHB prefetch for USB

Enabling AHB prefetch on USB1, USB2, USB3 controllers,
to improve the USB transfer throughput.

Bug 820602

Reviewed-on: http://git-master/r/30475
(cherry picked from commit f982fa0f0878a8f4bc1739bf047313171d3cf38d)

Original-Change-Id: Iec4e877136804d023177a8689df20cc1f19cda7c
Reviewed-on: http://git-master/r/34464
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R3c04d3971a69620c0fc3dffbcd63852d6d0b6080

5 years agoarm: tegra: disable lp0 on tegra3 A01 if it is enabled
Luke Huang [Wed, 25 May 2011 00:51:05 +0000]
arm: tegra: disable lp0 on tegra3 A01 if it is enabled

Always change to LP1 even if the default is set to LP0 for Tegra3 A01
since LP0 cannot be supported for this chip revision.

Bug 789450 782781

Original-Change-Id: I2d62cf458050fcdcdded1fc5bfc08fdb2d09844c
Reviewed-on: http://git-master/r/32852
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R904999681a1c35deabb685531843c6c39ba3748e

5 years agoarm: tegra: fuse: add function to get chipid
Luke Huang [Fri, 20 May 2011 21:20:42 +0000]
arm: tegra: fuse: add function to get chipid

1. Add the function to return chipid.
2. Remove the if-def for A01 for tegra2 and add kernel panic if tegra2-A01 is
detected.
3. Clean up errors/warnings reported by checkpatch.pl.

Original-Change-Id: I0aa4ed2c4fd77e8e5ae83feceee94372b1506446
Reviewed-on: http://git-master/r/32450
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R7e4adad9e8127d725ebae51bc308ace382bebc3e

5 years agoarm: tegra: add tegra_i2s_device0
Tom Cherry [Fri, 27 May 2011 01:41:45 +0000]
arm: tegra: add tegra_i2s_device0

Original-Change-Id: I788d41d7c9880e29031d50b3d8829953cbc38f4f
Reviewed-on: http://git-master/r/34239
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Raecd6f7dfd3d2bd398e49100d5c1f8848f9d2f67

5 years agoarm: tegra: pinmux: debugfs: Handling INVALID pinmux option
Laxman Dewangan [Sat, 28 May 2011 14:12:54 +0000]
arm: tegra: pinmux: debugfs: Handling INVALID pinmux option

When any pinmux is selected as INVALID option, may be POR, taking
dump of pinmux through debugfs interface is displaying junk character/
crashing the kernel.

Fixing this issue by handling correctly the INVALID option.

Original-Change-Id: I32c0ad0ba12ea44bc8fd1e2ec2ccb50269210f67
Reviewed-on: http://git-master/r/34429
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R4f7f4f9af4640b0858c384ce4982317635b8b6ad

5 years agoarm: tegra: Change Tegra3 L2 cache prefetch to next line
Scott Williams [Thu, 26 May 2011 20:20:13 +0000]
arm: tegra: Change Tegra3 L2 cache prefetch to next line

Change L2 cache prefetch offset from 8th line to next line.

Original-Change-Id: Ie88008e2ab5a882235ae91d71d193e898ca67121
Reviewed-on: http://git-master/r/33195
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R3826be5d5531d275a624193f3063372552b05743

5 years agoarm: tegra: Clean up SOC conditionals
Scott Williams [Tue, 24 May 2011 05:08:42 +0000]
arm: tegra: Clean up SOC conditionals

Change SOC conditionals to make them more forward-looking.

Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R77c675a1995116098b58f1f775bc7c3cc8722998

5 years agoARM: tegra: clocks: Completely remove DVFS for FPGA platforms
Scott Williams [Sat, 21 May 2011 00:33:06 +0000]
ARM: tegra: clocks: Completely remove DVFS for FPGA platforms

Dynamic Voltage & Frequency Scaling (DVFS) is not possible on
FPGA platforms. Completely remove the DVFS code from the image
on FPGA platforms to reduce the image size.

Original-Change-Id: I4f1a8587f01e775000f48fbca7c85d75acee9c74
Reviewed-on: http://git-master/r/32466
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R08c78dd7e7bfe891a3d48de16f5a863ad5d07999

5 years agoARM: tegra: power: Update CPU EDP initialization
Alex Frid [Wed, 25 May 2011 02:02:16 +0000]
ARM: tegra: power: Update CPU EDP initialization

Do not overwrite thermal zone and preserve boot CPU rate settings if
thermal sensor is initialized before edp governor.

Original-Change-Id: Ia705d5f453003c204459f594ffb95152ff74145f
Reviewed-on: http://git-master/r/32861
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rfae7a16b2a93b9b294d8b70191c57a9a2e7374fc

5 years agoARM: tegra: dvfs: Fix uninitialized variable use
Alex Frid [Tue, 24 May 2011 21:50:13 +0000]
ARM: tegra: dvfs: Fix uninitialized variable use

Completing fix started by 68e857d94f35286b9b359feef1e1dddc7e2aea8b.

Original-Change-Id: I61e9051da3d7aacd460d15ef8ff161b678c8fec1
Reviewed-on: http://git-master/r/32829
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>

Rebase-Id: R352e5430825dd246eb7c8242b78f04699273f8e6

5 years agoARM: tegra: clock: Fix speedo_id eval for max speedo value
Diwakar Tundlam [Fri, 20 May 2011 23:51:48 +0000]
ARM: tegra: clock: Fix speedo_id eval for max speedo value

Original-Change-Id: Ia36ea70b054262772df39650b5fdc7419be2bfcf
Reviewed-on: http://git-master/r/32802
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R90d4deb23bca5ba6bad270c6c6eb54a851ae6a6f

5 years agoarm: tegra: cardhu: Enabling Security Engine
Kasoju Mallikarjun [Tue, 24 May 2011 14:38:38 +0000]
arm: tegra: cardhu: Enabling Security Engine

bug 622025

Original-Change-Id: Ic01ad6e93a26b332e016fcef6dbc928918c25745
Reviewed-on: http://git-master/r/29952
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R3e82736c3e8fbe32ed222fcdcc7e54328a49aa91

5 years ago[ARM]: tegra: kfuse: enable/disable kfuse clock when needed
Mayuresh Kulkarni [Wed, 4 May 2011 08:06:03 +0000]
[ARM]: tegra: kfuse: enable/disable kfuse clock when needed

clock to kfuse is turned ON during boot-up which is not needed. hence
turn it on when needed and turn it off after use.

for bug 819505

Original-Change-Id: I3b0bd3ee295b4998d6d6f747a946ca28bd9550a5
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/30333
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R41acd5bc222e2041d7364997b6fdaa9c31c1ddb2

5 years agoARM: tegra: power: Fix warnings when CONFIG_PM is disabled
Scott Williams [Fri, 20 May 2011 23:08:58 +0000]
ARM: tegra: power: Fix warnings when CONFIG_PM is disabled

Original-Change-Id: I9d4b8c218cdfe6a91424b808f70c1ec056015783
Reviewed-on: http://git-master/r/32463
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R45bbed19108386e72f1057d09d13290a8bec2c17

5 years agoARM: tegra: clock: Set speedo_id according to actual fused SKU
Diwakar Tundlam [Wed, 18 May 2011 23:58:03 +0000]
ARM: tegra: clock: Set speedo_id according to actual fused SKU

- Read SKU_INFO fuse to get A02 SKU info
- Update CPU DVFS to use actual SKU info obtained
- Enable main table for EDP capping and thermal throttling

Original-Change-Id: I7ff3b06476998d77cc3f7a4fc03fb72e26b570db
Reviewed-on: http://git-master/r/32084
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Re91f616032d8045ea2c28822e40f815f3e449931

5 years agoARM: tegra: Block selection of unavailable FPGA features
Scott Williams [Wed, 18 May 2011 02:18:54 +0000]
ARM: tegra: Block selection of unavailable FPGA features

Certain power management features will not work on FPGA platforms.
Therefore, do not allow them to be selected.

Original-Change-Id: Icf33a6797fef6c921c2ce9a2096380338822353c
Reviewed-on: http://git-master/r/32244
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R46a74328085c8586d375584ca36df6e15322e8a2

5 years agoarm: tegra: Declare tegra_throttling_enable in .h
Robert Morell [Thu, 19 May 2011 16:31:45 +0000]
arm: tegra: Declare tegra_throttling_enable in .h

The build currently fails for some boards when CONFIG_CPU_FREQ=n, since
we don't build cpu-tegra.c but tegra_throttling_enable is still
referenced.  To fix this:
- Add cpu-tegra.h
- Define tegra_throttling_enable to NULL in the header if either
  CONFIG_CPU_FREQ or CONFIG_TEGRA_THERMAL_THROTTLE are not set
- Use the header file instead of declaring the function extern
  everywhere it's used

Bug 829501

Original-Change-Id: Ice84309546dee201f991a1194fefd80583afc455
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/32208
Reviewed-by: Allen R Martin <amartin@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Reda9651e2395231d5b1ec7150885d3d9f66ca16b

5 years agoarm: tegra: irq: fix wake level programming
Luke Huang [Wed, 18 May 2011 22:07:20 +0000]
arm: tegra: irq: fix wake level programming

After toggeling the latchwake_en bit, the status of wake event is latched to
pmc_sw_wake_status, not pmc_wake_status. Adding a new function to read out
from the proper register.

Original-Change-Id: Ib1478504fd16197afe3a2b676833f9ce7f6f7528
Reviewed-on: http://git-master/r/32078
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R371f4cecd474e8e1673e7ae6c465d7907998413f

5 years agotegra: dvfs: fix unintialized variable use
David Schalig [Wed, 18 May 2011 10:00:47 +0000]
tegra: dvfs: fix unintialized variable use

Assignment moved inside if statement, where it belongs.

bug 828756

Original-Change-Id: I6e1c621a8c4d64b9b5a43df1e79992863fe3d514
Reviewed-on: http://git-master/r/31984
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R6c935302ff60ed4029d4cb775cf2b851418577ca

5 years agoARM: Tegra: Support to update edp zones
Varun Wadekar [Thu, 12 May 2011 08:49:03 +0000]
ARM: Tegra: Support to update edp zones

Tegra cpu-freq driver will now recognize edp zones
and cap the max cpu freq for that zone. The temperature
monitoring driver will be giving inputs to cpu-freq
on the current temperature which would be interpreted
by the cpu-freq driver appropriately.

Original-Change-Id: I918eb31771aa7e1e1a5f25438edded727de6eb8c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/31339
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R6d93bf69d0731ce4ae84f80d1e9013378483331c

5 years agoARM: tegra: power: Enable Tegra3 core DVFS
Alex Frid [Wed, 11 May 2011 23:01:44 +0000]
ARM: tegra: power: Enable Tegra3 core DVFS

Enable Tegra3 core DVFS with default EDP limit set to 1.2V.

Bug 812738
Bug 826200

Original-Change-Id: If1e9f431729d0dbe6e8c89d9d8b9d5f9d2e8a2bf
Reviewed-on: http://git-master/r/31254
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3f6a3633f77b33541171c28078401a0fa51b432c

5 years agoARM: tegra: power: Enable Tegra3 CPU EDP by default
Alex Frid [Fri, 13 May 2011 22:01:53 +0000]
ARM: tegra: power: Enable Tegra3 CPU EDP by default

Original-Change-Id: I62ad3b3b7e0b4feba223c0dfe5792194aea6e4cd
Reviewed-on: http://git-master/r/31616
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rfac317c3ff2f26a6c5377efe8693996d245df7a6

5 years agoarm: tegra: power: Fix build break when CONFIG_PM disabled
Scott Williams [Tue, 17 May 2011 20:40:27 +0000]
arm: tegra: power: Fix build break when CONFIG_PM disabled

The code to select LP0/LP1 low-power mode via a sysfs node does
not compile if CONFIG_PM is disabled. This fixes that error.

Original-Change-Id: If166759bd89f03335bca529cbe50a32420f802f6
Reviewed-on: http://git-master/r/31903
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Ra9bab01ed156e683feae6f906a7b8ecb4f7bf3c6

5 years agoARM: tegra: Check if the cpu already booted or not
vjagadish [Fri, 6 May 2011 07:04:11 +0000]
ARM: tegra: Check if the cpu already booted or not

Check the CPU is ever booted before entering into
powerup status confirmation loop.

BUG 824307

Original-Change-Id: I474d0536b00e84967a240037d2ed984a889dd2e0
Reviewed-on: http://git-master/r/30679
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
Tested-by: Venkata Jagadish <vjagadish@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R2346bcc108f59eae21cc98a311b95dc702c0a57e

5 years agoarm: tegra: devices: Adding device details for tegra kbc
Alok Chauhan [Mon, 16 May 2011 16:17:34 +0000]
arm: tegra: devices: Adding device details for tegra kbc

Adding device details for the tegra based kbc driver.

Bug 827020

Original-Change-Id: I47b150fc97f97ce91c1de569aec067ad2e5f0660
Reviewed-on: http://git-master/r/31725
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Ra1a6e6dc6477cf1deae0b84dc3911b8ccfd9bbb8

5 years agoARM: tegra: power: Add suspend index to cpufreq table
Alex Frid [Fri, 13 May 2011 03:20:05 +0000]
ARM: tegra: power: Add suspend index to cpufreq table

Original-Change-Id: I7bbe018f3786b9683cc9d4189fdcaadb9098f3f1
Reviewed-on: http://git-master/r/31456
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R81da4e2834a9ae209aadba17337d484f26f67ada

5 years agoARM: tegra: power LP0/LP1 selection via sysfs
Karan Jhavar [Mon, 2 May 2011 20:32:57 +0000]
ARM: tegra: power LP0/LP1 selection via sysfs

Select LP0/LP1 on runtime using sysfs node /sys/power/suspend/type.
Valid selctions/commands are:
1. lp0
2. lp1
3. lp2

Original-Change-Id: I335a8845dbfed7539ae4bf8aee3ba3b97ecb3db3
Reviewed-on: http://git-master/r/30081
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R48e0a05f4d5c6637831834a350650f4a828f402e

5 years agoARM: tegra: clock: Enable clock while setting rate/parent
Alex Frid [Sun, 15 May 2011 01:58:34 +0000]
ARM: tegra: clock: Enable clock while setting rate/parent

When clock configuration (source mux, divider value) changes, the new
control register setting does not take effect if clock is disabled.
Later, when the clock is enabled it would run for several cycles on
the old configuration before switching to the new one. This h/w
behavior creates two problems:

- since dvfs takes into account only new (enabled) rate, the module
can be over-clocked during initial phase of the clock switch
- since parent clock refcount is updated when the mux register was
written, the parent clock maybe disabled by the time of actual switch
and h/w would not be able to complete switch at all

To avoid described problems clock is now always enabled while setting
the new rate/parent (and disabled afterwards to keep refcount intact).

Original-Change-Id: I9bda56a2a98c9f3678715da1e1b8fe78874fb71e
Reviewed-on: http://git-master/r/31640
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R9964ee8633a54e55e5b26d578487a6d0e02c4fe4

5 years agoarm: tegra: nvmap: Forcing to convert CarveOut requests to IOVM
Hiro Sugawara [Thu, 17 Mar 2011 20:58:13 +0000]
arm: tegra: nvmap: Forcing to convert CarveOut requests to IOVM

Adding a build time CONFIG option to enable forcing of conversion
of non-IRAM CarveOut memory allocation requests to IOVM requests.
Default is "y" to force the conversion.
Each forced conversion is reported to console.
Allocation alignments larger than page size for IOVM are enabled.
Single page CarveOut allocations are converted to system memory.
CarveOut memory reservation has been removed for aruba, cardhu,
and enterprise.

Original-Change-Id: I3a598431d15b92ce853b3bec97be4b583d021264
Reviewed-on: http://git-master/r/29849
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Reaf79d5ef57d3be8f2dc572de1919e854a117114

5 years agomedia: tegra: avp: Use SMMU to load AVP kernel
Kaz Fukuoka [Thu, 21 Apr 2011 01:53:42 +0000]
media: tegra: avp: Use SMMU to load AVP kernel

- Use nvrm_avp_e0000000.bin is for Tegra3 A01
- Use nvrm_avp_00001000.bin is for Tegra3 A02 and later

bug 765965

Original-Change-Id: I9bc28b122bd1b0cd2c1ece3bc681550de5912229
Reviewed-on: http://git-master/r/31202
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: R0e31e84ba66320176135096526fe73a5367a126f

5 years agoARM: tegra: power: Set Tegra3 CPU/core rail nominal voltage
Alex Frid [Sun, 8 May 2011 04:01:24 +0000]
ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltage

For different Tegra3 process corners/skus/revisions/boards set nominal
voltages for CPU and core rails as well as adjust maximum clock rates
as follows.

- VDD_CORE rail nominal voltage: default value is indexed by speedo_id
of the chip (speedo_id is determined by chip sku and revision). Minimum
of the default and board specific electrical design voltage is rounded
down against core dvfs voltage ladder. The result is set as nominal
core voltage (edp voltage API is not implemented, yet).

- VDD_CPU rail nominal voltage: default value is indexed by speedo_id
of the chip. If too high, it is lowered to core nominal voltage so that
core_on_cpu dependency is resolved at nominal core level. The result is
compared with voltage required to reach CPU maximum rate as specified
in the dvfs table for the particular process corner. Again, the minimal
level is selected, and finally set as CPU nominal voltage.

After nominal voltages are determined, maximum rate for each dvfs clock
is adjusted accordingly, so that it does not exceed the rate specified
in the respective DVFS table at nominal level.

Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3
Reviewed-on: http://git-master/r/30928
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: R30393515042d199154ba708afaefb134402f551a

5 years agoARM: tegra: restore voltage to nominal when reboot
Bo Yan [Mon, 2 May 2011 22:00:26 +0000]
ARM: tegra: restore voltage to nominal when reboot

At the time of reboot, all rails need to be set to nominal to ensure
the success of subsequent boot.

bug 821969   bug 797082

Original-Change-Id: Iee635c222619dfcb3e98f13e665ea2bd04e94245
Reviewed-on: http://git-master/r/30086
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Racbc707a55e92261310e956707a850df1db00f72

5 years agoarm: tegra: Support for core_edp and panel type from kernel command.
Laxman Dewangan [Mon, 9 May 2011 13:45:29 +0000]
arm: tegra: Support for core_edp and panel type from kernel command.

Selecting the core EDP voltage and panel type from the kernel commands.
The bootloader pass this information through kernel command.

Board will select the default configuration if there is no command option
for these parameters.

bug 822053

Original-Change-Id: Id7909d70b599c4a313d60d3ba2a9cf5b9eb7f2c3
Reviewed-on: http://git-master/r/30853
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R168653eae3bd5965bcbef2cde3ba26c8dace8f23

5 years agoARM: tegra: fuse: fix sysfs programming/reading logic
Varun Wadekar [Tue, 3 May 2011 04:10:11 +0000]
ARM: tegra: fuse: fix sysfs programming/reading logic

some testing revealed certain loopholes in the
code. also the way the shell sends data down to
the sysfs handlers changed which warranted the
change in the handlers.

Original change: http://git-master/r/#change,30134
(cherry picked from commit 64671e8dd11779b04e71048551cabfa8b04e3bb9)

Original-Change-Id: Iccd02bd5a257312fd8ef764980005edaf28db0a7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/30454
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R2f9ad21f95516466efaaa4eeb77ce77f066b19cd

5 years agoARM: tegra: implement events for clock tracing
Peter De Schrijver [Mon, 2 May 2011 12:54:27 +0000]
ARM: tegra: implement events for clock tracing

Original-Change-Id: If6ae23251aa615a678c8edb76d3c1e6463d86f2e

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Original-Change-Id: I50ffa54eacaf5b3973fcd6cb94eee56e46ec81bf
Reviewed-on: http://git-master/r/30384
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc05e6b5e44c3d337d718d2e62c91a06d4558d044

5 years agoARM: tegra: power: Add Tegra3 CPU/CORE rails dependencies
Alex Frid [Sun, 1 May 2011 06:23:42 +0000]
ARM: tegra: power: Add Tegra3 CPU/CORE rails dependencies

On Tegra3 VDD_CPU must be within [VDD_CORE - 300, VDD_CORE] range.
Updated tegra dvfs accordingly, and resolved circular dependencies
between CPU and CORE rails created by this requirement.

Original-Change-Id: I9c332ca2b4f4ed1599cb0712eb3eca55a1fa1539
Reviewed-on: http://git-master/r/29935
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R6aa2bc61513ab16c4551ebeb193e01803501f596

5 years agoarm:tegra: Do not power gate PCIE for tegra 3x SOC
Narendra Damahe [Fri, 29 Apr 2011 19:09:25 +0000]
arm:tegra: Do not power gate  PCIE for tegra 3x SOC

Power gating of PCIE will be separately handled for 3x SOC.
This is to fix bug 821213

Original-Change-Id: Id511778f4c3422ee9d92a2c77686803e09704ee4
Reviewed-on: http://git-master/r/29868
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra7ea317b419601288decf6ba314ad44dde0c3f0a

5 years agoarm: tegra: Fix wrong parameter to boot error message
Hiro Sugawara [Fri, 29 Apr 2011 18:59:37 +0000]
arm: tegra: Fix wrong parameter to boot error message

This makes up disregarded objection in change 29149.

Original-Change-Id: If8c83471719c743e2a74f4fb0ee8c34240498b7b
Reviewed-on: http://git-master/r/29863
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R96ba60f7918ff09614ac93e5ea024af51afc11ea

5 years agocrypto: tegra-aes: dual core support
Sanjay Singh Rawat [Thu, 28 Apr 2011 13:25:57 +0000]
crypto: tegra-aes: dual core support

* add bsea engine support for encryption and decryption
* add arbitration semaphore id for bsea

Bug 803932

Original change: http://git-master/r/#change,29672
(cherry picked from commit 0008cdb0f38d0cd0c074671fc067c4321f340b06)

Original-Change-Id: I59fcaab29c47a8b42e7470b30486851cfe90848f
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/30190
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rb63b593aa4fe4b4d4f3607ac9471ae7e7372407a

5 years agoARM: tegra: powergate: Add hot reset sequence for powergate
Jin Qian [Thu, 21 Apr 2011 19:55:47 +0000]
ARM: tegra: powergate: Add hot reset sequence for powergate

Original-Change-Id: I0e37b788c666ae99f46e7e6995c3700b0b23d412
Reviewed-on: http://git-master/r/29901
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R24afa8e7f33265722cee139f37ad53774d1dcb96

5 years agoARM: tegra: Add EMC to DDR clock ratio config option
Alex Frid [Wed, 4 May 2011 05:34:22 +0000]
ARM: tegra: Add EMC to DDR clock ratio config option

Original-Change-Id: Ib5b7c99b483785b84ece0662ae5e9e58227d257f
Reviewed-on: http://git-master/r/30309
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>

Rebase-Id: Rbe52fcf6868d3b19a5c42d7074f977f55c8c9cae

5 years agoARM: tegra: clocks: make pclk div dynamic
Prashant Gaikwad [Thu, 28 Apr 2011 10:18:44 +0000]
ARM: tegra: clocks: make pclk div dynamic

dynamic changing of pclk divider to follow APB clock minimum
frequency requirements with respect to sclk frequency.

Bug 819796

Original-Change-Id: Id6d4f9321fe3d49922ace9b50cb6e5114f63b9b5
Reviewed-on: http://git-master/r/29643
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb722438f9370900d4536ef9e09a6bcad29521ce0

5 years agoARM: tegra: clock: Remove "sole parent" requirement
Alex Frid [Tue, 26 Apr 2011 04:21:30 +0000]
ARM: tegra: clock: Remove "sole parent" requirement

During dvfs initialization, change propagation of sleeping attribute
from "current_parent-to-child" to "possible_parent-to-child". This would
guarantee that any non-sleeping clock has only non-sleeping parents, and
it is no longer required for sleeping clock to be a sole parent of all
its children.

Original-Change-Id: I11110f6cb9c538c1e71bf00195c3f49dd09ea1f7
Reviewed-on: http://git-master/r/29706
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3916f7d951cc3ea8b80d9e22a8200f45ec54fa3d

5 years agoARM: tegra: clock: Show cansleep attribute in clock tree
Alex Frid [Tue, 26 Apr 2011 00:57:36 +0000]
ARM: tegra: clock: Show cansleep attribute in clock tree

Original-Change-Id: Iff900aa5b69329696bcd250c824e0a191f6f6299
Reviewed-on: http://git-master/r/29705
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc93662daa81d9cf5ba656b81958f95241c259b47

5 years agoARM: tegra: clock: Clip Tegra3 CPU mode rate limits
Alex Frid [Sat, 23 Apr 2011 02:41:41 +0000]
ARM: tegra: clock: Clip Tegra3 CPU mode rate limits

Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate
are clipped to the entries in cpufreq scaling table.

Original-Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07
Reviewed-on: http://git-master/r/29703
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R99b548e992c80e4850e6d7f9443db8f7d7134956

5 years agoARM: tegra: power: Check Tegra3 auto-hotplug speed balance
Alex Frid [Fri, 22 Apr 2011 04:33:12 +0000]
ARM: tegra: power: Check Tegra3 auto-hotplug speed balance

When current CPU complex frequency is above target range:
- bring new core on-line only if cpufreq governor requests for
all already on-lined CPUs are above 50% of current CPU frequency
- off-line one core (despite high pick request) if cpufreq
governor requests for at least 2 on-lined CPUs are below 25% of
current CPU frequency
- do nothing if neither of the above conditions is true

Original-Change-Id: I77e1bd543a8fadd51974f7d574f256a6e7e2979a
Reviewed-on: http://git-master/r/29702
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc5c717454d1e09ca97ccc79fff60cb33fcf854e9

5 years agoarm: tegra3: Updating pinmux table based on TRM
Laxman Dewangan [Mon, 25 Apr 2011 06:44:31 +0000]
arm: tegra3: Updating pinmux table based on TRM

On tegra3 TRM, some of the pin mux option for a given
pin group is not recommended and so not exposed in the
TRM reference table.

Updating the pinmux table accordingly. The non-recommended
pin option is set as TEGRA_MUX_INVALID.

bug 817099

Original-Change-Id: I572ee84912fe065a73e59d4f9ba0ce01223ead85
Reviewed-on: http://git-master/r/29626
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R88ad8a84c4516c8692b9266d6c073f20e35b420e

5 years agoARM: tegra: correcting vde resource end field
Sanjay Singh Rawat [Mon, 25 Apr 2011 09:57:25 +0000]
ARM: tegra: correcting vde resource end field

Original-Change-Id: I3b71ff1a57093f7e4bba311cb5632c200a80666c
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28651
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R5987a45cb62bfb22861438539125e71a4788e8a1

5 years agoARM: tegra: Decode optional chip-private feature string in cmd line
Hiro Sugawara [Thu, 14 Apr 2011 17:41:06 +0000]
ARM: tegra: Decode optional chip-private feature string in cmd line

ap20 needs to distinguish between A03 and A03p revisions.

Original-Change-Id: I726d45f5ea3c5283ae11057f01c86038eb6c2872
Reviewed-on: http://git-master/r/27777
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If14b6330ccd8bb6420e0c9118291414cc383b94d

Rebase-Id: R60cae4b7b2061deeedd0cabaa6bf95f2f379514a

5 years agoARM: tegra: power: Update Tegra3 CPU auto-hotplug
Alex Frid [Wed, 20 Apr 2011 06:38:46 +0000]
ARM: tegra: power: Update Tegra3 CPU auto-hotplug

- taking CPU core off-line: selected CPU with minimum load
- switching from ULP to G CPU mode: set CPU clock to cpufreq
target rate after the mode switch is completed

Original-Change-Id: I9bf4d0f4b48c262cf678c603aac02043dd602674
Reviewed-on: http://git-master/r/28420
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I5a19be79dd8f8fe788637870a22cd34dcfea150e

Rebase-Id: Re264ec676c5c2103f7738c9eab5f4e11a4344975

5 years agoARM: tegra: power: Set minimum LP2 target residency
Alex Frid [Tue, 19 Apr 2011 04:35:58 +0000]
ARM: tegra: power: Set minimum LP2 target residency

Added board level tuning parameter to specify minimum LP2 residency
time (previous policy allows down to zero residency targets limited
only by LP2 exit latency).

Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22
Reviewed-on: http://git-master/r/28162
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6

Rebase-Id: Rcf9efce3dd037b0a7ca13a9c342f884fac38d654

5 years agoARM: tegra: Use proper type for physical addresses
Scott Williams [Wed, 13 Apr 2011 00:47:52 +0000]
ARM: tegra: Use proper type for physical addresses

Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496
Reviewed-on: http://git-master/r/27559
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1

Rebase-Id: R070df1711ad7b02dd9dbe17edad01e13c91a3615

5 years agoARM: tegra: timer: Clean up Tegra2 timer code
Scott Williams [Tue, 12 Apr 2011 00:10:54 +0000]
ARM: tegra: timer: Clean up Tegra2 timer code

Remove extraneous code.
Clean up timer register addresses.

Original-Change-Id: I459e5b1aa7062d8454b5c064354fe71ef3a737d4
Reviewed-on: http://git-master/r/27444
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I353886d350bb8389aa12dc2da03b3a3c5a0cc7ca

Rebase-Id: R39fb8dac614aeefb1d337c4b5d817038b4ea65d6

5 years agoARM: tegra: Fix sizeATaddr display order in error message.
Hiro Sugawara [Fri, 8 Apr 2011 20:21:02 +0000]
ARM: tegra: Fix sizeATaddr display order in error message.

Also move a local variable into a closed block.

Original-Change-Id: Ifca24c640c917d3a86c27da526c482ec0b6abeb2
Reviewed-on: http://git-master/r/27241
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Original-Change-Id: I24c57262a0e6f2b32c11e4786cc5a56b9ffe866b

Rebase-Id: R8f93d4507562402fd3394276d9745738706141f3

5 years agoARM: tegra: power: Re-initialize Tegra3 EMC after LP0
Alex Frid [Wed, 6 Apr 2011 03:24:36 +0000]
ARM: tegra: power: Re-initialize Tegra3 EMC after LP0

Since EMC frequency is not restored after exit from LP0, re-initialize
EMC clock with the new warm boot configuration, and make sure that the
1st after LP0 clock change does not use stale timing cache.

Skip Tegra2 specific EMC restoration on Tegra3 platforms.

Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2
Reviewed-on: http://git-master/r/26807
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406

Rebase-Id: Rb3fcd60c0c674e10d41d4cdc4d8e53a6e124a5bf

5 years agoARM: tegra: power: Add CPU EDP support
Alex Frid [Thu, 7 Apr 2011 03:43:55 +0000]
ARM: tegra: power: Add CPU EDP support

CPU electrical design point (EDP) limits specify maximum CPU frequency
depending on number of CPU cores on-line, and chip temperature. This
commit added initial edp governor to cpufreq driver. Governor is aware
of CPU departure/arrival, but temperature dependency is yet to be added.
Therefore CPU EDP support is left disabled for now.

Original-Change-Id: Ia875aa6904df7ec25ac98863d59a173703034241
Reviewed-on: http://git-master/r/26982
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iae2e9d47c2d3fd4cb32104adbad4f4b26c46064c

Rebase-Id: Rde24788e86558e1c21b18a1857a8b52220ba8e2a

5 years agoARM: tegra: power: add partition power check before suspend
Jin Qian [Wed, 16 Mar 2011 19:30:41 +0000]
ARM: tegra: power: add partition power check before suspend

Original-Change-Id: Ie4b29d1119bc2f640891525ab781c8de1bf64ddf
Reviewed-on: http://git-master/r/23215
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Idc616485ecdb9e7c39728409d91a511e1de79e05

Rebase-Id: Rd61725b233749ea76467686439b92ac22b65f424

5 years agoARM: tegra: clock: Modify EMC maximum rate settings
Alex Frid [Tue, 5 Apr 2011 23:45:05 +0000]
ARM: tegra: clock: Modify EMC maximum rate settings

On A01 Tegra3 chip EMC rate may not reach full PLLM range - set
maximum EMC rate equal to boot rate. Use PLLM frequency as EMC
rate limit for A02+ chips.

Original-Change-Id: I0b901a29d628362b09f2a3d0ce908b4019804cfd
Reviewed-on: http://git-master/r/26786
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I741fcfca646ba0a2a8732dbccaf7a2642d839809

Rebase-Id: R9b5913cccecc96221c1541887e6e3b03a8f1316a

5 years agoARM: tegra: clock: Updated EMC clock change procedure
Alex Frid [Fri, 1 Apr 2011 06:18:11 +0000]
ARM: tegra: clock: Updated EMC clock change procedure

Original-Change-Id: I0fad4b8d931b92c8dbbdd3b6ce7dd63b42c6464f
Reviewed-on: http://git-master/r/25177
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I109a5cff6b53cfea4b48b20c9114aa4a1c02f1d8

Rebase-Id: R6416c2a2c2c1dc1fd8619842b91fea24ae10b675

5 years agoARM: tegra: irqs.h simplification
Scott Williams [Wed, 6 Apr 2011 00:53:15 +0000]
ARM: tegra: irqs.h simplification

Original-Change-Id: I8f344d368a501c7bb3c0eba6cecabd7c48a6c9a2

Rebase-Id: Rcd1b8d194e030c536d7395d8e406385f58e77489

5 years agoarm: tegra: iovmm: Move SMMU window to bottom 1GB for AVP
Hiro Sugawara [Thu, 17 Mar 2011 18:19:29 +0000]
arm: tegra: iovmm: Move SMMU window to bottom 1GB for AVP

Tegra3 A01 continues to use the high address range.
Tegra3 A02 (and after) uses the bottom 1GB.
The new AHB register bit access has no effect to Tegra3 A01.

Original-Change-Id: I90cedbb22d9aae4307908750ebeb03bef639945c
Reviewed-on: http://git-master/r/23379
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I33253f8ae32c416a9d19694e87380dbae94c2f68

Rebase-Id: Rf2d058998ea09fcbe44fe3c61493a46938505c0b