Revert "ARM: Revert "ARM: 6878/1: fix personality flag propagation across an exec""

This reverts commit 25cd08cd1fb5888fe0d9bcc1e58b9d6b8378e1fd.
ADDR_COMPAT_LAYOUT is set on zygote to prevent Unity games from
crashing in K3.4. However, since the propagation of personality was
disabled, this flag never ended up being set on the fork()ed
processes.

Additionally, in order to prevent Bug 894472 to resurface with this
revert, mask out READ_IMPLIES_EXEC from being propagated to child
processes.

Bug 1023189

Change-Id: I01d5b7b3778b9e99815146bd2345bda1266e6309
Signed-off-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-on: http://git-master/r/168956
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Liang Cheng (SW) <licheng@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

ARM: Tegra: Turn off SD phase in for T114

Recently, on T114 we enabled SD updates on vpulse2 instead of
vblank. As a result, it no longer necessary to have
software or hardware phase in enabled.

Bug 1156207

Reviewed-on: http://git-master/r/166641

Change-Id: Ib398284cb708ad212ea22772bc454092036bc329
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/164163
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arm: tegra: isomgr: Init isomgr early.

Init isomgr earlier than device drivers.

Change-Id: I9b8b080a9f0e72ebae91c0557270624ac030d883
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/171166
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra11: clock: Fix XUSB HS clock initialization

XUSB HS clock initialization overwrote XUSB SS clock source settings
(both clocks share the source register). This is fixed now.

Change-Id: I722e55933534a954fde1012d88907ab7340dc81d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171272
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

ARM: mm: Remove unnecessary CMO in Cortex A15 startup

Cortex-A15 flush L2 cache after reset, there is no need to do this
in software, if L2 is already invalidated in bootloader and
cache is disabled. For secondary startup, there is no reason to
flush L2 as well.

This change assumes the setup code is always entered as the result
of CPU reset.

Change-Id: I6d58f8b4a638b70acfb35b97c87a09266aceef41
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/170563
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

ARM: Tegra: Roth: Update Configs for New Boards

Update KBC and Left Speaker for A01 P2454 and A02 P2453

Change-Id: I39782086d8b257b8570456580a01f64a7185b991
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/170969
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

asoc:tegra: fix dam cif programming

as per dam spec file chout is fixed to 32bits
so accept chout and ch1 input as 32bit always.

Change-Id: If1de02c2634fca45b4ffc1a51b8f75161e5a2645
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/170931
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Scott Peterson <speterson@nvidia.com>

cdc_ncm: fix bind failures for Icera devices

The Icera 5AN, 5AN BSD, and Nemo devices are composite devices that
include a NCM interface. Therefore, the NCM match flags should have
the VID, PID, Class, Subclass, and Protocol set to avoid bind()
failures for non-NCM interfaces.

Bug 1197415

Change-Id: If68a6ffaa4e1871c6a22ec8839806949804f502c
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/170576
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
Tested-by: David Norman <dnorman@nvidia.com>

power: max17042: added shutdown functionality

Change-Id: Ie0ec4e2970c645decde1c50e9858c9d4b2c41fd8
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/164812
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: t114: pinmux lp0 sequence with NOR_BOOT fix

Programming pinmux to avoid pad glitches during LP0.
Added fix for NOR_BOOT hang issue.

Bug 1053587

Change-Id: I6338f2e4fa621f2216dbe83e7bcccca4567973be
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/161226
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

arm: errata: 761320: Full cache line writes to the same memory region from at least two processors might deadlock processor

Under very rare circumstances, full cache line writes
from (at least) 2 processors on cache lines in hazard with
other requests may cause arbitration issues in the SCU,
leading to processor deadlock. This erratum can be
worked around by setting bit[21] of the undocumented
Diagnostic Control Register to 1.

Change-Id: I83f919ead5ef4f90f50fa3f38f2cc31ab6bfc31e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/170582
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

ARM: tegra11: clock: Optimize traversing EMC DFS table

Used last rounded EMC DFS table index to skip unnecessary
looping through the table.

Bug 1188643

Change-Id: I0dad723f2f6f58258fd79e33d95d7502ff0abf67
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170605
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM: tegra11: clock: Skip lowering voltage on EMC backup

If EMC backup rate is below current rate, skip lowering voltage when
switching to backup clock source, Final voltage will be set correctly
after main clock source is re-locked, and EMC clock is switched to
main source.

Bug 1188643

Change-Id: I82a4a85449dbd589c7692f6640e1bd5e08e0bc9b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170604
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arm: tegra: enable arm errata 761320 for T2 and T3.

Change-Id: Ifc5b2344875b33eccdc30896255f88b7c6b3bd47
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/170583
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

ARM: tegra: Rework timer for clusterswitching

This patch introduces a separate timer for clusterswitching. The timer will
queue the usual workitem on expiry. This allows all other operations to
happen immediately without having to cancel a delayed workitem. It also allows
the timer itself to be canceled when the conditions for a clusterswitch are
no longer fulfilled.

bug 1178947

Change-Id: Ieb63baf5a38ebcca29ad938365e46530f755a105
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/170533
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

regulator: bq24192: Disable supply by default

Disable voltage supply by default.

Bug 1179219

Change-Id: I6b157c7146f7a014099e9a142461b9130a7e3da1
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/170130
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: pluto: fix LP0 resume handling error for wake0

During resume from LP0 due to MDM_COLDBOOT going low,
tegra_wake_to_irq() returns an error after seeing -EINVAL at index
0 of the tegra_wake_event_irq array. Since a gpio wake source is
mapped to index 0 in the tegra_gpio_wakes array, the value should
be -EAGAIN.

Bug 1195187

Change-Id: I534002727f0956867d5fdb182af2e63c1f023f0e
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/169809
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

arm: tegra: isomgr: cleanup isomgr implementation.

Add more comments.

Change-Id: I42ea1accfac673231224b522fc4d41cf23837562
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/169778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

ARM: tegra: gizmo: Fix prefetch CFG5 address

Fixing prefetch CFG_5 register address offset
Using AHB prefetcher for SDMMC only on T114 and
T148 SOCs. SDMMC controller is removed from AHB
interface in later versions of Tegra.

Bug 1188541

Change-Id: Id74dc3839b80e0e394a589916d0669ae935125ef
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/169657
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

ARM: tegra: dalmore: update emc DVFS table

Bug 1189313

Change-Id: I17db9a8cfd896e2125d495d74f9fc61d4ce2729f
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/168927
Tested-by: Hunk Lin <hulin@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

USB: gadget: f_mtp: allocate mtp buffers using dma

Allocate mtp_requests using dma

Bug 1158861

Change-Id: Ib12f7b9dc686e967f8d3e9603e4dc9ba7bcdf3f1
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/161615
(cherry picked from commit 5eca89ad1da23de729f5ae8a4077f6d5cb19db7d)
Reviewed-on: http://git-master/r/168692
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: t11x: Enable hazard detection timeout

bug 1159132

Change-Id: Ie7987f590926a9c246e8b3312020af406d1ac7ef
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/168101
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arm: tegra: enable deferred cache maintenance

Enable deferred cache maintenance optimization.

bug 983964
bug 994226

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I4f7128392e2c790386b52790fa8fc88bda93910e
Reviewed-on: http://git-master/r/165464
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arm: tegra: config: Enable bq2419x charger driver

Enable bq2419x battery charger driver

Bug 1179923

Change-Id: Ie7453b7f13167733fa924c810377cee3f68d149b
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/170516
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra11: dvfs: Update CPU dvfs tables and bins

Based on characterization results:
- Integrated new cvb dvfs coefficients
- Expanded DFLL operating voltage range to 0.9V ... 1.35V with
  1.0V as dynamic tuning threshold
- Added speedo_id 2 to differentiate fast parts
- Duplicated CPU EDP table for new speedo_id

Bug 1170986
Bug 1178825
Bug 1161126

Change-Id: I49ccdb7c3d734dcdd3bb9f2542683d418d21ab5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170368
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra11: clock: Restore SCLK and HCLK rate limits

Set back minimum 12 MHz rate for system and AHB clocks (SCLK and
HCLK) - partial revert of cf02b47b2dfdbe1e19a40df6bd28620a0c422ce9
Bug 1057646 requires HCLK:PCLK 2:1 ratio only starting from 60MHz.

Change-Id: Ic82cac35b9861dccbc66b29c9d507c1100c73d7c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169967
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arm: tegra: isomgr: add null implementaion for isomgr api

this is to handle isomgr config option disable case.

Change-Id: I37ad6e60005a631aeb1295bf6282a9a3aadb78e1
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/169777
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

bluesleep: it should depend on Tegra HSUART

blueseep has code dependency on Tegra HSUART.
KConfig should reflect that dependency.

Bug 1193147

Change-Id: I66fe597f9554138c5387b2e070238cdf81b5cf32
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/169514
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>

tty: serial: tegra: Export symbols for bluesleep

The bluesleep modules uses couple of symbols
which are not exported. As a result, bluesleep
cannot be built as module.

Bug 1193147

Change-Id: I47bc31cb6ff525e346df29264698031fd94032c7
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/169513
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>

ARM: config: tegra11: enable PWM_FAN config

bug 1179033

Change-Id: Ib3ec36bca0ceec6d260c3d5e093b5dda7c2f42b6
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/169234
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: config: tegra11: enable FAN_THERM_EST config

Bug 1159205

Change-Id: Ic17a7344387ac3eaa507ac5d144fde8a750d28df
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/169223
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra11: dvfs: Add CPU rail DFLL mode trip-point

Added CPU rail DFLL mode trip-point necessary to limit minimum CPU
voltage at cold temperature. The respective cooling device is not
implemented, yet.

Bug 1177204

Change-Id: I6abe1bc3ace81935c25968385af1998052455da0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/168999
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

gpio: tegra: add tegra_is_gpio

Added tegra_is_gpio function to
return true if pin is configured as gpio

Bug 1172972

Change-Id: Ieac0af9a6ee000cbeb73e714395169799ae18e3b
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/168285
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

arm: tegra: Dalmore: Shutdown SMPS

Shutdown SMPS8 in LP0

Bug 1176125

Change-Id: I78a67a74da12d3bb7e9ab375652e84f1a65491a3
Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com>
Reviewed-on: http://git-master/r/166694
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: Initial runtime pre-silicon support

* Add runtime calls to determine pre-silicon config
* Determine mode from minor revision in tegra id
* Export mode through fuse sysfs for user mode tests/code

Change-Id: I500d4ae14b70322f558ab48634fb758d3014bca2
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161324
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: Add PRE_SILICON_SUPPORT option

New option for enabling pre-silicon quirks and
differentiating between the various supported
platforms at run time instead of compile time.

After all features are ported from the PLATFORM
config, that option will be removed.

Change-Id: I0b1fcd1425a95bfb48ac4f64e306b4503955ac4f
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161287
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

media: video: tegra: nvavp: Fix nvmap handle issue

In open call we were assigning the driver's nvmap handle to
the nvavp's client context which would get released in release
call to driver. This will cause driver's nvmap handle to be
invalid if a parallel client context is running and driver does
any nvmap operation.

Bug 1013063
Bug 1192772

Change-Id: Id02520ae8ec511bb8c50bc4d3908ea3e75e1ea6b
Signed-off-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-on: http://git-master/r/170585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

drivers: tegra: imx091/max77665: fix edp issue

Fix the potential NULL pointer usage in the case there is no edp client
allocated.

bug 1193275

Reviewed on: http://git-master/r/#change,170249

Change-Id: I8cf6670edfd8ddd8f60a5200efe80a49767296bf
(cherry picked from commit 4be68a5750f55ea9b8e1062d6d2b6789891ee371)

Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Change-Id: Iabb40765c7f5b935bb5938c24397fda54581638f
Reviewed-on: http://git-master/r/170560
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: Tegra: Print raw MC error code

Print raw error code too for better diagnostic.

Change-Id: Iaf1268eeff3ad1077a6035755302fde1c650e76e
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/170558
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

media: video: tegra: imx091: Fix pll_mult value

The pll_mult value for imx091 new mode [524x390]
is incorrectly set. Which is being used to derive
VtPixelClk and later this clock is used to calculate
coarse-time, frame-length and frame-rate, hence all
are being calculated to wrong values.
Slow-mo faces the incorrect fps issue when same mode
needs to be programmed with different fps.

Bug 1180474

Change-Id: I673f6ad77fbb52225c0b427f5c78bd53bc473bea
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/170414
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Purwar <apurwar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

ARM: Tegra: Fix MC error reporting

Check that array indexing is within bounds.

Change-Id: I36f4edf1567eec395a16c46711b3b25ead88cf98
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/170384
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

ARM: tegra: Skip unnecessary L1 flush for all tegra chips

Change-Id: I52b7ae07c42f0f76b5e1e6d8564c9cb518c359a6
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/169768
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

arm: tegra: usb_phy: Fix race condition in resume

Resume could fail if remote wake is detected
by  PMC after controller has been put in suspend
during resume code. Restart bringing up host
controller as in case of remote wake if this hapens.

Bug 1179329

Change-Id: I7df4fcb73c565aedc4b22ff9cf229d3b50b99d15
Signed-off-by: Abhishek Shukla <abhisheks@nvidia.com>
Reviewed-on: http://git-master/r/169602
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ALSA: hda: powergate HDA when clock gating

Use powergating APIs to ensure that HDA and display play nice.
Export powergate APIs so snd-intel-hda can be built as a module.

Bug 1178366

Change-Id: I30559b9288fcbd86615a674756e70f04c9fb5d83
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/169245
Reviewed-by: Automatic_Commit_Validation_User

arm: tegra: dalmore: Runtime panel detection

Bug 1182416

Change-Id: I362f892c32e0f3e8e32e136b3595c71b696b2bae
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/169066
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra11: clock: Don't preset EMC VREF bits

Don't preset VREF bits in XM2DQSPADCTRL3 registers during EMC clock
change procedure.

Change-Id: I3abb6d07d93632b61363e2b0f7de37e1d7312af0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM: tegra11: clock: Use tabulated EMC clock register

Instead of constructing settings for EMC clock source/divider
register, use value specified in the EMC DFS table.

Bug 1188643

Change-Id: I4d28ed00c0b049d4ab5ad645cbf721ef6453be8b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169556
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM: tegra11: clock: Add latency entry to EMC DFS table

Bug 1189313

Change-Id: I4e39647c0c4702f05f03ecd00c82aa568f5fedf6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169138
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

fixup debug clock getting

Change-Id: Ieef5ca0d92ae9dce9b32713301c7451d861d5e7e
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

HACK Revert "regulator: core: Mark all DT based boards as having full constraints"

This reverts commit 86f5fcfc3e400b2ac1562cb0fd6aabc9f83ee3e2.

Change-Id: I2aae15af8f1a648d68e5a1e2a12fdf67208de5bf
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

HACK: disable our delay functions, causing hang

Change-Id: Ic3e2960d29d9ccc51d57fe23a2a0b309f665a12b
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup tegra11x_init_early

Change-Id: If124ad54e72cce9c4e241496e55ce014e5bef9e4
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup tegra11_clocks upstream uart changes

Change-Id: I5908329b69e681171bf91123611aa4b6369dc751
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup tegra11_clocks pwm driver name

Change-Id: I2a4c4cd7ea691033b9f2211c84511a8badaaea96
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup tegra11_clocks apbdma driver name

Change-Id: I53a61011c96b3f03d71451658cf37c194786459b
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup sound tegra30_i2s regmap changes

incomplete, but a start

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup tegra_rt5640 compile

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup hda_intel platform driver

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup hda_intel pci driver

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup hda_intel pci

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

usb: otg: tegra: Updates for 3.6

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup usb: host: tegra: update ehci to use common phy

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup usb: host: tegra: update ehci to use common phy

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

usb: gadget: tegra: Updates for 3.6

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup regulator: palma: Disable smps10 boost during suspend

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

ARM: config: tegra11_android: Run savedefconfig

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup: mfd: max77663: mfd_add_devices addition

See 0848c94fb4a5cc213a7fb0fb3a5721ad6e16f096

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup: mfd: max8831: mfd_add_devices addition

See 0848c94fb4a5cc213a7fb0fb3a5721ad6e16f096

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup: mfd: bq2419x: mfd_add_devices addition

See 0848c94fb4a5cc213a7fb0fb3a5721ad6e16f096

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup timer

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup timer arch_timer registration

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup: crypto: testmgr - Adding ofb(aes) and cmac(aes) tests

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

ARM: PCI: remove unused sys->hw

See upstream commit 8084de8ad53332ed6e0ffe5db85533b8150d7d6b

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup: tegra30_i2s compile fix

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup/HACK sound changes

* switch to regmap
* switch to runtimepm
* remove hand register cache (may need to move to regmap)
* rename txcif/rxcif
* disable i2s due to not being updated for DT, where upstream requires
   DT

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup hda_intel.c: compiler errors due to function split

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Revert "LOOK Partial Revert "ALSA: hda: Support disabling of clocks for Tegra""

This reverts commit a70fbb1efdf02c50699576f6e67c030dc2d5ceca.

fixup boot_hsic_class: Convert to dev_err

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

HACK? fix USB compile

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

regulator: Convert smb349 charger to use a struct to pass in regulator runtime config

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

regulator: Convert tps80031 charger to use a struct to pass in regulator runtime config

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Revert "gpio: tegra: implement gpio_request and gpio_free."

This reverts commit 6bdc80e5837a2ee188f020fd34f81a37fedc24b9.

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

fixup mach-tegra: arm: tegra: power: lp0 wake enable modified

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Revert "ARM: tegra: gpio: Add range check for gpio enable/disable"

This reverts commit 30ea3fa73c8b8fd65e504cf23169969b7032113f.

drivers: video: tegra: 3d scaling uses devfreq

This change separates 3d load estimation and adjustment (device
policy) from the governor that makes estimation for a proper
clock frequency.

This patch introduces a regression: Due to changes in the interface
EMC scaling cannot be disabled anymore.

Bug 965517

Change-Id: I1d42640f33054df4c659a4a20e3ab69e29392855
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/130581
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Rebase-Id: R132aff46dd256478a06f6824bf56ef59287fd629

arm: tegra: roth:Change tfa9887L i2c address as per A01 design.

Change-Id: Ib0ac39f263a3e3fbdeb4c6fbb08f1590b1a8643e
Signed-off-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>
Reviewed-on: http://git-master/r/169846
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra11x: Enable RAM repair per fuse setting

fuse bits spare_10 and spare_11 decide whether or not to do RAM repair

bug 1027322
bug 1056548

Change-Id: Id12f5fde052332759b03d191fbea99dc01aab894
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/169134
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

asoc:tegra: BT Call on Pluto

1. Use a DAM in BT Codec path
2. Add T114 specific code for DAM programming
   in call related functions
3. Add T114 specific code for I2S programming
   in call related functions
4. Update the machine drivers to call DAM functions
   only if DAM is used in the concerned path

Bug 1171615

Change-Id: I3ba9f088117045f2465ee0485d8f1afb0ac9ec59
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/168684
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Enable UHSIC bus keepers always

Currently bus keepers are enabled 1 clock later
after drivers are tristated. But to be on safer
side bus keepers are enabled always.

Bug 1032043

Change-Id: I5a696c5fba1dde161fc674d80e3b4b2e937348fd
Signed-off-by: srinivas thaduvai <sthaduvai@nvidia.com>
Reviewed-on: http://git-master/r/169332
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: usb: Fix phy_power_on condition

When the Phy is left powered on, in non LP0 event phy_resume
should not be programmed while after an LP0 event it should be
programmed.

Bug 1166740

Change-Id: I046c38bcf5589e270fdd99dcd99af057f9bfba1c
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/167715
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: usb: fix hsic resume sequence

2LS sequnence for HSIC resume is removed.

Bug 1164414

Change-Id: I31fed9cc0edcdf447543c54284742f7ce35cb44b
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/165893
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Atyam <vatyam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: dalmore: Mask SDR104,DDR50 for SDIO

Mask SDR104 and DDR50 UHS mode support for SDIO
devices as CRC errors are observed in these modes.

Bug 1181574

Change-Id: I93fb9fecc5eadcccc4c1c7180100d723719bc74b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/169397
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
GVS: Gerrit_Virtual_Submit

ARM: tegra: pcie: Support more than one pcie card

- Increase tegra3 prefetchable memory space
- Restore missing initialization of root_bus_nr in
  add port in boot path.

Bug 1037185

Reviewed-on: http://git-master/r/167086
(cherry picked from commit b69a73dcf31daa377fe64c3d89a6fe3abc9e87ba)

Change-Id: Idefc0c89b4836e7e812d56257b606110eb6364c4
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/169385
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

secureos: Remove useless smc for t114

This change removes obsolete smc which causes abort when resuming
in secure os build.
Same smc function called twice at boot time by function tegra_resume,
1st in virtual context, 2nd in physical, cache clean during exec of 2nd call.
In consequence, if remove this obsolete call, the abort issue is fixed.

Change-Id: Ia08360e56738b5b70420929acf8885c16c266646
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/169227
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra11: config: Enable INA3221 config

Bug 1160066

Change-Id: I80d6ea65c437b21dbb3e7459282876e09e80db78
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/169216
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: roth: power key connected to KBC-COL0 on A01 rev board

The Power key is connected to the KBC-COL0  from roth board
revision A01 onwards.

bug 1186701

Change-Id: I218fb10d0e89471f3d2e2db1b37bf15832bb1a03
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/169017
GVS: Gerrit_Virtual_Submit

audio: Add support for programming TFA9887.

Change-Id: I82b85cea36a5cb6160ded5b65766ae82b11118ea
Signed-off-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>
Reviewed-on: http://git-master/r/167977
Reviewed-by: Scott Peterson <speterson@nvidia.com>

ARM: tegra: roth: Add fan pwm device support

Following updates:
Makefile includes board-roth-fan
board-roth-fan initialized platform data for pwm fan driver
board-roth-pinmux change setting of PWM0
Change pll_p to 37Mhz

Bug 1179033

Change-Id: I36918256aed4e73c537cbfcbac57c3b011538d0a
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/167680
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

asoc:tegra: Support setting bit clock

Support for setting I2S bit clock from information
in the pdata structure.

Correctly supported DSPA and DSPB modes of I2S
during voice call.

Change-Id: I50e20ed66d2d0a01050d1d3902d179133f767f87
Signed-off-by: ScottPeterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/133669
Reviewed-on: http://git-master/r/146605
Reviewed-by: Automatic_Commit_Validation_User

audio: a2220: Fix the wrong GPIO for reset

gpio number for reset is not specified in platform data, in fact, its
value is 0 after kzalloc.  Requesting gpio for this number is bad
because the pin for GPIO 0 is used for other purposes. The original
hack is to use a magic number 118 for reset GPIO, this still needs to
be fixed. Meanwhile, to unblock the work which requires GPIO 0,
do not request GPIO 0 in this module.

Change-Id: Ibe1c38e948603fcd1d9de1164d5f69b0804757d2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/169562
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Tested-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User