5 years agoARM: tegra: clock: Update CPU cluster switch clock control
Alex Frid [Wed, 13 Feb 2013 23:55:56 +0000]
ARM: tegra: clock: Update CPU cluster switch clock control

Updated clock control when cluster round trip changes CPU clock
source from PLL to DFLL: G CPU (PLL) => LP CPU (PLL) => G CPU (DFLL).

- made sure that PLL used as G CPU clock source during the last
residency is enabled across LP-to-G switch
- made sure that initial G CPU voltage is preset before cluster
switch to maximum of voltage levels required for G CPU running on
last residency PLL and next residency DFLL
- changed G CPU rail control from s/w dvfs to h/w cl-dvfs after the
switch to G CPU is completed

Change-Id: I7720cda544ef16a4691534b52315e9128b2b27c3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201830
(cherry picked from commit fd9b858e4443860b3538f8e85eacdb24bf32c59b)
Reviewed-on: http://git-master/r/207894
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra: dvfs: Check I2C pending flag for CL-DVFS tuning
Alex Frid [Fri, 1 Mar 2013 04:13:35 +0000]
ARM: tegra: dvfs: Check I2C pending flag for CL-DVFS tuning

In CL-DVFS tuning timer callback ignored last I2C data, and re-start
timer, if I2C pending flag is set.

Change-Id: Ifb609ff66498f30e20f0d9a0a5a56901ed707808
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/205382
(cherry picked from commit e31e9249827b3ec34f48cec9e28c3103a399a430)
Reviewed-on: http://git-master/r/207893
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Calibrate DFLL minimum rate
Alex Frid [Sat, 16 Feb 2013 09:12:23 +0000]
ARM: tegra: dvfs: Calibrate DFLL minimum rate

Implemented calibration of DVCO minimum rate for DFLL operations
under CL-DVFS control. DVCO minimum rate setting is dynamically
adjusted based on CL-DVFS monitor frequency measurements so that
CL-DVFS is able to converge to minimum rate at minimum voltage.

Change-Id: Ibd2604d5eddc26391bd5c7569db8a05189536715
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/203586
(cherry picked from commit 0b9c2270a1b245f7802e2beadfadc4ddc0b2d93a)
Reviewed-on: http://git-master/r/207892
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14x: clocks: Increase isp max rate
Prashant Malani [Tue, 5 Mar 2013 21:49:51 +0000]
ARM: tegra14x: clocks: Increase isp max rate

Increase the isp clock max rate to accomodate
increased core dvfs frequency values.

Change-Id: I3324fcb0a552447240f4d2f19eed969c16b0835d
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/206464
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agomedia: tegra: max77387: fix coverity issue
Charlie Huang [Tue, 5 Mar 2013 21:42:01 +0000]
media: tegra: max77387: fix coverity issue

Change-Id: Iade44182415422572ab8f99938a334e69ba8e1a6
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/206411
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: gpio: correct touch gpio_reset in platform data
Hunk Lin [Tue, 26 Feb 2013 13:10:57 +0000]
ARM: tegra: gpio: correct touch gpio_reset in platform data

Touch's gpio_reset is used in some platforms. Change gpio_reset to right
value in platform data.

Bug 1242929

Change-Id: Ib806b6c8aabda4623e38c66f4f42d349777b089e
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/203300
(cherry picked from commit ff746e03305e87db108f28b9cba169c2dd86dfd4)
Reviewed-on: http://git-master/r/206224
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra11: pluto: Fix inconsistent return value for imx091
Frank Chen [Wed, 27 Feb 2013 18:39:36 +0000]
ARM: tegra11: pluto: Fix inconsistent return value for imx091

The power on function for imx091 returns different
values in Dalmore and Pluto board files. Both of them
should return 1 for success.

Bug 1188605

Change-Id: I4587040e0752aae6afa13af819461fcf03932686
Reviewed-on: http://git-master/r/204739
(cherry picked from commit 98212602c5a3bba911f92bfb711fc2af4f839261)
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/206010
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agomedia: video: tegra: Check sensor ID when power on.
Frank Chen [Thu, 14 Feb 2013 21:42:30 +0000]
media: video: tegra: Check sensor ID when power on.

Read the sensor ID after power on so we can return
failure as quick as possible if the sensor is not
present.

Bug 1188665

Change-Id: Ic4c21f38bd4895c15ec1891c26b265f02c587332
Reviewed-on: http://git-master/r/200890
(cherry picked from commit 583b5f4cb5abeddfacf028c30c81952f348e962f)
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/206009
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Lin <robertl@nvidia.com>
Reviewed-by: Michael Stewart <mstewart@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra11: pinmux: correct pinmux register resource
Jay Cheng [Tue, 5 Feb 2013 00:02:01 +0000]
ARM: tegra11: pinmux: correct pinmux register resource

the last mux register expand to 0x3408 offset

Change-Id: Idc82ea6513fbc5a555540a9e416b2042554853ce
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Reviewed-on: http://git-master/r/197199
(cherry picked from commit b700ab73e5b08bec98d902380259bfd8e8f30a0e)
Reviewed-on: http://git-master/r/205945
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: pluto: enable MAXFLASH
Charlie Huang [Tue, 26 Feb 2013 21:36:59 +0000]
ARM: tegra: pluto: enable MAXFLASH

Program MAXFLASH_TH: The voltage of VDD_SYS that will trigger a MAXFLASH
system lock up prevention control sequence. Set this to 3.4V, the most
conservative setting. This value may perhaps be lowered once the behavior
of the MAXFLASH system is characterized.

Program LB_TMR_F: This is a timer that will trigger a re-evaluation of the
MAX-FLASH conditions after the FLASH current has been reduced. Set this to
256usecs.
Program LB_TMR_R: This is a timer that will trigger a re-evaluation of the
MAX-FLASH conditions after the FLASH current has been reduced. Set this to
256usecs.

Program MAXFLASH_HYS: set this to 200mV

Program the MAXFLASH_EN: Enable the system once it is programmed correctly.

bug 1239750

Change-Id: I66223cbeeed392b3959b6936e83763182622e893
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/204274
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra11: clock: Don't report PLLC2/C3 lock timeout
Alex Frid [Tue, 5 Mar 2013 00:32:02 +0000]
ARM: tegra11: clock: Don't report PLLC2/C3 lock timeout

- Since PLLC2/C3 lock bits may fluctuate after pll is locked, don't
report timeout in this case.
- Expanded lock timeout message with the state of lock register

Bug 1057353
Bug 1213649
Bug 1232950

Change-Id: I33666bccba098733f29b01ffb3518e79603e3abf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/206173
(cherry picked from commit b88abe28f9d3f8aec4b3602d6f6100486866e078)
Reviewed-on: http://git-master/r/206133
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dsi: Fix h_blank too small warning
Animesh Kishore [Wed, 6 Mar 2013 09:42:13 +0000]
video: tegra: dsi: Fix h_blank too small warning

Add changes for video/command mode case and
continuous/tx_only clock mode case.

Bug 1239034

Change-Id: I8c6c4b55bf212debcd2d124035a17fa8cae5f668
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/206635
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Move duplicate clocks initialization
Alex Frid [Sun, 3 Mar 2013 05:47:30 +0000]
ARM: tegra11: clock: Move duplicate clocks initialization

Moved duplicate clocks initialization after specially handled clocks:
audio, external, and xusb clocks - so that these special clocks can
be duplicated if necessary.

Bug 1243423

Change-Id: Id57318837cdf3c12dfb1b7d671668b2368109ccf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/205786
(cherry picked from commit c933faa21c073f8a864f7153c6c25fbbfbb296dd)
Reviewed-on: http://git-master/r/207902
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Update GPU and media bus dvfs tables
Alex Frid [Sun, 3 Mar 2013 05:12:51 +0000]
ARM: tegra11: dvfs: Update GPU and media bus dvfs tables

Bug 116126

Change-Id: I0acc2520494ad753918412427696b68a71a548ae
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/205784
(cherry picked from commit fe0a2fee48629e8d6897cf24aaf7e20316443507)
Reviewed-on: http://git-master/r/207901
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: clock: Check if parent is allowed
Alex Frid [Wed, 27 Feb 2013 05:19:42 +0000]
ARM: tegra: clock: Check if parent is allowed

Checked if parent is allowed when listing possible parents in debugfs.

Change-Id: Ie7ea8e5c0eeb895526bacf96798f49a96f4a6b83
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/204416
(cherry picked from commit 0c4ac58e8ea4798a20be6ff806fad4766665d3bc)
Reviewed-on: http://git-master/r/207900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Don't allow PLLM/C as super clock source
Alex Frid [Wed, 27 Feb 2013 04:16:10 +0000]
ARM: tegra11: clock: Don't allow PLLM/C as super clock source

Updated parent selection policy to prevent PLLM and PLLC from being
selected as super clock sources (explicit check just to enforce policy
already in place).

Change-Id: If27c813b071081c93dd511b2bb3e54bc600819f4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/204414
(cherry picked from commit 9b6ef19228f7dc490f8c395d644c1a0c046a6359)
Reviewed-on: http://git-master/r/207899
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Rename CPU idle rate control APIs
Alex Frid [Fri, 22 Feb 2013 06:27:44 +0000]
ARM: tegra: power: Rename CPU idle rate control APIs

Change-Id: Id9bc9deabf8573a0743c5aafd1dc42f654b6f842
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/204413
Reviewed-on: http://git-master/r/207898
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: pinmux: correct safe function of spdif_out
Vishal Singh [Tue, 5 Mar 2013 10:08:19 +0000]
ARM: tegra: pinmux: correct safe function of spdif_out

Changing the "safe" function of spdif_out pin from RSVD to RSVD1,
because the safe function should to be one of the 4 SFIOs.
Otherwise we get this error, if the safe function is assigned to
the pin: "The pingroup SPDIF_OUT was configured to RSVD1 instead
of <UNKNOWN>".

Bug 982315.

Reviewed-on: http://git-master/r/198731
(cherry-picked from commit 8ebcfee11f0f22fbef4547c36fb590ec79c2af28)

Change-Id: Ie17af4d282214ae0e98ae0a7d9313c6bec197056
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/206271
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra14x: bb: set INT_BB2AP_INT0 as wake source
Vinayak Pane [Thu, 7 Mar 2013 00:19:37 +0000]
arm: tegra14x: bb: set INT_BB2AP_INT0 as wake source

BBC interrupt BB2AP_INT0 is set as wake source. This
IRQ is used for IPC. Also, make this interrupt level-high
triggered.

Bug 1236920

Change-Id: If0dc5c44ae79a9d7275b6e66ac0e3b3a34874d4e
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/206866
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoThermal: Add thermal events tracing (ftrace)
Timo Alho [Wed, 6 Mar 2013 17:37:25 +0000]
Thermal: Add thermal events tracing (ftrace)

Following two events in thermal framework are traced:
 - Call to handle_thermal_trip (thermal_zone_device name and temperature
   will be printed)
 - Call to thermal_cdev_update (thermal_cooling_device name and updated
   cooling state value will be printed)

Bug 1050412

Change-Id: If7e685ce26455820408d694fa720105ecae15469
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/207010
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>

5 years agoregulator: palmas: Clear VREF0P425 bit of LDO_CTRL
Sumit Sharma [Thu, 7 Mar 2013 13:06:28 +0000]
regulator: palmas: Clear VREF0P425 bit of LDO_CTRL

Clear VREF0P425 bit of LDO_CTRL for TPS80036 to avoid
voltage division by 2 for LDO4, LDO5 & LDO9

Change-Id: I2f8b49d25729c3d50fadf6a6700568dd3109d763
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/207113
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agocrypto: tegra-se: Don't enable ROs in SE resume
Shravani Dingari [Fri, 8 Mar 2013 11:46:57 +0000]
crypto: tegra-se: Don't enable ROs in SE resume

Enabling ROs is taking time and during this time if entropy is
used, S.E hangs. Hence disabling ROs in resume.

Bug 1249497

Change-Id: I961b3e317490658142b19fc2af3177f80edcf6ec
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/207557
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoconfig: tegra11: bluetooth support on dalmore
Mursalin Akon [Thu, 7 Feb 2013 20:01:45 +0000]
config: tegra11: bluetooth support on dalmore

This CL includes changes to
- move from built-in to module for all of the
bluetooth kernel components
- add support for couple of bluetooth HID devices

Bug 1223876

Change-Id: Ida7c899a5bea9702564e1e2ba6fd170d5b2ae9b0
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/198473
(cherry picked from commit c7add4c3f78aa0d3b220e6ad8f9566f4496f75a7)
Reviewed-on: http://git-master/r/201198
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: baseband: add shutdown for safe down.
Shawn Joo [Wed, 2 Jan 2013 05:52:00 +0000]
arm: tegra: baseband: add shutdown for safe down.

when reboot or power off, baseband should be off safely by calling right shutdown process.
add shutdown callback.

Bug 1210566

Change-Id: I26cf97e73f5234df875407aeb8db8c67b317d778
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/190280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: Add cl_dvfs clock requirement for PWR_I2C
Chaitanya Bandi [Mon, 18 Feb 2013 09:20:39 +0000]
ARM: tegra: Add cl_dvfs clock requirement for PWR_I2C

Added cl_dvfs clock requirement for PWR_I2C through
platform data.

Bug 1234556

Change-Id: I59bf9fcf5364b44050df610c12e6aef519b25047
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/201709
(cherry picked from commit f78ad10003cbea807b354393f5523c738253ecbc)
Reviewed-on: http://git-master/r/206943
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoi2c: tegra: Add cl_dvfs clock enabling for PWR_I2C
Chaitanya Bandi [Mon, 18 Feb 2013 09:06:55 +0000]
i2c: tegra: Add cl_dvfs clock enabling for PWR_I2C

Added cl_dvfs clocks enabling for PWR_I2C in i2c
driver.

Bug 1234556

Change-Id: Ied62a1cfc3d8c296e9aa46f08c7f34d0ab9766e1
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/201584
(cherry picked from commit 5ee5ac1624de959b8293242def231276c1d5d823)
Reviewed-on: http://git-master/r/206942
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: Add duplicate cl_dvfs clocks for PWR_I2C
Chaitanya Bandi [Mon, 18 Feb 2013 08:47:48 +0000]
ARM: tegra: Add duplicate cl_dvfs clocks for PWR_I2C

Added clocks cl_dvfs_soc and cl_dvfs_ref associated
with PWR_I2C as duplicates

Bug 1234556

Change-Id: I28c25e5a7db845677bd86babb3e217b4cf64259a
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/201703
(cherry picked from commit eedce388240139deabf0c5fb2bf5f2327d2c581d)
Reviewed-on: http://git-master/r/206941
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agosched: reinitialize rq->next_balance when a CPU is hot-added
Paul Walmsley [Thu, 7 Mar 2013 03:02:56 +0000]
sched: reinitialize rq->next_balance when a CPU is hot-added

Reinitialize rq->next_balance when a CPU is hot-added.  Otherwise,
scheduler domain rebalancing may be skipped if rq->next_balance was
set to a future time when the CPU was last active, and the
newly-re-added CPU is in idle_balance().  As a result, the
newly-re-added CPU will remain idle with no tasks scheduled until the
softlockup watchdog runs - potentially 4 seconds later.  This can
waste energy and reduce performance.

This behavior can be observed in some SoC kernels, which use CPU
hotplug to dynamically remove and add CPUs in response to load.  In
one case that triggered this behavior,

0. the system started with all cores enabled, running multi-threaded
   CPU-bound code;

1. the system entered some single-threaded code;

2. a CPU went idle and was hot-removed;

3. the system started executing a multi-threaded CPU-bound task;

4. the CPU from event 2 was re-added, to respond to the load.

The time interval between events 2 and 4 was approximately 300
milliseconds.

Of course, ideally CPU hotplug would not be used in this manner,
but this patch does appear to fix a real bug.

Nvidia folks: this patch is submitted as at least a partial fix for
bug 1243368 ("[sched] Load-balancing not happening correctly after
cores brought online")

Change-Id: Iabac21e110402bb581b7db40c42babc951d378d0
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/206918
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Kamath <akamath@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoThermal: pid_thermal_gov: Fix wrong comparison when temp is negative
Jinyoung Park [Wed, 27 Feb 2013 06:05:03 +0000]
Thermal: pid_thermal_gov: Fix wrong comparison when temp is negative

Corrected variable type of trip_temp from unsigned long to signed long,
to prevent a wrong comparison issue when the temperature is below zero.
And changed order of temp and trip_temp comparison to reduce unnecessary
target calculation.

Bug 1233407

Change-Id: I95cdd67c08239c45115c66d9cfc93c68b59fd529
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/204935
(cherry picked from commit 8e1d798187c653c0802e9462fc3ed8d6d59b4c77)
Reviewed-on: http://git-master/r/206847
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: pluto: Fix panic when using RMC modem
Raj Jayaraman [Thu, 28 Feb 2013 22:25:02 +0000]
arm: tegra: pluto: Fix panic when using RMC modem

Bug 1243687

Change-Id: I619d7fb42fbb43bbee9ed59f55779b1df0a18624
Signed-off-by: Raj Jayaraman <rjayaraman@nvidia.com>
Reviewed-on: http://git-master/r/205276
(cherry picked from commit ef670c479860131e72da2b1656d47e45daff74b4)
Reviewed-on: http://git-master/r/206821
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agovideo: tegra: camera: enable sclk in camera
Jihoon Bang [Fri, 1 Mar 2013 17:53:54 +0000]
video: tegra: camera: enable sclk in camera

Enable sclk in camera and set 80MHz when
camera is opened. It helps boost KPI.

Bug 1234580

Change-Id: Id4bcddb31bcbad68f9bd8956124cfd4325b6cfc1
Reviewed-on: http://git-master/r/205603
(cherry picked from commit 8ed151f5699cae414b8ce9236770a55d8922e1eb)

Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Change-Id: Ieca8b86801481b88c6b4cc4717d806b852890d9a
Reviewed-on: http://git-master/r/206785
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agomisc: nct1008: modify shutdown functionality
Gaurav Batra [Tue, 26 Feb 2013 21:59:10 +0000]
misc: nct1008: modify shutdown functionality

Bug 1234272

The shutdown function acquires the lock and waits on
the worker function to finish which itself needs the lock.
This results in the deadlock. Moved the lock call after
the wait on workers to finish.

Change-Id: I894d6b7342f9d42d86946d592ce912ddb0e476d9
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
(cherry picked from commit dc1696d261650b3b3e47f305b16c0405a89f3743)
Reviewed-on: http://git-master/r/206766
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra11: clock: add camera to sclk
Jihoon Bang [Fri, 1 Mar 2013 17:49:53 +0000]
ARM: tegra11: clock: add camera to sclk

Add camera to sclk as a client.
Increasing sclk freq helps camera KPI.

Bug 1234580

Change-Id: Ia7e5f2572de18a197c7e614882fd2d8fcdd975c1
Reviewed-on: http://git-master/r/205602
(cherry picked from commit e65dba352a4f286f941e6e91906388f2fd14b90d)

Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Change-Id: I7a994fd1b44cf71dfd38584c3443f7de08b8d80f
Reviewed-on: http://git-master/r/206765
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra114: config: Remove PCIE support
Bo Yan [Wed, 27 Feb 2013 02:18:12 +0000]
ARM: tegra114: config: Remove PCIE support

T114 does not support PCIE.

Change-Id: Ibccc932630dd5480d296f49b46407a999d9dd195
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/204375
(cherry picked from commit 84e19753d9338c6af676e8b416dfb7f4847bfbe9)
Reviewed-on: http://git-master/r/206722
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14x: dvfs: Update core dvfs tables
Prashant Malani [Wed, 6 Mar 2013 00:18:29 +0000]
ARM: tegra14x: dvfs: Update core dvfs tables

Add new voltage levels for core dvfs table.
Also update big block entries with bin 0
values.

Bug 1246952

Change-Id: Icf0a1d9d926f92c332ffea5b97fbfdf109d23896
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/206466
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra14x: clocks: Raise c2bus clks max rate
Prashant Malani [Tue, 5 Mar 2013 21:53:33 +0000]
ARM: tegra14x: clocks: Raise c2bus clks max rate

Increase the rate of c2bus and related clocks,
i.e, 2d, 3d and epp, to accomodate higher values
in core dvfs table.

Change-Id: I4084952354a8cfdb0d90d9dd0d803ad8c255e080
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/206465
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra: roth: add missing pwrdet regulator entries
Bitan Biswas [Mon, 11 Feb 2013 14:43:10 +0000]
ARM: tegra: roth: add missing pwrdet regulator entries

bug 1233759

Change-Id: I2b6c191649210d6d58e37e3eb5da3b330b28b7f1
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/199454
(cherry picked from commit d918bdb2eccd22d03d660c24a1c0cd7c53544159)
Reviewed-on: http://git-master/r/204507
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoarm: tegra: usb_phy: add delay on wait loop of ack
Shawn Joo [Thu, 27 Dec 2012 11:09:03 +0000]
arm: tegra: usb_phy: add delay on wait loop of ack

There is no delay while reading gpio of modem ack.
it will be a bad influence on system.
put 1ms delay on the loop.

Bug 1191026

Change-Id: I1b3fa50cabbe002cd6a0ec4c66099dc694a5a6e5
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/190281
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agovideo: tegra: host: Send load value to EDP
Terje Bergstrom [Tue, 15 Jan 2013 08:17:07 +0000]
video: tegra: host: Send load value to EDP

Bug 1159974

Change-Id: I72a6d6de4d2f5fd3d686aa8c8e64d71a24e96323
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/198393
(cherry picked from commit 236a9f6b3e38284cc3e0013604a8b4079d3b43d5)
Reviewed-on: http://git-master/r/191164
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Tested-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agopower: max17042: trace battery status
Sivaram Nair [Tue, 26 Feb 2013 08:54:33 +0000]
power: max17042: trace battery status

We need visibility into the main battery status variables for EDP tuning
purposes. Added a debug print for this purpose.

Bug 1234447

Change-Id: I420307cb2df2b8d61b5314609c58e7a5c0a64595
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit f6a011f8e7dcbde4dcaabf42aa7b23f8eb1859a4)
Reviewed-on: http://git-master/r/204587
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoEDP: allow reducing manager cap on the fly
Sivaram Nair [Thu, 21 Feb 2013 16:54:22 +0000]
EDP: allow reducing manager cap on the fly

Current mechanism for reducing the maximum capacity of an EDP manager is
little cumbersome and requires multiple steps. This patch implements it
in a better way and allows the developer to achieve the effect in a
single debugfs modification.

Change-Id: I842105ae4bfe47d9856e477033b8543ee1664e2e
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit 2bc89cc8bcc2a60e53ddc34362a7ab31a27d7f15)
Reviewed-on: http://git-master/r/204586
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: modem_boot - add new E-state
Sivaram Nair [Thu, 21 Feb 2013 16:52:15 +0000]
ARM: tegra: modem_boot - add new E-state

A new E-state (E1) is added with 0mW for modem boot client. This makes
it easy to tune the overall budget (by moving modem_boot to E1 if
needed).

Change-Id: I229c4c8fe38efb3ebff42e0f42ce731ee1cac96a
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit f7735fb4c7431a94296a827b1ce9f967a72ab413)
Reviewed-on: http://git-master/r/204585
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: add pluto core system EDP device
Sivaram Nair [Wed, 20 Feb 2013 10:54:00 +0000]
ARM: tegra: add pluto core system EDP device

This patch adds and registers core system EDP device for pluto

Change-Id: I3a98216e11661cab9dddc35dcf935bab1d23cd22
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit 5af2818f815876ad77570bdb919b07534d2196ec)
Reviewed-on: http://git-master/r/204584
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoregulator: max77660: move register definitions to header
Pradeep Goudagunta [Wed, 27 Feb 2013 08:44:42 +0000]
regulator: max77660: move register definitions to header

Keeping all register definitions at one place, in core header.

Reviewed-on: http://git-master/r/204500
(cherry picked from commit f5a7d055a32ae1aedfec42fabae097a892dad9c8)
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Change-Id: Ice355168c3add1a60a6c102a9c8a823cf7e9d219
Reviewed-on: http://git-master/r/206952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agonvhost: tsec: make sure kfuse is pointed to hdmi.
Marvin Zhang [Thu, 14 Feb 2013 02:57:12 +0000]
nvhost: tsec: make sure kfuse is pointed to hdmi.

tsec needs to get pkey from kfuse by changing kfuse mux to tsec,
after tsec is done, it restores mux back to hdmi so that latter
can use it to load hdcp keys.

Bug 1235326

Change-Id: I52459a67159583f3f120fe8a8cbc1ea1ec4b13c7
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
(cherry picked from commit c965f3ccef4c41634d36250a5e3851a7794f4ab9)
Reviewed-on: http://git-master/r/200654
Reviewed-on: http://git-master/r/205708
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoextcon: palma: add vbus detection through extcon notification
Laxman Dewangan [Sun, 24 Feb 2013 15:32:38 +0000]
extcon: palma: add vbus detection through extcon notification

Add VBUS detection on palmas and notify the state through extcon
framework.

Bug 1238096

Change-Id: Ic5bb577aa66330e93b909df7dfc297aaf55fa0e6
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/203655
(cherry picked from commit b5e45af19fd91e8c54c17c1f21deee0afb8d6fd4)
Reviewed-on: http://git-master/r/204692
(cherry picked from commit 222d6e830ab6bb3253d18066ba5dc6f820d7a040)
Reviewed-on: http://git-master/r/206549
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomfd: palmas: add palmas-extcon as mfd sub driver.
Laxman Dewangan [Sun, 24 Feb 2013 15:34:03 +0000]
mfd: palmas: add palmas-extcon as mfd sub driver.

palma-extcon is sub palma driver used for detection of VBUS and ID
pin state. Add this driver as sub mfd device.

bug 1238096

Change-Id: I4f789d6d2193620f08f9e36576512aa6f3d9dc38
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/203656
(cherry picked from commit 61f3e5e8b699c8bdbe0962504d7d71963f682815)
Reviewed-on: http://git-master/r/204691
(cherry picked from commit 34e3ec60be0d416c16ffce68b106b29a8d90e305)
Reviewed-on: http://git-master/r/206548
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoiommu/tegra: smmu: Add support 4MB SMMU page
Hiroshi Doyu [Wed, 27 Feb 2013 17:47:14 +0000]
iommu/tegra: smmu: Add support 4MB SMMU page

Add support 4MB SMMU page

bug 1226176

Change-Id: If3959f7607746c8b5413dd548123fc0bbc1586d5
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/204754
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: panel: Add LM3528 registration for Atlantis
Chaitanya Bandi [Fri, 15 Feb 2013 10:54:30 +0000]
ARM: tegra: panel: Add LM3528 registration for Atlantis

Bug 1216857

Change-Id: I705b740ac1aa4b15a30bd6d993bbafb2ab4279a6
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/201123
(cherry picked from commit 1b8c56ae33dce65acde70a6f3ad51d362af6b246)
Reviewed-on: http://git-master/r/204956
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>

5 years agobacklight: lm3528: Add backlight driver for LM3528
Chaitanya Bandi [Tue, 12 Feb 2013 08:59:29 +0000]
backlight: lm3528: Add backlight driver for LM3528

Bug 1216857

Change-Id: I2ec1a393769804d73191d690d8340c30885e16ae
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/199925
(cherry picked from commit 82de53cdad7de223cfefc9b5e33b370bd5c18957)
Reviewed-on: http://git-master/r/204954
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agocrypto: tegra-se: Enable RO entropy source for DRBG
Shravani Dingari [Wed, 27 Feb 2013 05:25:34 +0000]
crypto: tegra-se: Enable RO entropy source for DRBG

Bug 1194672 , Bug 1213276

Change-Id: I2a1d033b5da8782b802f9dbac0461a596942b968
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/204402
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: dvfs: Update CPU DVFS tables
Seshendra Gadagottu [Mon, 4 Mar 2013 23:07:10 +0000]
ARM: tegra: dvfs: Update CPU DVFS tables

Updated DFLL/PLL CPU DVFS tables from latest
SV data. Updated following information:

- Updated tune0/tune1 values
- Different tune0 for high voltages
- Updated DFLL/PLL CVB data
- Updated min/max cpu voltages

Change-Id: I79f2105d4b2a5f0d4afd35d880fdb193125711e3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/206085
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: fuse: Read cpu speedo values from fuses
Seshendra Gadagottu [Mon, 4 Mar 2013 22:53:34 +0000]
ARM: tegra14: fuse: Read cpu speedo values from fuses

Change-Id: I4f6570f7ddabb119b25f09b286618d9657be5d22
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/206083
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agovideo: tegra: hdmi: reduce hdmi rate for lower dvfs.
Kevin Huang [Wed, 6 Mar 2013 19:32:20 +0000]
video: tegra: hdmi: reduce hdmi rate for lower dvfs.

Reduce the hdmi rate before we switch to the target rate.

Bug 1237346

Change-Id: I3407f45b0bb2b0eff76b033cfa0f1472f9dd0563
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/206763
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomedia: tegra: avp: Remove old AVP driver
Kaz Fukuoka [Wed, 20 Feb 2013 02:09:38 +0000]
media: tegra: avp: Remove old AVP driver

Change-Id: I6c33c41952b700e6c12e8f2d9d4f53aef302add3
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/202284
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: mipi-cal aperture
Charlie Huang [Sat, 2 Mar 2013 03:20:09 +0000]
ARM: tegra: mipi-cal aperture

add mipi-cal register mapping feature, so user space can access.

bug 1168468

Change-Id: I71faf09e7b41be4e6eb5a25c2e2d17e24545d719
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/205741
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: board id update
Bitan Biswas [Wed, 6 Mar 2013 06:55:03 +0000]
ARM: tegra: board id update

Ceres and Atlantis board-ids added

Change-Id: I017825cf7ade77d2ad79862ba4f9ee9423da60b6
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/206569
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoASoC: Tegra: Code cleanup
Ravindra Lokhande [Wed, 6 Mar 2013 12:00:25 +0000]
ASoC: Tegra: Code cleanup

Removed unnecessary code

Change-Id: I1d99dc44eafcd26ec2aabc09dde347bf335fa7fb
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/206666
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoarm: tegra11_defconfig: Enable CMA
Hiroshi Doyu [Wed, 6 Mar 2013 06:48:26 +0000]
arm: tegra11_defconfig: Enable CMA

Enable CMA

bug 1215880

Change-Id: I62edaa273d3d3e08f1e849f87027dc14f2f49441
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/206568
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agotegra: asoc: e1853: Fix the device name for E1853
Nitin Pai [Thu, 30 Aug 2012 17:08:07 +0000]
tegra: asoc: e1853: Fix the device name for E1853

Fixed the driver name for the E1853 sound driver.

Bug 1040171

Change-Id: Ifa54bbe9577f189bab293adc6219c9ce003f8954
Signed-off-by: Nitin Pai <npai@nvidia.com>
Reviewed-on: http://git-master/r/128570
(cherry picked from commit 2d396b8462e80a23979715d0b286ccf6c7127faf)
Reviewed-on: http://git-master/r/206554
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoarm: tegra: e1853: fix sysclk for codec dai
Vijaya Bhaskar [Tue, 22 Jan 2013 07:52:02 +0000]
arm: tegra: e1853: fix sysclk for codec dai

Fix the sys clock settings for codec dai

Bug 1179657
Bug 1218875

Reviewed-on: http://git-master/r/192358
(cherry picked from commit 0ca99051a37dbfcc59a1f931f025d9108bbebab7)

Reviewed-on: http://git-master/r/199409
(cherry picked from commit c7fe9db79ac4bb88367fc2db993b1bf9796610bb)

Change-Id: I2a37fdfa0a3d58a2f7b3e896505b8868ee06c9c2
Signed-off-by: Nitin Nagaraja <nitinn@nvidia.com>
(cherry picked from commit 1a8f84e79a78eccea3dda6138aa3852fd4b0a9b8)
Reviewed-on: http://git-master/r/206528
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Pai <npai@nvidia.com>
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agovideo: tegra: camera: increase max iso BW
Jihoon Bang [Tue, 5 Mar 2013 19:43:06 +0000]
video: tegra: camera: increase max iso BW

Change max iso BW from 540MBps to calculated peak BW.
Peak BW is calculated using max VI clock and total
byte per pixel of VI output.

Bug 1245734

Change-Id: I40516c2416e504fd8b7098e2aae40326bac5b0a3
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/206391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Tested-by: Philip Breczinski <pbreczinski@nvidia.com>

5 years agovideo: tegra: host: Fix error paths in user hwctx
Terje Bergstrom [Mon, 4 Mar 2013 07:31:55 +0000]
video: tegra: host: Fix error paths in user hwctx

Plug the unhandled error paths in code that sets a new context save /
restore sequence.

Change-Id: I5fd70c3e337f72414c38302a70336356352d06da
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/205843
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoasoc: codecs: max97236: updated driver from maxim
Dara Ramesh [Fri, 1 Mar 2013 07:02:42 +0000]
asoc: codecs: max97236: updated driver from maxim

updated driver from maxim (version v0.00.0107)

bug 1235740

Change-Id: I675b5f56444e06f19149222c3a2fb9c9492600bd
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/205434
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra: pcie: synchronize all asynch function calls
Preetham Chandru R [Thu, 21 Feb 2013 11:22:52 +0000]
ARM: tegra: pcie: synchronize all asynch function calls

Wait until all asynchronous function calls have been done otherwise
we might get into a deadlock situation when a mass storage device is
connected to usb 3.0 port.

Bug 1162845

Change-Id: I0fa2a85188a1d388273b3ae752e5ce9cf4d5d23b
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/205001
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: Tegra: Add devices to MC clock domain
Prashant Gaikwad [Wed, 6 Mar 2013 06:25:58 +0000]
ARM: Tegra: Add devices to MC clock domain

Add devices to monitor for MC clock to the domain. MC clock
domain will be turned off when these devices are runtime suspended.

Bug 1010971

Change-Id: Ica4f9fbbd2cc8f52422a787b45cfae37bc60e130
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/204945
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra14x: bb: turn on bbc rails at reset
Vinayak Pane [Thu, 14 Feb 2013 05:29:44 +0000]
arm: tegra14x: bb: turn on bbc rails at reset

BBC power rails are turned on before it is released
from reset. By default it should not be turned on
in the probe function.

Changed the regulator names to make it more relevant
to bbc.

Change-Id: I7e7a5b6303b8840931e465ea1f630d7dccb83b80
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/206078
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-by: Neil Patel <neilp@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoASoC: Tegra: Fix I2S_SLOT_CTRL2 reg access
Sumit Bhattacharya [Wed, 20 Feb 2013 16:48:55 +0000]
ASoC: Tegra: Fix I2S_SLOT_CTRL2 reg access

When I2S_SLOT_CTRL2 register is modified for TX or RX port previous
value in the register for the other port need to be saved. This will
fix concurrent playback capture issues in BT SCO mode.

Bug 1233807

Change-Id: I618c0e929e0d2c6f16a327a1cc66c61a6d8f6fe6
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/202583
(cherry picked from commit 39c312fcf65a899a27ff1b2d863f3f903991618a)
Reviewed-on: http://git-master/r/205925
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agodrivers: make tegra-throughput driver always post fps
Simo Melenius [Tue, 19 Feb 2013 09:28:50 +0000]
drivers: make tegra-throughput driver always post fps

- number of active clients only controls delivering throughput hints
- unified scaling needs fps rate regardless

Bug 1161410
Bug 1171636

Change-Id: I63b4fc2e93eac00d2702f154f6b2d73b7941af86
Signed-off-by: Simo Melenius <smelenius@nvidia.com>
Reviewed-on: http://git-master/r/201996
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: dalmore: update emc table to latest
Ray Poudrier [Wed, 23 Jan 2013 20:09:16 +0000]
ARM: tegra: dalmore: update emc table to latest

Bug 1189313

Change-Id: Ib2502085e533f3f858a058a337ef2cf4a62391c0
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/193500
(cherry picked from commit 1a80f0dbe95c35ba6a9a5132675c64db557b26e3)
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/201664
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14x: Enable LP1BB->LP1 transition
Prashant Malani [Tue, 26 Feb 2013 00:43:43 +0000]
ARM: tegra14x: Enable LP1BB->LP1 transition

If an LP1BB wake was caused solely due to the
end of paging event (i.e mem_req->0), we should
transition to LP1 without waking to active.

Bug 1239689

Change-Id: Ib3f8c1a74386f87a4e7d5f10878ef919bb5be6e1
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/204901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14x: Support BB-aware LP1
Prashant Malani [Mon, 25 Feb 2013 21:11:44 +0000]
ARM: tegra14x: Support BB-aware LP1

This enables LP1 exit due to BB paging event.
In case we enter LP1, mem_req=1 is set as the
wake event.

This allows LP1BB to be entered even when a
legacy LP1 entry is triggered.

Bug 1239689

Change-Id: Ia9ae305eb1bf3923e261d4e5c67b2c4db7b6b07e
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/203969
(cherry picked from commit 52b5885d344d6d17067658c6fd382bbee73b54ca)
Reviewed-on: http://git-master/r/204900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: Remove EXTPERIPH1_RST
Kaz Fukuoka [Tue, 5 Mar 2013 00:43:04 +0000]
ARM: tegra14: Remove EXTPERIPH1_RST

- EXTPERIPH1_RST is removed on Tegra14.
- Even in older Tegra, EXTPERIPH1_RST was not controlling anything.

Change-Id: I6f16daed8b87e1f29972248553a4066edb1ecd2e
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/206102
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra14: clock: Fix PLLM post-divider
Alex Frid [Sat, 9 Feb 2013 06:39:54 +0000]
ARM: tegra14: clock: Fix PLLM post-divider

Change-Id: If626eb9a81ce16bf79ccf866ae48ce9a63e63ebf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/205714
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra148: Turn on config for ARM erratum 754322
Bo Yan [Tue, 5 Mar 2013 06:02:27 +0000]
ARM: tegra148: Turn on config for ARM erratum 754322

ARM erratum 754322 for Cortex-A9 is applicable to r4p1 as well.

Change-Id: I694336080a1e102bb01a4fc6dd24fee0073eeead
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/206199
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra: Remove redundant diag reg save & restore
Bo Yan [Tue, 5 Mar 2013 00:42:14 +0000]
ARM: tegra: Remove redundant diag reg save & restore

The diagnostic register is saved and restored in cpu_v7_do_suspend
and cpu_v7_do_resume already, there is no need to duplicate this in
platform code, moreover, the current implementation is incomplete
since it doesn't do it for CPU0 in case of cluster wide power down.

Change-Id: I33dc791b4cdd436186e521b6b222f954fd838e91
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/206103
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: Tegra: Pluto: Update emc dvfs table
Graziano Misuraca [Tue, 29 Jan 2013 22:00:31 +0000]
ARM: Tegra: Pluto: Update emc dvfs table

Update emc dvfs table for AP40 SKU for
792/624/408/312/204/102/68/40.8/20.4/12.75
MHz support.

Bug 1189313

Change-Id: Ie59f9672faed60f00991a2453f2484ae91d8b728
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/195235
(cherry picked from commit 21fbc2a7bfb3033006f31b83d7277096a6b082be)
Reviewed-on: http://git-master/r/205805
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra14: CPU0 power gating
Seshendra Gadagottu [Mon, 18 Feb 2013 21:17:30 +0000]
ARM: tegra14: CPU0 power gating

Allow CPU0 power gating when number of online CPUs
are more than one.

Change-Id: I533e0ed52bd834fa9a08080333ed9d5eb9520ea0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/201834
(cherry picked from commit c021a30c7cd263a5d21ecc7a274f86cc3076304a)
Reviewed-on: http://git-master/r/205235
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoarm: tegra: dalmore: Increase display wakeup time
Vineel Kumar Reddy Kovvuri [Thu, 28 Feb 2013 12:16:27 +0000]
arm: tegra: dalmore: Increase display wakeup time

Fixes the issue of display failing to wakeup from LP0

Change-Id: Ice35f1518877e6e3810e5d2fe824ce12abf78a5b
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/205110
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoEDP: update documentation
Sivaram Nair [Tue, 26 Feb 2013 12:12:05 +0000]
EDP: update documentation

Adding documentation about debugfs features and tegra specific
implementation.

Change-Id: I087391b522ee89cfe7a75ad44c4ea005c139c1b2
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit c6844e9af030d13b1a664c1d1a5f1b74c4659234)
Reviewed-on: http://git-master/r/204589
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: e1853: Add ad1937 driver for E1861
Nitin Nagaraja [Tue, 8 Jan 2013 06:03:31 +0000]
arm: tegra: e1853: Add ad1937 driver for E1861

AD1937 audio codec was being programmed in userspace on Jetson platform.
Now it is moved into kernel space using the existing the codec driver.

Bug 992424

Change-Id: I6088c606906759bc005489f80a566b1bba14e707
Signed-off-by: Nitin Nagaraja <nitinn@nvidia.com>
Reviewed-on: http://git-master/r/189434
(cherry picked from commit 3975a4446d933bb1ef902c7bb17b90db9263e020)
Reviewed-on: http://git-master/r/203249
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: Tegra: add new sysfs entries for tegra_bbc_proxy
Stephane Dion [Tue, 19 Feb 2013 09:33:48 +0000]
ARM: Tegra: add new sysfs entries for tegra_bbc_proxy

One entry to register the modem client
and one other to perform reserve and realize in a single sysfs write

bug 1205851

Change-Id: I340c7fe69037aef951f019ad86065eaa1381967b
Signed-off-by: Stephane Dion <sdion@nvidia.com>
Reviewed-on: http://git-master/r/202975
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: Board file changes for modified palmas driver
Sumit Sharma [Tue, 22 Jan 2013 08:17:40 +0000]
arm: tegra: Board file changes for modified palmas driver

Changes in board files to support modified palmas driver

Change-Id: Ie2434b7f28b7d4b3393ae035dd233897aac2df8e
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/199258
(cherry picked from commit 710a8caacf5773e1ddb395fbf6eae9f16a84f0d7)
Reviewed-on: http://git-master/r/192825
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: macallan: Change analog power for touch
Xiaohui Tao [Wed, 27 Feb 2013 19:24:41 +0000]
ARM: tegra: macallan: Change analog power for touch

Rayidum needs power supply for their analog power to be at least
3v. Change the supply from 2.9v to 3.1v.

Bug 1241244

Change-Id: Ief2f0e8412da4c608d0c18950ac5ea3830880a4f
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/204756
(cherry picked from commit 75485c37afc1245216a5d3fa4973c29e886c68a3)
Reviewed-on: http://git-master/r/205969
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agohwmon: ina230: check conversion ready bit
Deepak Nibade [Wed, 6 Feb 2013 16:12:51 +0000]
hwmon: ina230: check conversion ready bit

check conversion ready bit before reading
current/power registers and wait till it is set

Bug 1228591

Change-Id: I2d1278a1d36f3d591106a005d5875307d6e7de19
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/198002
(cherry picked from commit 3653e6c81ff7ce6ec398a1c01f4a4782775d3e8d)
Reviewed-on: http://git-master/r/205850
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: pluto: modify power rail data for reworked boards
Deepak Nibade [Wed, 20 Feb 2013 10:47:05 +0000]
ARM: tegra: pluto: modify power rail data for reworked boards

- values of resistors are different on boards which are reworked
for power measurement
- modify rail data to reflect this change
- make use of power_config to detect whether board is power
reworked or not

Bug 1228591

Change-Id: I4d8326dd3503ef7967f59fb2f74af5f5ece5e5d9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/202514
(cherry picked from commit 2a7ac5271501ba0ebb9c4be49742a0c10a398fb7)
Reviewed-on: http://git-master/r/205849
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: clock: Mark CEILING users in the clock tree
Alex Frid [Thu, 28 Feb 2013 06:46:02 +0000]
ARM: tegra: clock: Mark CEILING users in the clock tree

Marked cap shared users with "^" sign in the clock tree.

Change-Id: Ia85d15cd616fb17db22c366e1ca096a842c1be9f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/204988
(cherry picked from commit 9ed8c8ba27578513e092f0db0a7782d750ce0399)
Reviewed-on: http://git-master/r/205795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Rename CL-DVFS minimum rate field
Alex Frid [Sun, 24 Feb 2013 06:17:29 +0000]
ARM: tegra: dvfs: Rename CL-DVFS minimum rate field

Renamed CL-DVFS minimum rate field: from dfll_rate_min to dvco_rate_min
to clearly differentiate minimum rate DVCO inside DFLL can run at under
CL-DVFS control, and DFLL clock rate, that can be scaled down from DVCO
rate by the DFLL clock skipper.

Change-Id: I21e52050ca48b3cc31d54a40488ccfb75953b999
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/203635
(cherry picked from commit 6a80de6a7392b8b921f38de265817b508c5cada3)
Reviewed-on: http://git-master/r/205794
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agonet: wireless: bcm4335: power off card when not in use
Om Prakash Singh [Thu, 14 Feb 2013 04:24:52 +0000]
net: wireless: bcm4335: power off card when not in use

Power off the card when wifi is off and power up only when wifi
is turned on

Bug 1011349

Change-Id: I018c3757280c81c9077dd07949422bf572fc3a0d
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: http://git-master/r/200684
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra11: power: Update CPU EDP limits
Alex Frid [Sat, 23 Feb 2013 04:08:05 +0000]
ARM: tegra11: power: Update CPU EDP limits

Bug 1161126

Change-Id: Ic480197f8f57650085385135db5186ac738ec994
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/203563
(cherry picked from commit 59c46e56aa782ee814f93e5927f54fe828bcff70)
Reviewed-on: http://git-master/r/205793
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Tune CL-DVFS target module trimmers
Alex Frid [Wed, 23 Jan 2013 04:34:11 +0000]
ARM: tegra11: dvfs: Tune CL-DVFS target module trimmers

Added mechanism to tune CL-DVFS target module trimmers (along with
CL-DVFS settings) when low/high voltage range boundary is crossed.
Updated CPU clock trimmers on Tegra11 per characterization results.

Bug 1223242

Change-Id: If44a19bd8406e7c109b59b0c9e01182adcd591cb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/193286
(cherry picked from commit 388dd4977d0680bfa0e4d06cf4c14fbbeded6f7a)
Reviewed-on: http://git-master/r/205790
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Re-arrange CL-DVFS pm callbacks
Alex Frid [Wed, 20 Feb 2013 02:41:16 +0000]
ARM: tegra11: dvfs: Re-arrange CL-DVFS pm callbacks

Moved CL-DVFS closed loop suspend/resume operations from CL-DVFS
device power management callbacks to platform syscore callbacks.
This is done to avoid I2C bus contention between CL-DVFS exit from
closed loop and drivers s/w access to power I2C during suspend and
shutdown entry. Possible remedy for such contention - abort suspend,
and restore CL-DVFS closed loop - would adversely affect suspend
residency time. On the other hand during syscore operations CL-DVFS
h/w is the only one using power I2C bus.

CL-DVFS device suspend callback is still used to force cold zone
voltage limit, regardless of entry temperature to be safe when SoC
is resumed at cold.

This partially reverts commit 37d1df541838c65677d0ae4eb529de9160336a7f,
and commit 965dbfab96b842f50574c8ec092207b465ca0401

Bug 1237641

Change-Id: I4424babe16776fa410a0b0f54f4b7e605a1e25c4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/202644
(cherry picked from commit 4a49cb2ce0f20f9e63a8aa11e502c753d8873584)
Reviewed-on: http://git-master/r/205789
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agousb: xhci: tegra: disable regulators in lp0 path
Ajay Gupta [Fri, 1 Mar 2013 19:40:56 +0000]
usb: xhci: tegra: disable regulators in lp0 path

We should be disabling all xusb regulators except vbus to
save power. Vbus regualtor is needed for xusb LP0 wakeup
capability.

Also changes the sequence of regualtor enable and disable
as listed below. The older sequence is causing kernel
panic during LP0 exit path.

Enable sequence:
regulator_enable(tegra->xusb_vddio_hsic_reg);
regulator_enable(tegra->xusb_hvdd_usb3_reg);
regulator_enable(tegra->xusb_vbus_reg);
regulator_enable(tegra->xusb_avddio_usb3_reg);
regulator_enable(tegra->xusb_avdd_usb3_pll_reg);

Disable sequence:
regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
regulator_disable(tegra->xusb_avddio_usb3_reg);
regulator_disable(tegra->xusb_vbus_reg);
regulator_disable(tegra->xusb_hvdd_usb3_reg);
regulator_disable(tegra->xusb_vddio_hsic_reg);

Bug 1245553

Change-Id: I39b2c5437f39306965e49d7247347a0e91241f0f
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/205735
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agousb: xhci: tegra: fix padctl intr handler
Bharath Yadav [Thu, 28 Feb 2013 09:51:53 +0000]
usb: xhci: tegra: fix padctl intr handler

This fixes the hang issue seen when SS link training fails,
causing constant padctl intr triggering elpg entry/exit.

We should not be doing ss elpg exit without host elpg exit.

Bug 1238452

Change-Id: I340b4556b22b2c729ea121966b29f013b935e532
Signed-off-by: Bharath Yadav <byadav@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/205729
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agommc: tegra: Enable calibration for sdmmc4
Pavan Kunapuli [Sat, 9 Feb 2013 13:49:30 +0000]
mmc: tegra: Enable calibration for sdmmc4

Enable auto calibration for sdmmc4 on T148 chips. Disable it only
for T11x chips

Change-Id: I4ee26e79a03fd603c260964bd28ae0b69aa1c41c
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/199103
(cherry picked from commit d200ba8f830e84443602ed94c7a15a53402f98d2)

Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Change-Id: Iba470a3d529155882132eed2df6ca5c461dcd628
Reviewed-on: http://git-master/r/205485
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoregulator: palmas: Added regulator support for TPS80036 PMIC
Sumit Sharma [Wed, 13 Feb 2013 10:19:21 +0000]
regulator: palmas: Added regulator support for TPS80036 PMIC

Added REGEN regulator support in palmas driver for TPS80036

Change-Id: Ic65e79cdabd6b093b61fc0fe1670a59ace034088
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200398
(cherry picked from commit 5ccccee268d0408f09fe8d10be7474a697ef71db)
Reviewed-on: http://git-master/r/205425
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agogpio: palmas: Added gpio support for TPS80036 PMIC
Sumit Sharma [Wed, 13 Feb 2013 10:17:55 +0000]
gpio: palmas: Added gpio support for TPS80036 PMIC

Added support for more number of GPIOs for TPS80036

Change-Id: I6eab1c4ba65182a5d968b60349a972a4cf6e67cd
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200397
(cherry picked from commit e64966e899fd810f40840fb1212bdfff3d6fc04f)
Reviewed-on: http://git-master/r/205424
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoxusb: Use pmc and pad ctrl apis
Krishna Yarlagadda [Thu, 28 Feb 2013 05:11:31 +0000]
xusb: Use pmc and pad ctrl apis

Changes to use common pmc and pad ctrl apis provided
to avoid code ovelap and conflicts between
USB2.0 and USB3.0

Bug 1225060

Change-Id: Ia93698fc4691f7d7dd7cdbf3fbf14d77b72cf04b
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/205106
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agoARM: tegra14x: Remove timeout from LP1BB
Prashant Malani [Fri, 22 Feb 2013 07:38:41 +0000]
ARM: tegra14x: Remove timeout from LP1BB

The 10ms timeout for LP1BB does not
guarantee reduction in LP1BB latencies.
Therefore it is removed for the time being.

We also reduce the duration of waits used during
mem_req interrupt programming.

Bug 1236920

Change-Id: I7501cc7103444afc2b771087f7da7abe1ecbee4b
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/203200
(cherry picked from commit 33168bcd93be2ed86d55f3b3e9c9715a0b118a08)
Reviewed-on: http://git-master/r/204899
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoarm: tegra: ceres: enable soctherm with preliminary settings
Diwakar Tundlam [Wed, 27 Feb 2013 22:56:40 +0000]
arm: tegra: ceres: enable soctherm with preliminary settings

Three soctherm trip points enabled for T148 on Ceres.
CPU EDP and other Tj trip points are bound to nct device.

Bug 1242336
Bug 1243563

Change-Id: I2c7d79f7bf6bcbaf221d90d14b5e35d11d606f37
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/204877
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>