5 years agoARM: tegra: bonaire: rename tegra system timer
Alex Van Brunt [Thu, 10 Jan 2013 01:26:00 +0000]
ARM: tegra: bonaire: rename tegra system timer

Change-Id: Ia4542dc990ffffae78e3b3a4df0e7bc682163d31

5 years agoARM: tegra12: init irq from device-tree
Alex Van Brunt [Thu, 10 Jan 2013 01:22:45 +0000]
ARM: tegra12: init irq from device-tree

bug 1164943

Change-Id: Ib546cfbd916e4aae2cba249fb845e524cf518f57

5 years agoMERGE FIXUP: cpuidle: add support for states that affect multiple cpus
Alex Van Brunt [Tue, 27 Nov 2012 18:37:39 +0000]
MERGE FIXUP: cpuidle: add support for states that affect multiple cpus

Change-Id: I2fb6c178b4c3b4612bb89a597d0123dd7d7e7fc6

5 years agoARM: tegra: Add Tegra mach-types back
Alex Van Brunt [Wed, 21 Nov 2012 01:17:12 +0000]
ARM: tegra: Add Tegra mach-types back

Change-Id: I8bb5e400e85e63f1596fe28d05c63b79aa72a5e5

5 years agoregulator: Remvoe extra regulator stub from merge
Alex Van Brunt [Wed, 9 Jan 2013 23:16:38 +0000]
regulator: Remvoe extra regulator stub from merge

Change-Id: I7ef6a0dfcb6f599b80719fc0b0c692b729414670

5 years agoARM: tegra12: Add spare fuse definition for 12x
Alex Van Brunt [Wed, 9 Jan 2013 22:39:43 +0000]
ARM: tegra12: Add spare fuse definition for 12x

For now, tegra12x uses the same fuse as tegra3x for the spare bit.

Change-Id: Ie5d9a37455fc73a460a919cd62ccf9b83b098f50

5 years agoHACK: tegra12: Diable ARCH_TIMER for now
Alex Van Brunt [Wed, 9 Jan 2013 21:34:17 +0000]
HACK: tegra12: Diable ARCH_TIMER for now

ARCH_TIMER doesn't work yet on our 3.7 branch. Once it works, this
change should be reverted.

Change-Id: Ie3190d5ee6249f3f6cf43dd0a8f73dfece2e22f8

5 years agoARM: tegra: bonaire: add UART support
Kunal Agrawal [Mon, 24 Dec 2012 11:28:45 +0000]
ARM: tegra: bonaire: add UART support

added code to enable and initialize uart on
bonaire platform.

Change-Id: I89a92b2e7d0f3c9969f95f4a56ed3b265c4372f7
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/174113
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: bonaire: enable UART
Kunal Agrawal [Wed, 26 Dec 2012 04:20:47 +0000]
ARM: tegra: bonaire: enable UART

Enable UART on bonaire

Change-Id: I75fc3f8cc2dd12627720d395b783d7e99f009803
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/174190
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: Hack for nvhost code to work.
Alex Waterman [Mon, 17 Dec 2012 17:46:03 +0000]
video: tegra: host: Hack for nvhost code to work.

Should be properly fixed at some point in the future.

Change-Id: I1e9609a578e4b29aea1358e6301fbd95812f90b0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/172016
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: kernel: GCOV needs android toolchain
Alex Waterman [Thu, 13 Dec 2012 21:53:03 +0000]
arm: kernel: GCOV needs android toolchain

Alert GCOV that the toolchain being used is the Android
toolchain not the generic gcc toolchain. If this config
option is not set, then the kernel will crash on boot.

Change-Id: I21567919c300d8ad5e969b99b1ce7cdae17e261b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/171165
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: fixup for merge
Alex Waterman [Thu, 13 Dec 2012 01:29:12 +0000]
ARM: tegra12: dvfs: fixup for merge

Parts of commit 0bedc869b11e58def2fd3ad10185f0e002c8e2d3
were missed. This simply adds those bits in since they now
became necessary after the merge.

Change-Id: I32e5389d26e7c37523acb978c738cdeb85576c53
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/171132
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: fix cclk_g mux value for net13 header change
Chao Xu [Mon, 3 Dec 2012 18:24:34 +0000]
ARM: tegra12: clock: fix cclk_g mux value for net13 header change

NET13 header swapped field definitions between PLLX_OUT0 and PLLX_OUT0_LT.
We had to change the field bits to continue accessing PLLX_OUT0. This needs
to be followed up because for t114 both CPU_CLK and PLLX_OUT0 use the _LT
signals.

Change-Id: Icc29355f648630e63977393372028ca59c296fea
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/168103
Reviewed-by: Automatic_Commit_Validation_User

5 years agodrivers: video: tegra: update T12x host1x headers to net13
Chao Xu [Wed, 14 Nov 2012 23:31:31 +0000]
drivers: video: tegra: update T12x host1x headers to net13

Change-Id: I891a418ef08634a91d7b64127112a4e035eb2678
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/163725
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: enable gk20a vpr channel
Jin Qian [Mon, 10 Dec 2012 21:13:05 +0000]
video: tegra: host: enable gk20a vpr channel

Add vpr buffer for circular buffer and pagepool buffer but
still allocate from generic carveout until vpr heap is enabled
in tot kernel.

Bug 1186721
Change-Id: I75aa887c63be292b47781416345d19299e082d7f

Signed-off-by: Jin Qian <jqian@nvidia.com>
Change-Id: I1d922cf83fc9a5647cac169a341119214de57df7
Reviewed-on: http://git-master/r/169797
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: host: add gk20a pmu perfmon
Jin Qian [Thu, 15 Nov 2012 19:28:01 +0000]
video: tegra: host: add gk20a pmu perfmon

Bug 1168529

Change-Id: Icc047eaf6711f5b2c6975e04a3d65c5937720bc0
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/164025
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: update gpu dvfs
Jin Qian [Wed, 5 Dec 2012 19:46:43 +0000]
ARM: tegra12: dvfs: update gpu dvfs

Change-Id: I69317ed5cb86ddca8732a73dd5ecdd4e3a2f485a
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/168820
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Update PLLC2/C3 startup sequence
Bhanu Chetlapalli [Wed, 5 Dec 2012 20:06:01 +0000]
ARM: tegra12: clocks: Update PLLC2/C3 startup sequence

T124 changes the type of C2 & C3 PLLs which need IDDQ handling

Bug 1001865

Change-Id: I93e3b1a251df7a3d33330843a2d32a64024b5fc9
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/168816
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: HACK: Mark ISP/VI as keepalive
Bhanu Chetlapalli [Tue, 4 Dec 2012 20:03:51 +0000]
drivers: video: tegra: HACK: Mark ISP/VI as keepalive

Bug 1188795

Change-Id: Icffc17c3cad33223aef4d44ba8ca6464d5986223
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/168431
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: Update VI struct
Bhanu Chetlapalli [Fri, 30 Nov 2012 22:24:17 +0000]
drivers: video: tegra: Update VI struct

Add CSI clock to VI, since they are dependant on the same unit
Also a single clock controls both ISPs (and there is only 1 VI unit),
so removing the ".1" from the clock name

Bug 1175411

Change-Id: I9f8b9d859a2003c190d1ec7268786ad9da113059
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/167843
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Add aliases for camera devs
Bhanu Chetlapalli [Fri, 30 Nov 2012 22:20:44 +0000]
ARM: tegra12: clocks: Add aliases for camera devs

Device VI controls VI & CSI clocks
Both ISP devices control ISP clock

Bug 1175411

Change-Id: I455318ccd8986320b430cd2511735ad124171d9e
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/167842
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Update clk_out enable masks to NET12
Bhanu Chetlapalli [Tue, 13 Nov 2012 00:48:17 +0000]
ARM: tegra12: clocks: Update clk_out enable masks to NET12

Bug 1164664

Change-Id: Ic03e0b49b409334e319b3714ff124162e3e6eb95
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/163161
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Update clocks to NET12
Bhanu Chetlapalli [Tue, 20 Nov 2012 20:30:22 +0000]
ARM: tegra12: clocks: Update clocks to NET12

Fixed many incorrect register settings & updates clocks to agree
with clocking policy

Bug 1164664

Change-Id: Ia24b22b1618afe42a9720aa7d3e29222aa1ae593
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/165130
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: add dummy entry for vic03
Jin Qian [Wed, 5 Dec 2012 01:46:43 +0000]
ARM: tegra12: dvfs: add dummy entry for vic03

Change-Id: Ibe90127ee511ae0af723d0a74b6abdb090208625
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/168544
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: syncpt WAR for ISP
Amit Arora [Mon, 17 Sep 2012 17:24:49 +0000]
drivers: video: tegra: syncpt WAR for ISP

This change sets NVSYNCPT_ISP_0_0 to NVSYNCPT_MPE to unblock
camera team till more than 32 syncpoints are supported.

Change-Id: If25f60bb9728bb1cf092a64b383414c1d64ab268
Signed-off-by: Amit Arora <amita@nvidia.com>
Reviewed-on: http://git-master/r/133284
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Tested-by: Ken Adams <kadams@nvidia.com>

5 years agoARM: tegra: bonaire: update pinmux settings for NET2_CORE4
Jin Qian [Wed, 28 Nov 2012 22:23:05 +0000]
ARM: tegra: bonaire: update pinmux settings for NET2_CORE4

Change-Id: I5b1644aa70a35c21af749398d7192c2c92df6fd0
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/167078
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agotegra: host: gk20a: cache flushes
Bob Bond [Thu, 27 Sep 2012 21:55:42 +0000]
tegra: host: gk20a: cache flushes

Add cache flushes to the gk20a pte setup and simulation code

Change-Id: I3f1d0e4f20a3bcfe91ba47e99bb42750371f9592
Signed-off-by: Bob Bond <rbond@nvidia.com>
Reviewed-on: http://git-master/r/139418
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: bonaire: disable SMMU on FPGA
Jin Qian [Thu, 15 Nov 2012 21:44:59 +0000]
ARM: tegra: bonaire: disable SMMU on FPGA

Change-Id: I20708493a12508f2d7c0d59229f068fa45761432
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/164056
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>

5 years agodrivers: video: tegra: Tegra12 ispb device/resources
Ken Adams [Wed, 28 Nov 2012 18:13:59 +0000]
drivers: video: tegra: Tegra12 ispb device/resources

Adds register resources and device for ispb module.

Change-Id: Ie954a66fab10c1fcbf805e8ac4024c8619d9c395
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/145623

5 years agoARM: tegra: iomap: Tegra12 ISP
Ken Adams [Thu, 18 Oct 2012 22:14:24 +0000]
ARM: tegra: iomap: Tegra12 ISP

Updates ISP and ISPB addresses.

Change-Id: Ib10b45557b19bd6473e14af17457063ac1628225
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/145722

5 years agodrivers: video: tegra: update T12x host1x headers
Ken Adams [Wed, 28 Nov 2012 17:37:43 +0000]
drivers: video: tegra: update T12x host1x headers

Removed some (now) superflous hand-generated host1x definitions.

Change-Id: If3b27c1c5c113acbf0d8a813af7c62ab574960e5
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/167009

5 years agodrivers: video: tegra: fix host1x includes
Ken Adams [Wed, 28 Nov 2012 07:50:26 +0000]
drivers: video: tegra: fix host1x includes

host1x02 and host1x04 were being included improperly
in a few places.  fixed to remove the host1x02 versions.

Change-Id: Ia9dc34cb32a13aea0643f2af602d22ef66e9092a
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/166820

5 years agoARM: tegra: merge fixups
Ken Adams [Tue, 27 Nov 2012 19:14:41 +0000]
ARM: tegra: merge fixups

This change accounts for changes necessary due to
change http://git-master/r/161923 in the previous merge.

Change-Id: Ie0b1454d4ac051a473a793c9cab449da2fe866d9
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/166644
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>

5 years agodrivers: video: tegra: fix qt regression
Jin Qian [Wed, 14 Nov 2012 02:00:33 +0000]
drivers: video: tegra: fix qt regression

device num_clks is wrong from merge.

Change-Id: I1ce7a3330229e5e598ebe5f11b3e16bceb71fa40
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/163644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: fix t124 i2c6 and pll_p_out5 offsets
Jin Qian [Fri, 16 Nov 2012 23:13:32 +0000]
ARM: tegra12: clock: fix t124 i2c6 and pll_p_out5 offsets

Bug 1164664

Change-Id: I5a935b9c59371d395465a23814966e8ad6393d61
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/164445
Reviewed-by: Edgardo Handal <ehandal@nvidia.com>
Tested-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: gk20a: don't break signals
Robert Morell [Tue, 13 Nov 2012 02:02:54 +0000]
drivers: video: tegra: gk20a: don't break signals

wait_event_interruptible will return ERESTARTSYS if a signal is pending.
We can't deal with this properly in many cases because we've already
changed hardware state and can't back out.  For these cases, use a
lengthy timeout rather than *_interruptible.

Change-Id: I152d571c56e2424f3baf5f7eb30590ecd3685c9d
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/163182
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: Increase gr idle timeout
Adeel Raza [Tue, 6 Nov 2012 20:16:26 +0000]
drivers: video: tegra: Increase gr idle timeout

Increase GR_IDLE_TIMEOUT_DEFAULT to 20000 usecs for
CONFIG_TEGRA_SIMULATION_PLATFORM.

Change-Id: I9f345b6ddb47bc232550c40e82c655365a53d0d9
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/161759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: bonaire: Lower UART clock for only QT
Adeel Raza [Tue, 13 Nov 2012 00:44:20 +0000]
ARM: tegra: bonaire: Lower UART clock for only QT

Previously UART clock was being lowered for ASIM + QT and pure QT. UART
clock only needs to be lowered for pure QT.

Bug 1166332

Change-Id: Ifcc8b7291fa45313b01ac67d96326e7de928c843
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/163153
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: update tegra12x clock table
Jin Qian [Thu, 8 Nov 2012 20:34:30 +0000]
ARM: tegra12: clock: update tegra12x clock table

Bug 1164664

Change-Id: Iea5e10edeb99180e61f98b2887e6691d8e665cba
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/162468
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: add gpu ioctl based zbc ctrls
Jin Qian [Wed, 7 Nov 2012 23:27:23 +0000]
drivers: video: tegra: add gpu ioctl based zbc ctrls

Change-Id: Ibebaeb302591333e31ec9c0623d7f720e472b929
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/162153
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: add a new field for gk20a pmu cmdline arg
Jin Qian [Wed, 7 Nov 2012 02:32:02 +0000]
drivers: video: tegra: add a new field for gk20a pmu cmdline arg

Match kernel with newer pmu ucode built from chips_a 14315261.
This change is compatible with current pmu ucode.

Change-Id: I7a923b641cb5e60292eb7acfd847736b943fe057
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/161843
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: host: remove channel zcull ioctls
Jin Qian [Tue, 6 Nov 2012 20:39:40 +0000]
drivers: video: host: remove channel zcull ioctls

NVHOST_IOCTL_CHANNEL_ZCULL_GET_SIZE
NVHOST_IOCTL_CHANNEL_ZCULL_GET_INFO

They're replaced by gpu ctrl ioctls.

Change-Id: Idaa3b972b77096e3ac90b22e94b18e53429bf34d
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/161780
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: HACK: set mem efficiency to 100
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:28 +0000]
ARM: tegra12: clock: HACK: set mem efficiency to 100

Change-Id: I734b831bb46388e2c5b7e0d5245ad75b0c8e9bf1
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/160946
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Use cvb model for pll clock source
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:27 +0000]
ARM: tegra12: dvfs: Use cvb model for pll clock source

da959dc5b8c2877468b27130f5d956c7d8cdb868: Use cvb model for pll clock source

Change-Id: Iefd4434bee225f578c55b8d76a312f1be5235ca7
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161403
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Don't apply dfll min voltage in pll mode
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:26 +0000]
ARM: tegra12: dvfs: Don't apply dfll min voltage in pll mode

28fa89d56de8b0691c684727f58e79e0d42e42b4: Don't apply dfll min voltage in pll mode

Change-Id: I54e0dc1c958f5214ef492c6f9dbfc3a2fb393cee
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161402
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Move min millivolts to dfll_data
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:25 +0000]
ARM: tegra12: dvfs: Move min millivolts to dfll_data

0bedc869b11e58def2fd3ad10185f0e002c8e2d3: Move min millivolts to dfll_data

Change-Id: Iaf213dfa3ec1642e0a45396de5f475a544e8f964
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161401
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Round up CPU dvfs frequency list
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:25 +0000]
ARM: tegra12: dvfs: Round up CPU dvfs frequency list

a2e058e8abfa328dcd6f82ac8e662090aaaf95a6 Round up CPU dvfs frequency list

Change-Id: Ida75ac26a35a518f84c1577aea29bb5d3be7f284
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161400
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update CPU rate and voltage range
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:24 +0000]
ARM: tegra12: dvfs: Update CPU rate and voltage range

1ee632fa39ef0fd73e567e4dfe9b557bc1d9f66f: Update CPU rate and voltage range

Change-Id: I342dbe73e1d1fc98bb42f6e1a5ef5487e2cd0e82
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161399
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Increased CPU min voltage limit
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:23 +0000]
ARM: tegra12: dvfs: Increased CPU min voltage limit

e5f3316a7b5a557feaf6eb93c9ee0e36d2c03471: Increased CPU min voltage limit

Change-Id: If876fc617457a6d4f0fac1d2eac639e7a593ee4c
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Round down CPU rate when run on pll
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:23 +0000]
ARM: tegra12: dvfs: Round down CPU rate when run on pll

4f887f9941d79104eba5747c261665ed06b77556 Round down CPU rate when run on pll

Change-Id: I9a5718eedc0cb31fc64eefe470df14430dbd020e
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161397
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Integrate dfll mode data with dvfs table
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:22 +0000]
ARM: tegra12: dvfs: Integrate dfll mode data with dvfs table

af81273fffc4ac402e5e8a4dc424465c039ee84b: Integrate dfll mode data with dvfs table

Change-Id: I6d88f3a51cee05eb7f2497038b9498015341aff0
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161396
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update XUSB clocks dvfs table
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:21 +0000]
ARM: tegra12: dvfs: Update XUSB clocks dvfs table

cf3b57e2d5b79f2dcd65635cadd873e3413d5226 Update XUSB clocks dvfs table

Change-Id: I5127bd7cc92570d59814e53485af0f0689b28781
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/160945
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: decrease sclk min limit
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:21 +0000]
ARM: tegra12: clock: decrease sclk min limit

9f82f47f9791bc63e6dd195cb0cf5fc9c9841441: decrease sclk min limit

Change-Id: Ib7cafeb329d8d6521f12bd961c608ed8eac47d42
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Switch from DFLL to PLL at low rate
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:20 +0000]
ARM: tegra12: clock: Switch from DFLL to PLL at low rate

72181d511d15193a95e860ac55a0a1d7d12d06ba: Switch from DFLL to PLL at low rate

Change-Id: Ia0d086ee146755cc84d376b3b1b51bd6b94f010c
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161393
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Fix G-to-G CPU switch
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:19 +0000]
ARM: tegra12: clock: Fix G-to-G CPU switch

5fbe3365d66c0e6ebadc92f47fb05ce61d4c6455: Fix G-to-G CPU switch

Change-Id: I7f19b60ace99a6e647b965aa35306ed0c3a320d5
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161392
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update DFLL switch error handling
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:19 +0000]
ARM: tegra12: clock: Update DFLL switch error handling

911ab103724f15fe4e1dd2167a26b3a9442c3d37: Update DFLL switch error handling

Change-Id: Ieeaab2ab0a7350ddcf98f04b543b79f5ab1c7361
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Remove pll table restriction
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:18 +0000]
ARM: tegra12: clock: Remove pll table restriction

905bfb114b30d7279178d9e1a51dd870ab6a2da7: Remove pll table restriction

Change-Id: Iac15abf5ca552523c3727bec4dada80615c8f4eb
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Dynamically allocate cl dvfs object
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:17 +0000]
ARM: tegra12: clock: Dynamically allocate cl dvfs object

1b483f1b12722347915b4c50f03e12788b41230d Dynamically allocate cl dvfs object

Change-Id: Iede93371aa77233e8135fbf0f5ae4fcc584b0aa7
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161389
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Acquire CL-DVFS clocks in probe
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:17 +0000]
ARM: tegra12: clock: Acquire CL-DVFS clocks in probe

ea8a25e4b67ea1b3ad94eaaf419370995e36563c: Acquire CL-DVFS clocks in probe

Change-Id: I14c2ce2152db9b2adac3250d216b6dccd6b1d036
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161388
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Enable PLLE VREG
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:16 +0000]
ARM: tegra12: clock: Enable PLLE VREG

9d9fcac3f42fcb904e009d79c6fdacddba8ff1b2 Enable PLLE VREG

Change-Id: I8b2d287d846c8d4e2ab547cfc340bf09d94705b5
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161386
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Put PLLU under h/w control
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:15 +0000]
ARM: tegra12: clock: Put PLLU under h/w control

bffc20e32302958441f87d2336e78876dceb2ee4 Put PLLU under h/w control

Change-Id: Iafc792d2fb01ebd75d616a78cf16d1ea1cf4913c
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161383
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/C3 configuration
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:15 +0000]
ARM: tegra12: clock: Update PLLC2/C3 configuration

30112f386b4697681d748e644517e56f5e8ae1cf Update PLLC2/C3 configuration

Change-Id: I3c649400529d30414637cce388f631334dd8a5d0
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161382
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add CL-DVFS platform device
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:14 +0000]
ARM: tegra12: clock: Add CL-DVFS platform device

7441d68b36611da86975f7788f037462816afc80 Add CL-DVFS platform device

Change-Id: Ic385d97b367905340a17ad2a82e5495b76cb945b
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161381
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Remove CL-DVFS I2C fast clock
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:13 +0000]
ARM: tegra12: clock: Remove CL-DVFS I2C fast clock

7d038460eb3280196f209498723ce5b12c0914de Remove CL-DVFS I2C fast clock

Change-Id: Ia8390c3ba3bdbb9ac54821302e33b0b5f8ae61ae
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161380
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add DFLL resume operation
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:12 +0000]
ARM: tegra12: clock: Add DFLL resume operation

d25398c7850650eb8f658481fba5272f2d98ad77 Add DFLL resume operation

Change-Id: I40302dc0247ac05a08cb73e14902546759b45cf0
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161379
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update cpufreq table construction
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:12 +0000]
ARM: tegra12: clock: Update cpufreq table construction

55c7ec8b0dc8f7aaaefcd53f86d8c472e203fd37 Update cpufreq table construction

Change-Id: I981e2a4001957821cff0b99e92926aabdd953945
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161378
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Increase PLLX vco max limit
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:11 +0000]
ARM: tegra12: clock: Increase PLLX vco max limit

30335b9ff69501f5bc8d923db6499e633ec9280f Increase PLLX vco max limit

Change-Id: I32a8235bd66ef2f7a5a2b715021a2478bc243c23
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161376
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Keep PLLE under s/w control
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:10 +0000]
ARM: tegra12: clock: Keep PLLE under s/w control

bbf27f133179ddfe4ad2e51b27c3be122810a8fe Keep PLLE under s/w control

Change-Id: I5329fc7e4fb221434404ee570c3ec7e6257c1706
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161373
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/C3 settings
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:10 +0000]
ARM: tegra12: clock: Update PLLC2/C3 settings

01ed444edb73107a5f0eafc26d29a07a4bef1561 Update PLLC2/C3 settings

    Bug 1053337

Change-Id: Ia665515db93600d548f783eab99ba7893cac2144
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161372
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add use dfll parameter callback
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:09 +0000]
ARM: tegra12: clock: Add use dfll parameter callback

732addf09be81e4100f8d9265a3bb7d472b20ebf Add use dfll parameter callback

Change-Id: Ic9a67c5398f7e9a600b35ab1ab86473998f2d1e0
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161371
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Update switch to/from dfll clock source
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:08 +0000]
ARM: tegra12: clocks: Update switch to/from dfll clock source

8f02cfdd2da7d47d83a99904e0bb3450e9a8543e Update switch to/from dfll clock source

Change-Id: Ide879a613428166957527dfc0484b971b018f22b
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161370
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: warn only when error not expected
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:08 +0000]
ARM: tegra12: clocks: warn only when error not expected

4584a9752a2f77d4cc8507b2b8f8c9d4f851e2d4: warn only when error not expected

Change-Id: I84629111f80242602066e9a445325c3c22a335d1
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161369
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Correct HDA device ids
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:07 +0000]
ARM: tegra12: clock: Correct HDA device ids

2712e4c1d93618bf09083d07c05a29dcfcca9ef2 Correct HDA device ids

Change-Id: I2f71d23b9b90d39d1aaf253b1a1f3c15a5a5a2e7
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161368
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/C3 configuration
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:06 +0000]
ARM: tegra12: clock: Update PLLC2/C3 configuration

e58689bd9190388e164ececab9d7b4c765c5e4db Update PLLC2/C3 configuration

Change-Id: Icc2c635d32c235d21b94d91aee024e1ce41d7c27
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161366
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Round down CPU rate when run on pll
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:06 +0000]
ARM: tegra12: clocks: Round down CPU rate when run on pll

4f887f9941d79104eba5747c261665ed06b77556 Round down CPU rate when run on pll

Change-Id: I7cfbdce98dc3d1438b63b41bd9541e1e19ea978d
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161362
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Increase clk_out2 maximum rate to 40.8MHz
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:05 +0000]
ARM: tegra12: clock: Increase clk_out2 maximum rate to 40.8MHz

b9e1c736e6f45be1d8ca2a7d88c81801bf08d6d9 Increase clk_out2 maximum rate to 40.8MHz

Change-Id: I1ac97579baada3260b644fe6d151cbefa4b274b1
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161347
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/3 default settings
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:04 +0000]
ARM: tegra12: clock: Update PLLC2/3 default settings

187d535f06ee13bad577c839d2ea9f0f75aa8f00 Update PLLC2/3 default settings

Change-Id: Iebb0753b08a364346c180a687bcb0d11c11eef33
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161346
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: HDMI TMDS and PLL setup
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:04 +0000]
ARM: tegra12: clock: HDMI TMDS and PLL setup

861009a83a9a3c761b4e848125ea6e1e4cce842c HDMI TMDS and PLL setup

    Reviewed-on: http://git-master/r/133418

Change-Id: I31980025beb2fdf23a189d4ab4ffeaa43341af9e
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161345
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Provide WAR for MSENC clock propagation
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:03 +0000]
ARM: tegra12: clock: Provide WAR for MSENC clock propagation

b9ecdbdf477b6afe77dfc10ffb5cb634de6a5c5e Provide WAR for MSENC clock propagation

    Bug 1005168

    Reviewed-on: http://git-master/r/133366
    (cherry picked from commit 7671be9a888a62f7db9d87005d3f644302fc667e

Change-Id: I24868a1a3faaae2d06017b3330de690603a3e846
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161343
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Fix function init annotation mismatch
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:02 +0000]
ARM: tegra12: clock: Fix function init annotation mismatch

07bad5984f869255f391eddb38dcc47e3451efe8 - Fix function init annotation mismatch

Change-Id: I1f16628ccf865ce1a5a6600dcb9a7a05bb9fc325
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161342
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Clock table entry for MIPI CAL is added
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:01 +0000]
ARM: tegra12: clock: Clock table entry for MIPI CAL is added

967e016b8c549f7fd3d53e91d18a8f41fe8ac7e4   Clock table entry for MIPI CAL is added for T11x

Change-Id: I7600a763b78d500b0cebb63e7e7136ed98c6d8ab
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161341
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add support for PLLE
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:01 +0000]
ARM: tegra12: clock: Add support for PLLE

1b5abd3d19c246018c7d7e5874aa52a00cfd740a Add support for PLLE

    Reviewed-on: http://git-master/r/132940
    (cherry picked from commit 9592caf7cfba60c02fd6dcd07b4c02946c4ee3f5

Change-Id: I1d01c43702821246883e5aa2100133a0d3463b65
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161339
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Merge commit main-jb-2012.09.27-B1
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:00 +0000]
ARM: tegra12: clock: Merge commit main-jb-2012.09.27-B1

953aa48aef738dcba99601fd37b58580273c9c3e
   Merge: 7d6fe62 f3c7b01
   Date:   Tue Oct 9 19:36:22 2012 -0700

    Merge commit 'main-jb-2012.09.27-B1' into t148-1009

Change-Id: I65da40e4235d582c68f6b70f6d18e36ade51838c
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161338
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: bonaire: turn on ICEDCC
Jin Qian [Tue, 6 Nov 2012 03:27:14 +0000]
ARM: tegra: bonaire: turn on ICEDCC

Change-Id: I7704a5cf939067f292dc0840778861bfa728c8b4
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/161498
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: protect gk20a runlist with pmu mutex.
Jin Qian [Sat, 3 Nov 2012 00:07:40 +0000]
drivers: video: tegra: protect gk20a runlist with pmu mutex.

ELPG entry sequence touchs runlist. Driver need to coordinate with
gk20a PMU for exclusive access on updating runlist and doing channel
pre-emption.

Bug 1170122
Bug 1171121

Change-Id: Ie93d1ab76e668c8ae08e783fa88150f136e5d2b5
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/161029
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: gk20a: Fix kzalloc usage
Alex Van Brunt [Wed, 31 Oct 2012 22:24:15 +0000]
video: tegra: gk20a: Fix kzalloc usage

Swap the parameter order in some uses of kzalloc so that they are
correct.

Change-Id: I9a853951a4d86334af2fdd775c2f7be9f6c61ceb
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/160348
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

5 years agoARM: tegra12: clock: Fix CPU clock source initialization
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:55:59 +0000]
ARM: tegra12: clock: Fix CPU clock source initialization

Pull in change
2f42a335a5104b045c89f29d6314f0b46b11be04: Fix CPU clock source initialization

Change-Id: Ie6a4568b04a1c38bf2b168cad6be919539a368b4
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/160944
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: Fix merge build issues
Hoang Pham [Wed, 7 Nov 2012 04:37:19 +0000]
ARM: tegra12: Fix merge build issues

Change-Id: I8dae8284418b08c8fe958d6223fb326ff36e5a70
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/161864
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: remove timeout for gk20a wait_event
Jin Qian [Fri, 2 Nov 2012 01:34:49 +0000]
drivers: video: tegra: remove timeout for gk20a wait_event

asim timing is too fast for wait. I have to use 10 sec for pmu actions.
Also timeout leaves driver in an inconsistent state w/o recovery code.
So just remove timeout for now but keep it interruptible.

Bug 1169237

Change-Id: I09c792b7f35b521e68c77b7b3bfb3524362042a0
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/160747
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Acorn Pooley <apooley@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: remove gk20a cache flush for pde/pte
Jin Qian [Wed, 31 Oct 2012 01:53:32 +0000]
drivers: video: tegra: remove gk20a cache flush for pde/pte

pte/pde are set to volatile, no need to flush L2 other than
invalidate tlb.

Change-Id: I35c6c342145a3d23076d049ce2129f96b65489e3
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/160088
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: bonaire: enable DCC
Jin Qian [Tue, 30 Oct 2012 19:00:55 +0000]
ARM: tegra: bonaire: enable DCC

Change-Id: I8f7c1c4f092d5c2040bb85098415311a118c8177
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/159950
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: release mem_handle after unmap_buffer
Jin Qian [Fri, 26 Oct 2012 21:52:07 +0000]
drivers: video: tegra: release mem_handle after unmap_buffer

Kernel duplicates user mem handle before map_buffer but never
releases it. This is causing mem leak.

Added vm_map_user to return handle/mem_mgr to caller since
only callers knows where the handle come from.

Remove deprecated channel_map_buffer ioctls.

Bug 1161272
Bug 1167583

Change-Id: I71e34720fc55245180c303d41377ff06fa4e73ce
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/159288
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Acorn Pooley <apooley@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: add new gpfifo entry format
Jin Qian [Tue, 23 Oct 2012 19:58:53 +0000]
drivers: video: tegra: add new gpfifo entry format

Bug 1162419

Change-Id: I1d430edb422cabf392f10d97d0a2927409e03542
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/147043
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Acorn Pooley <apooley@nvidia.com>
Tested-by: Acorn Pooley <apooley@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: remove gk20a temp_ctx_header
Jin Qian [Thu, 11 Oct 2012 00:20:43 +0000]
drivers: video: tegra: remove gk20a temp_ctx_header

Change-Id: I3607a9b6bcd11ab47a7e8ec2a17a6f3dfa9b2957
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/143397
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoFix merge build issues
Bhanu Chetlapalli [Thu, 1 Nov 2012 19:40:35 +0000]
Fix merge build issues

Change-Id: I03cbd53fd3a5cd5a0c63a475719cf18a4997dbea
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/160652
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: bonaire: fix UARTA pinmux for FPGA
Jin Qian [Fri, 19 Oct 2012 01:43:06 +0000]
ARM: tegra: bonaire: fix UARTA pinmux for FPGA

Change-Id: I9b400ab7139eaa0c7b922fe3a7deb31561a5ed3c
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/145813
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

5 years agodrivers: video: tegra: add wfi before gk20a host syncpt increment
Jin Qian [Tue, 9 Oct 2012 23:50:01 +0000]
drivers: video: tegra: add wfi before gk20a host syncpt increment

Fix a bug when priv_cmdbuf goes around the end of circular buffer

Bug 1155990

Change-Id: Ifdfe1e02ed347f5f1e62800068d206dda687480d
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/142811
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

5 years agodrivers: video: tegra: refine gk20a gr idle wait
Jin Qian [Tue, 9 Oct 2012 02:02:27 +0000]
drivers: video: tegra: refine gk20a gr idle wait

Check fifo engine status for gr ctxsw.
gr is NOT idle if ctxsw is active OR gr engine is busy.

Caller of gr_gk20a_wait_idle need to provide a value for polling
delay. This value is doubled each time a polling failed but the
max delay is limited by a pre-defined value.

Use same delay increment for other idle pollings in gr code.

Change-Id: Ie5751381f91ea7ec2530a61de6e6c076aa0a4f0f
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/142547
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

5 years agodrivers: video: tegra: move gk20a runlist update to fifo code
Jin Qian [Tue, 9 Oct 2012 00:35:07 +0000]
drivers: video: tegra: move gk20a runlist update to fifo code

Added two special case for suspend/resume.

1. chid == ~0 and add == false for suspend
Remove all active channels from runlist but runlist->active_channels
is retained for resume.

2. chid == ~0 and add == true for resume
Add back all runlist->active_channels to runlist.

Change-Id: Ibe4a7c5d5df2420729c93bd4acbf4c01a7a8af6d
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/142533
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

5 years agodrivers: video: tegra: share same code for gk20a vms
Jin Qian [Mon, 8 Oct 2012 23:38:45 +0000]
drivers: video: tegra: share same code for gk20a vms

gk20a channel, bar1, pmu vm are essentially same.

Change-Id: Ia76a148a1bd91c6839e0619b2e219bc21ff11965
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/142509
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>