6 years agoarm: tegra: power: enable dynamic VDD_CPU EDP capping
Bhanu Chetlapalli [Fri, 21 Sep 2012 08:02:42 +0000]
arm: tegra: power: enable dynamic VDD_CPU EDP capping

Picked from tegra11 & applied to tegra12
Original Commit: 526812684ac41bcf20eb452628498fc200e0964a

Using the model used to enforce max frequency for a given VDD_CPU EDP.
Enabled for dalmore and pluto.

Initialised edp_reg_override to 6A and increased default per-platform
edp-limit higher by 6A to allow users to override the limit up by upto
6A when needed for specific use-cases.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 9648d86f4a9a7b3b2557e98530e8265ea9f53467)
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ie6deec42bd555f2395d72337747cacb18d794bcb
Reviewed-on: http://git-master/r/193135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Put UTMIPLL under h/w control
Bhanu Chetlapalli [Wed, 10 Oct 2012 05:25:08 +0000]
ARM: tegra12: clock: Put UTMIPLL under h/w control

Picked from tegra11 & applied to tegra12
Original Commit: 32fdc7f8d32e47ec0c9e893bbe47d65d54cfe2dc

Programming UTMIPLL register to let hardware to
control UTMIPLL.

Bug 1057339

(cherry picked from commit 6ff04c9acbb229e22410f7d70e4e127dc6768a34)

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I646c56ba1dfdbeaf2e29984b1f39d68c0bb593b6
Reviewed-on: http://git-master/r/193134
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: fix curacao_sim build break
Bhanu Chetlapalli [Mon, 22 Oct 2012 17:47:59 +0000]
ARM: tegra12: clock: fix curacao_sim build break

Picked from tegra11 & applied to tegra12
Original Commit: 2597328141764ab70cd703a10303d246bd810715

Fixes unused warning-as-error problems with curacao_sim
build target.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ibcf040e66e67ceba641e7c81fc0d4cff5ab02abd
Reviewed-on: http://git-master/r/193133
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agovideo: tegra: fix build breaks
Stefan Becker [Tue, 22 Jan 2013 10:30:12 +0000]
video: tegra: fix build breaks

- correct inclusion of chip specific code

Bug 1211729

Change-Id: I12198f2a6d4272eefc4dc8a8753d502efd1fdd3f
Signed-off-by: Stefan Becker <stefanb@nvidia.com>
Reviewed-on: http://git-master/r/193025
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: Fix VIC clock register
Terje Bergstrom [Wed, 9 Jan 2013 08:15:30 +0000]
ARM: tegra12: Fix VIC clock register

VIC clock register and bit offsets have changed.

Bug 1181569

Change-Id: I7384ef59464e70016fd3c5883ed4bc88d8a293b3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/189873
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoarm: tegra: bonaire: Change SE device data name
Shravani Dingari [Tue, 22 Jan 2013 09:11:33 +0000]
arm: tegra: bonaire: Change SE device data name

Bug 1206795

Change-Id: If6cf79e173800919d06bf1b7e40177bbfe7df666
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/191550
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agoarm: configs: bonaire: Enable Tegra SE
Shravani Dingari [Tue, 22 Jan 2013 08:52:44 +0000]
arm: configs: bonaire: Enable Tegra SE

Enabled se_dev, cryptodev and crypto test support
in bonaire config

Bug 1206795

Change-Id: I1108509fbe29b8daf3359804023f1cfecdeb1adc
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/191542
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agocrypto: tegra-se: Fix clock and queue issues on FPGA
Shravani Dingari [Tue, 22 Jan 2013 05:33:46 +0000]
crypto: tegra-se: Fix clock and queue issues on FPGA

Changes required for T124 FPGA platform to run SE tests

Bug 1206795

Change-Id: I91d142c5330714e0899d8e45d8caa876cc8fb0a7
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/191986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agoARM: tegra12: clock: Update clocks for net14
Chao Xu [Sat, 5 Jan 2013 01:12:11 +0000]
ARM: tegra12: clock: Update clocks for net14

Change-Id: I440dc2353be5ff6fe7ba8b580c346e5e24a4dbd7
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/192447
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>

6 years agotegra: mc: change MC interrupt bit define 1207701
Xue Dong [Fri, 18 Jan 2013 21:07:29 +0000]
tegra: mc: change MC interrupt bit define 1207701

Bug 1156725
Change-Id: I221373a8b56f9953238d5f69a3f30a9b4f0a5ebd
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/192492
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: Fix clock detect on Qt after merge
Jin Qian [Fri, 18 Jan 2013 23:00:25 +0000]
ARM: tegra: Fix clock detect on Qt after merge

Change-Id: I77e7c4a43a36065c0752d583b88546556619ce94
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/192532
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: remove gpio enable/disable for bonaire
Xue Dong [Mon, 14 Jan 2013 00:50:57 +0000]
ARM: tegra: remove gpio enable/disable for bonaire

Change-Id: I828adbb7a64eb384f9445e351dea765e90778f51
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/190916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agotegra: remove netlist revision checking for QT
Xue Dong [Mon, 14 Jan 2013 18:59:42 +0000]
tegra: remove netlist revision checking for QT

Change-Id: Ica5b5dd680a2511856ddef1a410cd5d245785259
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/190985
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agotegra: host: gk20a driver use presilicon interface
Xue Dong [Mon, 14 Jan 2013 18:29:36 +0000]
tegra: host: gk20a driver use presilicon interface

Change-Id: I0bbd72d5f174fe780bc9644d1fe40bb98d304bda
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/190978
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: kernel fix QT platform detection
Xue Dong [Wed, 16 Jan 2013 18:27:36 +0000]
ARM: tegra: kernel fix QT platform detection

Change-Id: Id789dd0e410c11f64a37bbd938224e8c0a703898
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/190976
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agotegra: mc: add MC error handling support for T124
Xue Dong [Fri, 14 Dec 2012 01:48:10 +0000]
tegra: mc: add MC error handling support for T124

Bug 1156725
Change-Id: I1e5f820f41b2f9c7daa5947033c5b5e671942a41
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/170222
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: update gpfifo_hw format
Jin Qian [Thu, 15 Nov 2012 02:31:31 +0000]
drivers: video: tegra: update gpfifo_hw format

change nvhost_gpfifo struct to same as nvhost_gpfifo_hw
remove nvhost_gpfifo_hw once userspace tests are updated

Bug 1162419

Change-Id: I9a16f184e3fd1d9107bfe1bb29f31be7f1569075
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/163817
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: skip programming gk20a pll on qt
Jin Qian [Tue, 22 Jan 2013 22:23:02 +0000]
drivers: video: tegra: skip programming gk20a pll on qt

After reset gk20a a few times, init hangs in gk20a pll init.
Disable it for now while debugging the real problem.

Change-Id: Ifedec04b30977198e742bb6b701df074ec42275d
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/193159
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: remove deprecate t124 routines
Jin Qian [Sat, 12 Jan 2013 01:49:16 +0000]
drivers: video: tegra: remove deprecate t124 routines

Moved T124 ioctls to start from 100.

Bug 1040912

Change-Id: I79a01855f6d74edc0a9fd89549de9e948a6026b8
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/190811
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: enable gk20a deinit path
Jin Qian [Thu, 10 Jan 2013 01:32:04 +0000]
drivers: video: tegra: enable gk20a deinit path

gk20a deinit should run after prepare_poweroff is called,
which releasees hw states but preserves sw states. Then
gk20a deinit destroyes all sw states, i.e. mappings, buffers,
irqs, apertures, etc.

Fix a few memory leaks in gk20a deinit. Moved allocation from
gk20a_probe into init to match resource releases in deinit.

gk20a address space support depends on gk20a channel
so get/put channel to trigger init/deinit when necessary,
same for gk20a ctrl device node.

Skip ctag alloc for bar1 and pmu vm. ctag is destoryed
by gr deinit, which is before bar1/mm deinit.

Add a check on null nvmap ref handles before freeing them.

Bug 1199927

Change-Id: I09e39f725e24aa008027ea42b93e8260e0fecd0a
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/190151
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: added gk20a suspend/resume support
Jin Qian [Sat, 19 Jan 2013 02:52:04 +0000]
drivers: video: tegra: added gk20a suspend/resume support

Enable host1x to powergate gk20a when it's idle for a while.

gk20a doesn't support powergate but use railgate instead so stub
powergate with invalid powergate_id for now.

Insert syncpt increment method at end of each gpfifo submission
to keep track of method completion for host1x module idle check.

Add code to suspend/resume gk20a after railgate on/off. sw state
init is skipped and sw states are perseverd in memory. gk20a pmu
has no resume support. It's simply reset and init.

Add gk20a prepare_poweroff/finalize_poweron routines to support
real module idle/busy with powergating.

Remove code from gk20a init since gk20a will be railgated early
during boot and the init work is done by finalize_poweron every
time gk20a gets out of railgating (power on).

Add flags to remember whether sw states have been initialized
for each engine so that reinit can skip them.

Move ctx state init from sw init to hw init. Other than query
image sizes from fecs, the ucode also has a side effect to
initialize hw (ramchain, etc).

Add missing busy/idle calls for nvhost_as and gk20a ioctls.
It's important to call busy/idle correctly since they define
when gk20a is powered on/off.

Bug 795183

Change-Id: I2b770eea11c911ca213ffe614527bd3810ca0249
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/142760
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: update gk20a perfmon counter
Jin Qian [Fri, 18 Jan 2013 01:05:06 +0000]
drivers: video: tegra: update gk20a perfmon counter

Use counter #3 for GR and CE2 busy cycle counting.
Remove unused counter #4.

Bug 1218938

Change-Id: I455378c7744a905247e01de9d0ebaf09fce33fc0
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/192224
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: update to match gk20a pmu ucode (14822743)
Jin Qian [Wed, 16 Jan 2013 20:39:42 +0000]
drivers: video: tegra: update to match gk20a pmu ucode (14822743)

Bug 1218938

Change-Id: Ie53c00dfcc91392105e782d4c599e99c88037083
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/191779
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: add debug dump for gk20a falcon
Jin Qian [Wed, 16 Jan 2013 20:07:22 +0000]
drivers: video: tegra: add debug dump for gk20a falcon

Also move elpg dump to a separate function.

Bug 1218938

Change-Id: Ib86bfbfaa50842713da5ac4b4453d37f7f9d33e3
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/191778
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agovideo: tegra: host: remove gk20a clock slowdown during init
Jin Qian [Fri, 4 Jan 2013 01:29:09 +0000]
video: tegra: host: remove gk20a clock slowdown during init

gk20a has 32x clock slowdown when out of reset to save power.
driver removes this slowdown after graphics is initialized.

Bug 1164093
Bug 835296

Change-Id: I8b9b75e129d4b2d2de7f1fdd5b6d337830742114
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/188478
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agovideo: tegra: host: Enable VIC clock on boot
Terje Bergstrom [Tue, 8 Jan 2013 07:34:39 +0000]
video: tegra: host: Enable VIC clock on boot

Bug 1181569

Change-Id: Ibf01fe6747c9229d2d5111f640496592906d8c69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/189470
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agodrivers: video: tegra: Add gk20a support to net14
Chao Xu [Fri, 18 Jan 2013 18:53:33 +0000]
drivers: video: tegra: Add gk20a support to net14

Enable PLLG_ref and pllp_out5 for gk20a. Also add NETD_img.bin (bug 1197653).

Change-Id: I6fa9d1c2558553e331164aa341d7f625696c5205
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/192452
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>

6 years agotegra: dc: revert 187510 on simulator platform
Xue Dong [Thu, 17 Jan 2013 04:29:46 +0000]
tegra: dc: revert 187510 on simulator platform

Change-Id: Ief6c7a56d9dd6682fbfb649cce4013f87d9046c4
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/190918
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: Pre-silicon support for linsim and qt
Alex Van Brunt [Thu, 17 Jan 2013 18:08:55 +0000]
ARM: tegra: Pre-silicon support for linsim and qt

Don't call BUG() in pre-silicon code when the platform is not an
FPGA.

Change-Id: I9e05221d3e362a8d6fb74c9fc493fe462281373e
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra12: clocks: Fixup clocks for 3.7
Alex Van Brunt [Thu, 17 Jan 2013 16:40:53 +0000]
ARM: tegra12: clocks: Fixup clocks for 3.7

Fix the types used to call __raw_read and __raw_write.

Grab a handful of register definition changes that were hidden in
merges.

Change-Id: If34349f3a355cfd500b67eaecc95f8dcd06c144f
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>

6 years agotegra: host: fix T124 host sync point define
Xue Dong [Mon, 14 Jan 2013 00:12:04 +0000]
tegra: host: fix T124 host sync point define

Change-Id: Ide2bff80c0d46faaf731fea4cfafe984bc14dbd5
Signed-off-by: Xue Dong <xdong@nvidia.com>

6 years agotegra: remove netlist revision checking for QT
Xue Dong [Mon, 14 Jan 2013 18:59:42 +0000]
tegra: remove netlist revision checking for QT

Change-Id: Ica5b5dd680a2511856ddef1a410cd5d245785259
Signed-off-by: Xue Dong <xdong@nvidia.com>

6 years agoARM: tegra: remove gpio enable/disable for bonaire
Xue Dong [Mon, 14 Jan 2013 00:50:57 +0000]
ARM: tegra: remove gpio enable/disable for bonaire

Change-Id: I828adbb7a64eb384f9445e351dea765e90778f51
Signed-off-by: Xue Dong <xdong@nvidia.com>

6 years agotegra: mc: add mc error handling for T124
Xue Dong [Sun, 13 Jan 2013 23:33:01 +0000]
tegra: mc: add mc error handling for T124

Change-Id: I69e5a03e513c2b7d87c954032c3eb2aa71203e88
Signed-off-by: Xue Dong <xdong@nvidia.com>

6 years agoARM: tegra: Init tegra_apb_io before using it
Alex Van Brunt [Fri, 30 Nov 2012 22:05:58 +0000]
ARM: tegra: Init tegra_apb_io before using it

tegra_apb_io_init() needs to be called before fuse_init() because it will
call apb_read() which requires tegra_apb_io_init() to have been called.

Change-Id: Ib84c6e1fc1fadddd91310d4778beb14379e182fb

6 years agoARM: tegra12: Fix link problems in 3.7
Alex Van Brunt [Sat, 12 Jan 2013 00:32:35 +0000]
ARM: tegra12: Fix link problems in 3.7

Always compile headsmp.c to get tegra_resume.
Always compule reset.c to get tegra_cpu_reset_handler_save.
Turn on THERMAL to get thermal_cooling_device_register.

Change-Id: Ib69d2032b875b49b323eba2527544390f540c079
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>

6 years agovideo: tegra: host: Fix nvmap build errors
Alex Van Brunt [Fri, 11 Jan 2013 18:28:39 +0000]
video: tegra: host: Fix nvmap build errors

chip_support.h needs to be included to ge tthe definition of
struct nvhost_chip_support.

Change-Id: I49f1446361d2f69a601a8f7c0497f74472ac647e
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>

6 years agoFIXUP: video: tegra: host: Fixup host1x build errors
Alex Van Brunt [Fri, 11 Jan 2013 01:45:27 +0000]
FIXUP: video: tegra: host: Fixup host1x build errors

Fixes I2c531e491d140d00272dccdc8ff9f4ee5f403dc2

Change-Id: I5b20ea8066519fd509514167ec296c2c6967bebe

6 years agodrivers: video: tegra: update T12x host1x headers
Alex Van Brunt [Fri, 11 Jan 2013 01:38:34 +0000]
drivers: video: tegra: update T12x host1x headers

Add host1x_sync_intstatus_r.

Change-Id: Iac2634b412535ac721ade3ac688d7e5d723d1b2a

6 years agoFIXUP: video: tegra: host: New submit interface
Alex Van Brunt [Thu, 10 Jan 2013 22:04:45 +0000]
FIXUP: video: tegra: host: New submit interface

Change-Id: I1ffd4de35818fc379ff1e0378c2afe9408075f65

6 years agoARM: tegra: bonaire: rename tegra system timer
Alex Van Brunt [Thu, 10 Jan 2013 01:26:00 +0000]
ARM: tegra: bonaire: rename tegra system timer

Change-Id: Ia4542dc990ffffae78e3b3a4df0e7bc682163d31

6 years agoARM: tegra12: init irq from device-tree
Alex Van Brunt [Thu, 10 Jan 2013 01:22:45 +0000]
ARM: tegra12: init irq from device-tree

bug 1164943

Change-Id: Ib546cfbd916e4aae2cba249fb845e524cf518f57

6 years agoMERGE FIXUP: cpuidle: add support for states that affect multiple cpus
Alex Van Brunt [Tue, 27 Nov 2012 18:37:39 +0000]
MERGE FIXUP: cpuidle: add support for states that affect multiple cpus

Change-Id: I2fb6c178b4c3b4612bb89a597d0123dd7d7e7fc6

6 years agoARM: tegra: Add Tegra mach-types back
Alex Van Brunt [Wed, 21 Nov 2012 01:17:12 +0000]
ARM: tegra: Add Tegra mach-types back

Change-Id: I8bb5e400e85e63f1596fe28d05c63b79aa72a5e5

6 years agoregulator: Remvoe extra regulator stub from merge
Alex Van Brunt [Wed, 9 Jan 2013 23:16:38 +0000]
regulator: Remvoe extra regulator stub from merge

Change-Id: I7ef6a0dfcb6f599b80719fc0b0c692b729414670

6 years agoARM: tegra12: Add spare fuse definition for 12x
Alex Van Brunt [Wed, 9 Jan 2013 22:39:43 +0000]
ARM: tegra12: Add spare fuse definition for 12x

For now, tegra12x uses the same fuse as tegra3x for the spare bit.

Change-Id: Ie5d9a37455fc73a460a919cd62ccf9b83b098f50

6 years agoHACK: tegra12: Diable ARCH_TIMER for now
Alex Van Brunt [Wed, 9 Jan 2013 21:34:17 +0000]
HACK: tegra12: Diable ARCH_TIMER for now

ARCH_TIMER doesn't work yet on our 3.7 branch. Once it works, this
change should be reverted.

Change-Id: Ie3190d5ee6249f3f6cf43dd0a8f73dfece2e22f8

6 years agoARM: tegra: bonaire: add UART support
Kunal Agrawal [Mon, 24 Dec 2012 11:28:45 +0000]
ARM: tegra: bonaire: add UART support

added code to enable and initialize uart on
bonaire platform.

Change-Id: I89a92b2e7d0f3c9969f95f4a56ed3b265c4372f7
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/174113
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agoARM: tegra: bonaire: enable UART
Kunal Agrawal [Wed, 26 Dec 2012 04:20:47 +0000]
ARM: tegra: bonaire: enable UART

Enable UART on bonaire

Change-Id: I75fc3f8cc2dd12627720d395b783d7e99f009803
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/174190
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agovideo: tegra: host: Hack for nvhost code to work.
Alex Waterman [Mon, 17 Dec 2012 17:46:03 +0000]
video: tegra: host: Hack for nvhost code to work.

Should be properly fixed at some point in the future.

Change-Id: I1e9609a578e4b29aea1358e6301fbd95812f90b0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/172016
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoarm: kernel: GCOV needs android toolchain
Alex Waterman [Thu, 13 Dec 2012 21:53:03 +0000]
arm: kernel: GCOV needs android toolchain

Alert GCOV that the toolchain being used is the Android
toolchain not the generic gcc toolchain. If this config
option is not set, then the kernel will crash on boot.

Change-Id: I21567919c300d8ad5e969b99b1ce7cdae17e261b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/171165
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: fixup for merge
Alex Waterman [Thu, 13 Dec 2012 01:29:12 +0000]
ARM: tegra12: dvfs: fixup for merge

Parts of commit 0bedc869b11e58def2fd3ad10185f0e002c8e2d3
were missed. This simply adds those bits in since they now
became necessary after the merge.

Change-Id: I32e5389d26e7c37523acb978c738cdeb85576c53
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/171132
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: fix cclk_g mux value for net13 header change
Chao Xu [Mon, 3 Dec 2012 18:24:34 +0000]
ARM: tegra12: clock: fix cclk_g mux value for net13 header change

NET13 header swapped field definitions between PLLX_OUT0 and PLLX_OUT0_LT.
We had to change the field bits to continue accessing PLLX_OUT0. This needs
to be followed up because for t114 both CPU_CLK and PLLX_OUT0 use the _LT
signals.

Change-Id: Icc29355f648630e63977393372028ca59c296fea
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/168103
Reviewed-by: Automatic_Commit_Validation_User

6 years agodrivers: video: tegra: update T12x host1x headers to net13
Chao Xu [Wed, 14 Nov 2012 23:31:31 +0000]
drivers: video: tegra: update T12x host1x headers to net13

Change-Id: I891a418ef08634a91d7b64127112a4e035eb2678
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/163725
Reviewed-by: Automatic_Commit_Validation_User

6 years agovideo: tegra: host: enable gk20a vpr channel
Jin Qian [Mon, 10 Dec 2012 21:13:05 +0000]
video: tegra: host: enable gk20a vpr channel

Add vpr buffer for circular buffer and pagepool buffer but
still allocate from generic carveout until vpr heap is enabled
in tot kernel.

Bug 1186721
Change-Id: I75aa887c63be292b47781416345d19299e082d7f

Signed-off-by: Jin Qian <jqian@nvidia.com>
Change-Id: I1d922cf83fc9a5647cac169a341119214de57df7
Reviewed-on: http://git-master/r/169797
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agovideo: tegra: host: add gk20a pmu perfmon
Jin Qian [Thu, 15 Nov 2012 19:28:01 +0000]
video: tegra: host: add gk20a pmu perfmon

Bug 1168529

Change-Id: Icc047eaf6711f5b2c6975e04a3d65c5937720bc0
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/164025
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: update gpu dvfs
Jin Qian [Wed, 5 Dec 2012 19:46:43 +0000]
ARM: tegra12: dvfs: update gpu dvfs

Change-Id: I69317ed5cb86ddca8732a73dd5ecdd4e3a2f485a
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/168820
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clocks: Update PLLC2/C3 startup sequence
Bhanu Chetlapalli [Wed, 5 Dec 2012 20:06:01 +0000]
ARM: tegra12: clocks: Update PLLC2/C3 startup sequence

T124 changes the type of C2 & C3 PLLs which need IDDQ handling

Bug 1001865

Change-Id: I93e3b1a251df7a3d33330843a2d32a64024b5fc9
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/168816
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: HACK: Mark ISP/VI as keepalive
Bhanu Chetlapalli [Tue, 4 Dec 2012 20:03:51 +0000]
drivers: video: tegra: HACK: Mark ISP/VI as keepalive

Bug 1188795

Change-Id: Icffc17c3cad33223aef4d44ba8ca6464d5986223
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/168431
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: Update VI struct
Bhanu Chetlapalli [Fri, 30 Nov 2012 22:24:17 +0000]
drivers: video: tegra: Update VI struct

Add CSI clock to VI, since they are dependant on the same unit
Also a single clock controls both ISPs (and there is only 1 VI unit),
so removing the ".1" from the clock name

Bug 1175411

Change-Id: I9f8b9d859a2003c190d1ec7268786ad9da113059
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/167843
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clocks: Add aliases for camera devs
Bhanu Chetlapalli [Fri, 30 Nov 2012 22:20:44 +0000]
ARM: tegra12: clocks: Add aliases for camera devs

Device VI controls VI & CSI clocks
Both ISP devices control ISP clock

Bug 1175411

Change-Id: I455318ccd8986320b430cd2511735ad124171d9e
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/167842
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clocks: Update clk_out enable masks to NET12
Bhanu Chetlapalli [Tue, 13 Nov 2012 00:48:17 +0000]
ARM: tegra12: clocks: Update clk_out enable masks to NET12

Bug 1164664

Change-Id: Ic03e0b49b409334e319b3714ff124162e3e6eb95
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/163161
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clocks: Update clocks to NET12
Bhanu Chetlapalli [Tue, 20 Nov 2012 20:30:22 +0000]
ARM: tegra12: clocks: Update clocks to NET12

Fixed many incorrect register settings & updates clocks to agree
with clocking policy

Bug 1164664

Change-Id: Ia24b22b1618afe42a9720aa7d3e29222aa1ae593
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/165130
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: add dummy entry for vic03
Jin Qian [Wed, 5 Dec 2012 01:46:43 +0000]
ARM: tegra12: dvfs: add dummy entry for vic03

Change-Id: Ibe90127ee511ae0af723d0a74b6abdb090208625
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/168544
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: syncpt WAR for ISP
Amit Arora [Mon, 17 Sep 2012 17:24:49 +0000]
drivers: video: tegra: syncpt WAR for ISP

This change sets NVSYNCPT_ISP_0_0 to NVSYNCPT_MPE to unblock
camera team till more than 32 syncpoints are supported.

Change-Id: If25f60bb9728bb1cf092a64b383414c1d64ab268
Signed-off-by: Amit Arora <amita@nvidia.com>
Reviewed-on: http://git-master/r/133284
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Tested-by: Ken Adams <kadams@nvidia.com>

6 years agoARM: tegra: bonaire: update pinmux settings for NET2_CORE4
Jin Qian [Wed, 28 Nov 2012 22:23:05 +0000]
ARM: tegra: bonaire: update pinmux settings for NET2_CORE4

Change-Id: I5b1644aa70a35c21af749398d7192c2c92df6fd0
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/167078
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agotegra: host: gk20a: cache flushes
Bob Bond [Thu, 27 Sep 2012 21:55:42 +0000]
tegra: host: gk20a: cache flushes

Add cache flushes to the gk20a pte setup and simulation code

Change-Id: I3f1d0e4f20a3bcfe91ba47e99bb42750371f9592
Signed-off-by: Bob Bond <rbond@nvidia.com>
Reviewed-on: http://git-master/r/139418
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: bonaire: disable SMMU on FPGA
Jin Qian [Thu, 15 Nov 2012 21:44:59 +0000]
ARM: tegra: bonaire: disable SMMU on FPGA

Change-Id: I20708493a12508f2d7c0d59229f068fa45761432
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/164056
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>

6 years agodrivers: video: tegra: Tegra12 ispb device/resources
Ken Adams [Wed, 28 Nov 2012 18:13:59 +0000]
drivers: video: tegra: Tegra12 ispb device/resources

Adds register resources and device for ispb module.

Change-Id: Ie954a66fab10c1fcbf805e8ac4024c8619d9c395
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/145623

6 years agoARM: tegra: iomap: Tegra12 ISP
Ken Adams [Thu, 18 Oct 2012 22:14:24 +0000]
ARM: tegra: iomap: Tegra12 ISP

Updates ISP and ISPB addresses.

Change-Id: Ib10b45557b19bd6473e14af17457063ac1628225
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/145722

6 years agodrivers: video: tegra: update T12x host1x headers
Ken Adams [Wed, 28 Nov 2012 17:37:43 +0000]
drivers: video: tegra: update T12x host1x headers

Removed some (now) superflous hand-generated host1x definitions.

Change-Id: If3b27c1c5c113acbf0d8a813af7c62ab574960e5
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/167009

6 years agodrivers: video: tegra: fix host1x includes
Ken Adams [Wed, 28 Nov 2012 07:50:26 +0000]
drivers: video: tegra: fix host1x includes

host1x02 and host1x04 were being included improperly
in a few places.  fixed to remove the host1x02 versions.

Change-Id: Ia9dc34cb32a13aea0643f2af602d22ef66e9092a
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/166820

6 years agoARM: tegra: merge fixups
Ken Adams [Tue, 27 Nov 2012 19:14:41 +0000]
ARM: tegra: merge fixups

This change accounts for changes necessary due to
change http://git-master/r/161923 in the previous merge.

Change-Id: Ie0b1454d4ac051a473a793c9cab449da2fe866d9
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/166644
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>

6 years agodrivers: video: tegra: fix qt regression
Jin Qian [Wed, 14 Nov 2012 02:00:33 +0000]
drivers: video: tegra: fix qt regression

device num_clks is wrong from merge.

Change-Id: I1ce7a3330229e5e598ebe5f11b3e16bceb71fa40
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/163644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: fix t124 i2c6 and pll_p_out5 offsets
Jin Qian [Fri, 16 Nov 2012 23:13:32 +0000]
ARM: tegra12: clock: fix t124 i2c6 and pll_p_out5 offsets

Bug 1164664

Change-Id: I5a935b9c59371d395465a23814966e8ad6393d61
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/164445
Reviewed-by: Edgardo Handal <ehandal@nvidia.com>
Tested-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: gk20a: don't break signals
Robert Morell [Tue, 13 Nov 2012 02:02:54 +0000]
drivers: video: tegra: gk20a: don't break signals

wait_event_interruptible will return ERESTARTSYS if a signal is pending.
We can't deal with this properly in many cases because we've already
changed hardware state and can't back out.  For these cases, use a
lengthy timeout rather than *_interruptible.

Change-Id: I152d571c56e2424f3baf5f7eb30590ecd3685c9d
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/163182
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: Increase gr idle timeout
Adeel Raza [Tue, 6 Nov 2012 20:16:26 +0000]
drivers: video: tegra: Increase gr idle timeout

Increase GR_IDLE_TIMEOUT_DEFAULT to 20000 usecs for
CONFIG_TEGRA_SIMULATION_PLATFORM.

Change-Id: I9f345b6ddb47bc232550c40e82c655365a53d0d9
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/161759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: bonaire: Lower UART clock for only QT
Adeel Raza [Tue, 13 Nov 2012 00:44:20 +0000]
ARM: tegra: bonaire: Lower UART clock for only QT

Previously UART clock was being lowered for ASIM + QT and pure QT. UART
clock only needs to be lowered for pure QT.

Bug 1166332

Change-Id: Ifcc8b7291fa45313b01ac67d96326e7de928c843
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/163153
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: update tegra12x clock table
Jin Qian [Thu, 8 Nov 2012 20:34:30 +0000]
ARM: tegra12: clock: update tegra12x clock table

Bug 1164664

Change-Id: Iea5e10edeb99180e61f98b2887e6691d8e665cba
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/162468
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: add gpu ioctl based zbc ctrls
Jin Qian [Wed, 7 Nov 2012 23:27:23 +0000]
drivers: video: tegra: add gpu ioctl based zbc ctrls

Change-Id: Ibebaeb302591333e31ec9c0623d7f720e472b929
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/162153
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: tegra: add a new field for gk20a pmu cmdline arg
Jin Qian [Wed, 7 Nov 2012 02:32:02 +0000]
drivers: video: tegra: add a new field for gk20a pmu cmdline arg

Match kernel with newer pmu ucode built from chips_a 14315261.
This change is compatible with current pmu ucode.

Change-Id: I7a923b641cb5e60292eb7acfd847736b943fe057
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/161843
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agodrivers: video: host: remove channel zcull ioctls
Jin Qian [Tue, 6 Nov 2012 20:39:40 +0000]
drivers: video: host: remove channel zcull ioctls

NVHOST_IOCTL_CHANNEL_ZCULL_GET_SIZE
NVHOST_IOCTL_CHANNEL_ZCULL_GET_INFO

They're replaced by gpu ctrl ioctls.

Change-Id: Idaa3b972b77096e3ac90b22e94b18e53429bf34d
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/161780
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: HACK: set mem efficiency to 100
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:28 +0000]
ARM: tegra12: clock: HACK: set mem efficiency to 100

Change-Id: I734b831bb46388e2c5b7e0d5245ad75b0c8e9bf1
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/160946
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Use cvb model for pll clock source
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:27 +0000]
ARM: tegra12: dvfs: Use cvb model for pll clock source

da959dc5b8c2877468b27130f5d956c7d8cdb868: Use cvb model for pll clock source

Change-Id: Iefd4434bee225f578c55b8d76a312f1be5235ca7
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161403
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Don't apply dfll min voltage in pll mode
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:26 +0000]
ARM: tegra12: dvfs: Don't apply dfll min voltage in pll mode

28fa89d56de8b0691c684727f58e79e0d42e42b4: Don't apply dfll min voltage in pll mode

Change-Id: I54e0dc1c958f5214ef492c6f9dbfc3a2fb393cee
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161402
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Move min millivolts to dfll_data
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:25 +0000]
ARM: tegra12: dvfs: Move min millivolts to dfll_data

0bedc869b11e58def2fd3ad10185f0e002c8e2d3: Move min millivolts to dfll_data

Change-Id: Iaf213dfa3ec1642e0a45396de5f475a544e8f964
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161401
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Round up CPU dvfs frequency list
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:25 +0000]
ARM: tegra12: dvfs: Round up CPU dvfs frequency list

a2e058e8abfa328dcd6f82ac8e662090aaaf95a6 Round up CPU dvfs frequency list

Change-Id: Ida75ac26a35a518f84c1577aea29bb5d3be7f284
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161400
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Update CPU rate and voltage range
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:24 +0000]
ARM: tegra12: dvfs: Update CPU rate and voltage range

1ee632fa39ef0fd73e567e4dfe9b557bc1d9f66f: Update CPU rate and voltage range

Change-Id: I342dbe73e1d1fc98bb42f6e1a5ef5487e2cd0e82
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161399
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Increased CPU min voltage limit
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:23 +0000]
ARM: tegra12: dvfs: Increased CPU min voltage limit

e5f3316a7b5a557feaf6eb93c9ee0e36d2c03471: Increased CPU min voltage limit

Change-Id: If876fc617457a6d4f0fac1d2eac639e7a593ee4c
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Round down CPU rate when run on pll
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:23 +0000]
ARM: tegra12: dvfs: Round down CPU rate when run on pll

4f887f9941d79104eba5747c261665ed06b77556 Round down CPU rate when run on pll

Change-Id: I9a5718eedc0cb31fc64eefe470df14430dbd020e
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161397
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Integrate dfll mode data with dvfs table
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:22 +0000]
ARM: tegra12: dvfs: Integrate dfll mode data with dvfs table

af81273fffc4ac402e5e8a4dc424465c039ee84b: Integrate dfll mode data with dvfs table

Change-Id: I6d88f3a51cee05eb7f2497038b9498015341aff0
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161396
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: dvfs: Update XUSB clocks dvfs table
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:21 +0000]
ARM: tegra12: dvfs: Update XUSB clocks dvfs table

cf3b57e2d5b79f2dcd65635cadd873e3413d5226 Update XUSB clocks dvfs table

Change-Id: I5127bd7cc92570d59814e53485af0f0689b28781
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/160945
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: decrease sclk min limit
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:21 +0000]
ARM: tegra12: clock: decrease sclk min limit

9f82f47f9791bc63e6dd195cb0cf5fc9c9841441: decrease sclk min limit

Change-Id: Ib7cafeb329d8d6521f12bd961c608ed8eac47d42
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Switch from DFLL to PLL at low rate
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:20 +0000]
ARM: tegra12: clock: Switch from DFLL to PLL at low rate

72181d511d15193a95e860ac55a0a1d7d12d06ba: Switch from DFLL to PLL at low rate

Change-Id: Ia0d086ee146755cc84d376b3b1b51bd6b94f010c
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161393
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Fix G-to-G CPU switch
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:19 +0000]
ARM: tegra12: clock: Fix G-to-G CPU switch

5fbe3365d66c0e6ebadc92f47fb05ce61d4c6455: Fix G-to-G CPU switch

Change-Id: I7f19b60ace99a6e647b965aa35306ed0c3a320d5
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161392
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Update DFLL switch error handling
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:19 +0000]
ARM: tegra12: clock: Update DFLL switch error handling

911ab103724f15fe4e1dd2167a26b3a9442c3d37: Update DFLL switch error handling

Change-Id: Ieeaab2ab0a7350ddcf98f04b543b79f5ab1c7361
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Remove pll table restriction
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:18 +0000]
ARM: tegra12: clock: Remove pll table restriction

905bfb114b30d7279178d9e1a51dd870ab6a2da7: Remove pll table restriction

Change-Id: Iac15abf5ca552523c3727bec4dada80615c8f4eb
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Dynamically allocate cl dvfs object
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:17 +0000]
ARM: tegra12: clock: Dynamically allocate cl dvfs object

1b483f1b12722347915b4c50f03e12788b41230d Dynamically allocate cl dvfs object

Change-Id: Iede93371aa77233e8135fbf0f5ae4fcc584b0aa7
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161389
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Acquire CL-DVFS clocks in probe
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:17 +0000]
ARM: tegra12: clock: Acquire CL-DVFS clocks in probe

ea8a25e4b67ea1b3ad94eaaf419370995e36563c: Acquire CL-DVFS clocks in probe

Change-Id: I14c2ce2152db9b2adac3250d216b6dccd6b1d036
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161388
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Enable PLLE VREG
Bhanu Chetlapalli [Mon, 5 Nov 2012 18:56:16 +0000]
ARM: tegra12: clock: Enable PLLE VREG

9d9fcac3f42fcb904e009d79c6fdacddba8ff1b2 Enable PLLE VREG

Change-Id: I8b2d287d846c8d4e2ab547cfc340bf09d94705b5
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/161386
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>