5 years agoARM: Tegra: fix arch timer registration sequence
Varun Wadekar [Tue, 3 Jul 2012 12:00:10 +0000]
ARM: Tegra: fix arch timer registration sequence

Change-Id: I94d4ab5c8d53e454bbd09b6ef2586b1baf69d456
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/113243
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rd019e521e2e29eb875a4a1d0aff31b5d3eba2666

5 years agoARM: Tegra11: curacao: fix tegra_grhost_device loading
Varun Wadekar [Tue, 3 Jul 2012 10:23:10 +0000]
ARM: Tegra11: curacao: fix tegra_grhost_device loading

Change-Id: Ifcba004551418d85ec72bdfe87872896a7b019f1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/113240
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R614432114267153b040af741128f2e32800e77f1

5 years agoARM: Tegra: add tegra11x-pinmux to supported pinmux devices
Varun Wadekar [Tue, 3 Jul 2012 10:23:47 +0000]
ARM: Tegra: add tegra11x-pinmux to supported pinmux devices

Change-Id: I6f924492be2e8e4337ecc2d7fe52758704de72ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/113241
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R7926f6086a71e8e3e6e6c4e27a8c351c55e8129b

5 years agoARM: use ARM_ARCH_TIMER instead of LOCAL_TIMER
Varun Wadekar [Tue, 3 Jul 2012 10:25:01 +0000]
ARM: use ARM_ARCH_TIMER instead of LOCAL_TIMER

Change-Id: Id149dcec5f531e249960603f27693775a56b3f4e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/113242
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rebc0db942508d5a7b008005b6102c190575fe27c

5 years agoPartial Revert "ARM: tegra11: fix compilation issues"
Dan Willemsen [Mon, 5 Nov 2012 19:49:41 +0000]
Partial Revert "ARM: tegra11: fix compilation issues"

This reverts commit 1b6c57a85f3db2b9382836a64f43729c53f3c17a.

Rebase-Id: R1f9dd2df06a1f47e9be6142e823f0a278a545edf

5 years agoMerge remote branch 'remotes/experimental/dev/android-t114-3.4-rebased' into k3.4
Bo Yan [Mon, 2 Jul 2012 21:18:30 +0000]
Merge remote branch 'remotes/experimental/dev/android-t114-3.4-rebased' into k3.4

Conflicts:
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/timer.c

Change-Id: Ie967f1d45f50601f3c1fad958405d5343e722687

Rebase-Id: R8bded2bd20be11b5c206dd740395c08aed5cf1f8

5 years agoPartial ARM: tegra: clocks: Consolidate input frequency measurements
Dan Willemsen [Fri, 2 Nov 2012 03:25:54 +0000]
Partial ARM: tegra: clocks: Consolidate input frequency measurements

Consolidate the functions used to measure the input frequency
into a single implementation and perform the measurement only
once.

Change-Id: I3d13e608a7256d154373542ca001cbda9c03c21b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/83613
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Conflicts:

arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/tegra2_clocks.c
arch/arm/mach-tegra/tegra3_clocks.c
arch/arm/mach-tegra/timer-t2.c
arch/arm/mach-tegra/timer-t3.c

Conflicts:

arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/timer.c

Rebase-Id: R024e19b70f89402e9ce1b059fc48f862403086d2

5 years agoPartial Revert "ARM: tegra: curacao: enable DC to run on simulator"
Dan Willemsen [Fri, 2 Nov 2012 03:12:09 +0000]
Partial Revert "ARM: tegra: curacao: enable DC to run on simulator"

This reverts commit a9f941dbf764f0a109a92bbda25187a125cce277.

Conflicts:

arch/arm/mach-tegra/board-curacao-panel.c

Rebase-Id: R9eb5488be3e6edab920317932aa0edbe2d5163d5

5 years agoPartial Revert "ARM: tegra: curacao: Set usb device mode by default"
Dan Willemsen [Fri, 2 Nov 2012 02:04:01 +0000]
Partial Revert "ARM: tegra: curacao: Set usb device mode by default"

This reverts commit a859e11eba8b6d438f865aee1cc518d0f6d9ee01.

Rebase-Id: R3f68db8ebd1593b3cefb1661c56676be2d511f55

5 years agoPartial Revert "arm: tegra: curacao: Use DCb as default display"
Dan Willemsen [Fri, 2 Nov 2012 02:00:26 +0000]
Partial Revert "arm: tegra: curacao: Use DCb as default display"

This reverts commit eaf3a2c4cde056c9d613b69df8a990ac59ee457d.

Rebase-Id: R61756f64e3066a4e3cb505b3cd970a23c0246004

5 years agoRevert "ARM: tegra: iomap: fix bsea aperture size"
Dan Willemsen [Fri, 2 Nov 2012 02:10:40 +0000]
Revert "ARM: tegra: iomap: fix bsea aperture size"

This reverts commit 8ec2f4874675743fe5cf78fca11b084ed7bfd9b2.

Rebase-Id: R38b0c8b798c9b5bc9306e8f2499a1022507974a3

5 years agoPartial Revert "ARM: tegra: curacao: Enable camera sensor"
Dan Willemsen [Fri, 2 Nov 2012 02:04:18 +0000]
Partial Revert "ARM: tegra: curacao: Enable camera sensor"

This reverts commit 4836ad127d8d0a438989399fa02cf455eb553b05.

Rebase-Id: Ra5f2b741f42bdf91ba8c6882cf77ebe590126576

5 years agoARM: Tegra: 11x: Add ARM_CPU_SUSPEND
Bo Yan [Wed, 27 Jun 2012 01:35:42 +0000]
ARM: Tegra: 11x: Add ARM_CPU_SUSPEND

Rebase-Id: R73dedada1837e2c86505c2ae5f9bbb3b2cf953fe

5 years agoMerge remote branch 'remotes/vwa/dev/android-t114-3.4-rebased' into new
Bo Yan [Wed, 27 Jun 2012 01:35:42 +0000]
Merge remote branch 'remotes/vwa/dev/android-t114-3.4-rebased' into new

This actually merges TOT of dev/android-t114-3.4-rebased into
origin/android-t114-3.4 on 6/26/2012

Conflicts:
arch/arm/configs/tegra_curacao_android_defconfig
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-curacao-panel.c
arch/arm/mach-tegra/board-curacao-pinmux.c
arch/arm/mach-tegra/board-curacao-power.c
arch/arm/mach-tegra/board-curacao.c
arch/arm/mach-tegra/board-curacao.h
arch/arm/mach-tegra/include/mach/iomap.h
arch/arm/mach-tegra/include/mach/irqs.h
arch/arm/mach-tegra/tegra11_clocks.c

Change-Id: I37608c30489613150a5e9e270af71c16cc667005

Rebase-Id: Rc98729d8cef139f43adbf91180080fa24d5b9dd9

5 years agomisc: apanic: erase kpanic when no data
Tom Zhu [Thu, 24 Sep 2009 15:58:50 +0000]
misc: apanic: erase kpanic when no data

erase kpanic partition when there is no data(console and thread)

Signed-off-by: Tom Zhu <a2289c@android-hal-04.(none)>
Signed-off-by: San Mehat <san@google.com>
Change-Id: I76a17b489720910d7845ec30799601c347f88468
Reviewed-on: http://git-master/r/111039
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R1fa30289f3314e196c8e09db517b5476fe52d478

5 years agomisc: apanic: bad block handling
Tom Zhu [Mon, 21 Sep 2009 21:36:05 +0000]
misc: apanic: bad block handling

Add bad block handling in apanic

Signed-off-by: Tom Zhu <ling.zhu@motorola.com>
Signed-off-by: San Mehat <san@google.com>

misc: apanic: Improved bad-block / watchdog handling

1. handle cases that there is no more good blocks
2. touch softlockup watchdog at the start of apanic
3. change unsigned char get_bb() to unsigned int get_bb()
4. return idx instead of rc2, to keep the previous written pages.

Signed-off-by: Tom Zhu <ling.zhu@motorola.com>
Signed-off-by: San Mehat <san@google.com>
Change-Id: Id42eff1d6d7bb26b06327ff15e9ee5b37df99e67
Reviewed-on: http://git-master/r/111038
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R2231aafc2eb653830e09fe68135ad7f659ed3222

5 years agoramconsole/apanic: Ensure ramconsole does not get cluttered by apanic threads
San Mehat [Thu, 17 Sep 2009 21:27:41 +0000]
ramconsole/apanic: Ensure ramconsole does not get cluttered by apanic threads

Change-Id: Ib31c1653e28af3e818f2d4bef86c5149a78ebda4
Signed-off-by: San Mehat <san@google.com>
Reviewed-on: http://git-master/r/111037
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Reb7800e8a64925ed893ec74579f8eda19dcc5b60

5 years agodrivers: apanic: Android kernel panic handler.
San Mehat [Tue, 1 Sep 2009 20:43:01 +0000]
drivers: apanic: Android kernel panic handler.

This driver triggers when the kernel panics and attempts to
write critical debug data to the flash.

Signed-off-by: San Mehat <san@google.com>

drivers: apanic: checkpatch fixes

Signed-off-by: San Mehat <san@google.com>

apanic: Fix a few cases of calling non-atomic things from atomic

We need to pay special care to not enrage cond_resched(), and the
base nand bb stuff calls schedule() so thats out.

Change-Id: I2f57b5666b3e575bf88bec4b8bbd1da1b4701a13
Signed-off-by: San Mehat <san@google.com>
Reviewed-on: http://git-master/r/111036
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R6ebadcd77135f85a35065fcce9a81dfdf6772997

5 years agokernel_debugger_core: add interrupt-context debugger core
Brian Swetland [Wed, 9 Apr 2008 05:34:46 +0000]
kernel_debugger_core: add interrupt-context debugger core

This provides kernel_debugger() which can be called from an interrupt
context low level debugger wedge to execute commands that inspect
kernel state.  It doesn't do much on its own.

Signed-off-by: Brian Swetland <swetland@google.com>

kernel_debugger_core: Add sysrq command.

sysrq <c> will run the sysrq command <c> and dump what
was added to the kernel log while the command ran.

Signed-off-by: Brian Swetland <swetland@google.com>
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Change-Id: I7d260f89595f18638bcedc90d27471b840957631
Reviewed-on: http://git-master/r/111034
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R078775f41883d31bd9d397f7256481eef08421e1

5 years agoUSB: composite: Allow configurations to handle unhandled setup requests
Joe Swantek [Tue, 15 Dec 2009 12:17:40 +0000]
USB: composite: Allow configurations to handle unhandled setup requests

Signed-off-by: Mike Lockwood <lockwood@android.com>
Change-Id: I5b5ffd02578ccd92e6909735f259e39f5143339b
Reviewed-on: http://git-master/r/110674
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Ra322344422946076110063e93087067388cbcafe

5 years agoUSB: composite: Add flag to usb_function to hide its interface during enumeration
Mike Lockwood [Fri, 11 Dec 2009 16:24:07 +0000]
USB: composite: Add flag to usb_function to hide its interface during enumeration

Change-Id: Ie999b5190e3e2b6fd23015b8e796cdd178829929

Signed-off-by: Mike Lockwood <lockwood@android.com>
Change-Id: Ie84b8a1bf8e81458716b9ae21002d1e6cc6ffffa
Reviewed-on: http://git-master/r/110670
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Re3738155c95b8d7fa5d1790bff4ef8ff7912596d

5 years agoUSB: composite: Fix USB WHQL Certification Issues
Jared Suttles [Fri, 7 Aug 2009 23:57:49 +0000]
USB: composite: Fix USB WHQL Certification Issues

Submitted on behalf of RaviKumar Vembu <ravi.v@motorola.com>
Signed-off-by: Jared Suttles <jared.suttles@motorola.com>
Signed-off-by: Mike Lockwood <lockwood@android.com>
Change-Id: I0f286a428e8a1df5f173873233fadea987775f6b
Reviewed-on: http://git-master/r/110669
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rd020ea5303a19a19d143f681d95a1618a0a7a566

5 years agodrivers: usb: gadget: handle NULL descriptors in composite config_buf
Jared Suttles [Thu, 30 Jul 2009 21:13:27 +0000]
drivers: usb: gadget: handle NULL descriptors in composite config_buf

This fixes a problem in enumeration after a gadget function is removed.

Submitted on behalf of RaviKumar Vembu <ravi.v@motorola.com>

Signed-off-by: Jared Suttles <jared.suttles@motorola.com>
Signed-off-by: Mike Lockwood <lockwood@android.com>
Change-Id: I96d0a8a8881d948c6623f17fb6efad511906d272
Reviewed-on: http://git-master/r/110667
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R3eee6bd290bf9c0bd093e3f9a5e94fe28d0b7dee

5 years agoDROP: Revert "USB: EHCI: fix HUB TT scheduling issue with iso transfer"
Greg Kroah-Hartman [Mon, 28 Nov 2011 22:40:10 +0000]
DROP: Revert "USB: EHCI: fix HUB TT scheduling issue with iso transfer"

DROP: this was a temporary regression fixed in later kernels

This reverts commit f0cc710a6dec5b808a6f13f1f8853c094fce5f12.

Change-Id: I1547640e9a205a8a43ecde531a5cda7a5de0321a
Cc: Matthieu Castet <matthieu.castet@parrot.com>
Cc: Thomas Poussevin <thomas.poussevin@parrot.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Reviewed-on: http://git-master/r/110206
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R52d478b91169aa2028977f55272345cb92351c66

5 years agoARM: Tegra11: add pinmux configuration
Varun Wadekar [Mon, 2 Jul 2012 15:00:18 +0000]
ARM: Tegra11: add pinmux configuration

Change-Id: I7509817f53c36adc43ccb0c851a1bd1fa7769748
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Raf24a9ae071ae91017090fa4f2034df785a5a9b3

5 years agoARM: tegra11: fix arch_timer_register
Varun Wadekar [Mon, 2 Jul 2012 14:50:35 +0000]
ARM: tegra11: fix arch_timer_register

arch_timer_register now takes struct arch_timer instead of individual resources

Change-Id: I5177116822327d6c59f5a2075016ae2d4c9f9379
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R3533b6c4b54c94b7f06beeb64c962af5e934cc57

5 years agoARM: tegra11: fix compilation issues
Varun Wadekar [Mon, 2 Jul 2012 14:48:43 +0000]
ARM: tegra11: fix compilation issues

- use DIV_U71_UART instead of DIV_U151_UART
- conditionalise tegra_dtv_device for T30 only

Change-Id: Iac8009727144dce0ed9676e09a3848093446e5a1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R24b40ce3b86178e60bd156a691b578ad1b36b545

5 years agoARM: tegra: add common tegra_clk_measure_input_freq instead of the per chip version
Varun Wadekar [Mon, 2 Jul 2012 14:46:34 +0000]
ARM: tegra: add common tegra_clk_measure_input_freq instead of the per chip version

Change-Id: I56536a96e0427bdfe46bd8ea253a45be1e824cb4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rc21a75b6c091b8d43163d85b867eeb9427075bb1

5 years agoARM: Tegra11: curacao: enable pinmux and gpio devices during board init
Varun Wadekar [Mon, 2 Jul 2012 13:12:17 +0000]
ARM: Tegra11: curacao: enable pinmux and gpio devices during board init

Change-Id: I6833d0cd7deb8fae784dc2a5695358f2e1ba1652
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R58ab05b664d126459bf21da903bbaa7014133ab3

5 years agoARM: Tegra11x: add clocks for T114
Varun Wadekar [Mon, 2 Jul 2012 13:04:52 +0000]
ARM: Tegra11x: add clocks for T114

Change-Id: Ibcda3749f86e5a193862d3ba8ef392e1010442a7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R0d3e56b953567ccd43ee546bd8cd002d7a539920

5 years agoARM: tegra11: Support Curacao build
Bo Yan [Sat, 30 Jun 2012 00:52:15 +0000]
ARM: tegra11: Support Curacao build

With these changes, curacao build can be made successfully. However,
since timer change is incomplete, it most likely won't work on FPGA.
pinmux and chip init also need further fixes.

Change-Id: Idf934816f7c526eb2f2c7814ffd122375b8630dd
Signed-off-by: Bo Yan <byan@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rb7d4782d847ddd7a4acf3ad95f8fd96fc0ab73bc

5 years agoehci: tegra: Delete unused variable
Bo Yan [Sat, 30 Jun 2012 00:42:31 +0000]
ehci: tegra: Delete unused variable

This fixes compilation warning

Change-Id: I079a7a464f2b043a2563d2e438987c8a3d7c28dd
Signed-off-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R52778f039935f67e81bda52058591124fd7e5709

5 years agoARM: tegra11: clock: Add DSI implicit dependency on PLLP
Alex Frid [Tue, 12 Jun 2012 20:38:43 +0000]
ARM: tegra11: clock: Add DSI implicit dependency on PLLP

Added dsi fixed clock entry derived from PLLP_OUT3. This would allow
DC driver to properly ref-count implicit dependency of DSI operations
on PLLP_OUT3 clock.

Change-Id: I3a90ca4b59d95c65d859f61b8667f7e741601d2a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/108418
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Recce63ad98e85e2edd5e597da7c573ae027555a2

5 years agoARM: tegra11: clock: Clean clock definitions
Alex Frid [Tue, 12 Jun 2012 19:46:23 +0000]
ARM: tegra11: clock: Clean clock definitions

- removed obsolete xio clock
- removed ENABLE_ON_INIT flag from PLLP secondary dividers definition
(they can be disabled during initialization)
- corrected device id for nor driver

Change-Id: I07f32b27126d15d07568f2327fdb2214a7e40a96
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/108417
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6a8ec8b4db6fddcfed895f7a3f0feb96f50cb729

5 years agoARM: tegra: clock: Enable 2D/3D idle divisors
Alex Frid [Tue, 12 Jun 2012 18:14:19 +0000]
ARM: tegra: clock: Enable 2D/3D idle divisors

Enabled 3D/2D h/w rate scaling when the respective module is idle.

Change-Id: I5bfeca791951ea5c417cba62b97188f96babbf68
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/108416
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R121021daeba99a1a97b2ce09820a86f03f15b098

5 years agoARM: tegra11: clock: Update i2c clock entries
Alex Frid [Tue, 12 Jun 2012 05:22:18 +0000]
ARM: tegra11: clock: Update i2c clock entries

- Limit possible i2c clock parents to oscillator clk_m and low frequency
pll_p to avoid recursive voltage dependency (when i2c interface is used
as PMU transport)

- Add i2c fast clock entry which is derived from pllp_out3. This is
non-muxed hard wired input clock for i2c and does not have any control
bit in CAR registers.

Change-Id: I39bc2710944cf712e264c312dd2383c8f65a8afc
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/108414
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R950f40a14a316b976041f3521a6df64af9207508

5 years agoARM: tegra11: curacao: Update cl-dvfs platform data
Alex Frid [Tue, 12 Jun 2012 03:31:49 +0000]
ARM: tegra11: curacao: Update cl-dvfs platform data

Updated cl-dvfs platform data to match curacao PMU; made sure
regulators are initialized before cl-dvfs.

Change-Id: I47d2bdac8aa2d263ccc89623aaa408c8c5565493
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/108129
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Re100f728fb12f7c4a95e42adf062deeeefd05bec

5 years agoARM: tegra11: dvfs: Separate dfll and legacy dvfs min voltages
Alex Frid [Sun, 10 Jun 2012 04:16:05 +0000]
ARM: tegra11: dvfs: Separate dfll and legacy dvfs min voltages

Added a separate entry for dfll minimum voltage to characterization
data, and applied it as dfll voltage low limit instead of legacy
dvfs minimum voltage.

Change-Id: Ibfc1576a098f72db0df27b92c657f7650df085c4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107807
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Raab999f53f8cd4bb52c2c739c8aa1949035a6cb9

5 years agoARM: tegra11: dvfs: Separate dfll droop and out min rates
Alex Frid [Sun, 10 Jun 2012 00:54:39 +0000]
ARM: tegra11: dvfs: Separate dfll droop and out min rates

Added a separate entry for dfll minimum rate to dfll characterization
data, and applied it as dfll rate low boundary instead of dfll droop
minimum rate.

Change-Id: If6a4f77861e4912ff5cda29c77fdef1f1a334043
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107806
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R76aa53b0e2958aa24560ec9ea78063db7dd019c7

5 years agoARM: tegra11: clock: Add Security Engine clock entry
Mallikarjun Kasoju [Mon, 11 Jun 2012 15:29:52 +0000]
ARM: tegra11: clock: Add Security Engine clock entry

Add SE clock entry in tegra11

Bug 837124

Change-Id: Ibb4a338e2e0abe8106a2c9242a23daf0139256e2
Reviewed-on: http://git-master/r/107951
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rddacf7422fa37d912e558bdfe35ad8f763aca6dd

5 years agoARM: tegra11: clock: Update peripheral clocks operations
Alex Frid [Thu, 7 Jun 2012 00:16:20 +0000]
ARM: tegra11: clock: Update peripheral clocks operations

- Added locking for peripheral clocks secondary reference counting
(although enable/disable register access is atomic, but some clocks
may share an enable bit).

- Skipped clock/reset control operations for clocks with PERIPH_NO_ENB
flag.

Change-Id: I98490fedc4d25faebc32dc79179c133f9e88476d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106937
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rae9ae7b94782a64e0ad58050840f59b6359669dc

5 years agoARM: tegra11: clock: Add pll dividers access lock
Alex Frid [Wed, 6 Jun 2012 06:14:10 +0000]
ARM: tegra11: clock: Add pll dividers access lock

Added locking for non-atomic access to shared secondary PLL dividers
registers.

Change-Id: If07aa244f8ae1843232aa82541b57f5a2752fd6e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106936
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R37846b65df74a52fcde0a300a7ed04ce9fe51ab1

5 years agoARM: tegra: curacao: Remove ganged mode config macro
Animesh Kishore [Wed, 6 Jun 2012 10:38:02 +0000]
ARM: tegra: curacao: Remove ganged mode config macro

Use in file macro to select ganged mode.

Bug 944115

Change-Id: Id312babe70d84b84b0e3956a64460dffbb01e64b
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/106744
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

Rebase-Id: R4c27eb92da3fe3317a8848b2e47a3ccd516fc6fc

5 years agoARM: tegra11: clock: Remove duplicated uart clock entries
Alex Frid [Wed, 6 Jun 2012 03:39:48 +0000]
ARM: tegra11: clock: Remove duplicated uart clock entries

Change-Id: If9c32cb3c4bcf78bcecf23f2f1334f8e57fa954f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106935
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R4f5eb4f0b9027fdc2c442beb3646b580c2e43098

5 years agoARM: tegra11: clock: Update common clock table
Alex Frid [Wed, 6 Jun 2012 03:19:39 +0000]
ARM: tegra11: clock: Update common clock table

- removed duplicated sbc5 and sbc6 entries (merge artifact)
- consolidated non-tegra3 settings
- don't check for tegra2 in emulation (not supported)

Change-Id: Ic23c6d07dd46a8a14d3fcfef6d10d60a15237071
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106933
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R6bc23acf96e137690d07c396212d35093c2a0090

5 years agoARM: tegra11: Select dual cbus for Tegra11 SoC family
Alex Frid [Wed, 6 Jun 2012 01:28:17 +0000]
ARM: tegra11: Select dual cbus for Tegra11 SoC family

Change-Id: I3767a76da3ed9e8a94fabdb192cc1257cd5e244d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106662
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R0b3d416690572f51cd80a329debd18276cbc1ea0

5 years agotegra: usb: 2LS WAR removal
Krishna Yarlagadda [Wed, 6 Jun 2012 12:27:43 +0000]
tegra: usb: 2LS WAR removal

remove 2LS WAR for T114 chip as this is fixed in hardware

Bug 969261

Change-Id: I6532cd23bd110ab3bd3a8ef2ce18d37bf4a1b0ff
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/106757
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rd42d448e83de4470b6514d6a3b2cf9fd830e9726

5 years agoARM: tegra11: Update L2 data RAM latency only once
Bo Yan [Tue, 5 Jun 2012 20:55:23 +0000]
ARM: tegra11: Update L2 data RAM latency only once

The L2 data RAM latency only needs to be set once every time when
cluster 0 is switched into. Other CPUs will have the same setting
as CPU0, so no need to set it once it's set already.

Change-Id: I4d7f99e162587310cea9d961871686594b999677
Reviewed-on: http://git-master/r/106560
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R366eada68b595a3fb19118c73f7171b48104eff4

5 years agoarm: tegra: usb: Disable the usb WAR for T114
Suresh Mangipudi [Thu, 7 Jun 2012 03:55:13 +0000]
arm: tegra: usb: Disable the usb WAR for T114

Disable the USB WAR's for T114, as the WAR's are not needed for T114.

- USB cntrlr asserts PORTSC.SUSP bit before the bus goes to suspend
- USB write-to-sysmem DMA interrupt vs.CPU read-from-sysmem coherence
- remove WAR for 2LS bit WAR

Bug 969265
Bug 969335
Bug 969261

Change-Id: I57b26de3ac1fe88c615d6353ab6448b5f3a4852d
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106992
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R257ea36916f24d26e4c621f79aee55c0bfe3a0c9

5 years agoarm: tegra: curacao: enable unaligned buffer support
Suresh Mangipudi [Wed, 6 Jun 2012 06:40:01 +0000]
arm: tegra: curacao: enable unaligned buffer support

Enable the unaligned buffer support for T114 based platforms

Bug 969252

Change-Id: Ifd945c5a3ccd65ebd5ee0b84bc5b70720de00cb7
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106689
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rf5f54a109a19b930656f8e1c77b19f3ac087edc0

5 years agoechi: tegra: Add support for unaligned buffers
Suresh Mangipudi [Wed, 6 Jun 2012 06:38:41 +0000]
echi: tegra: Add support for unaligned buffers

T114 supports unaligned buffers, so add support for the same.

Bug 969252

Change-Id: I6bd67aadec8eeb4ee3cba138fa94df4a75e736e0
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106688
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc361914cee9b7cc6d222310153855d73650290ba

5 years agousb: tegra: unaligned buffer support
Suresh Mangipudi [Wed, 6 Jun 2012 06:33:43 +0000]
usb: tegra: unaligned buffer support

Add unaligned buffer support for t114.

Bug 969252

Change-Id: I827518806f0747e891427f350467b3784cffb67c
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106687
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R3238dd4ce4c85d0b6fe67325dd43235d09f511bd

5 years agoARM: tegra: t114: Pinmux LP0 entry/exit sequence
Ashwini Ghuge [Tue, 5 Jun 2012 08:50:11 +0000]
ARM: tegra: t114: Pinmux LP0 entry/exit sequence

Updating pinmux LP0 entry/exit sequence
to prevent pad glitches

Bug 988086

Change-Id: I68040ee8c744ae878f9aa96c2a2745fcdb94b650
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/105172
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R2413e61ac8acb71b4f352a89d527ae687a43833c

5 years agoARM: tegra: clock: update device id of SE
Mallikarjun Kasoju [Thu, 16 Feb 2012 06:51:51 +0000]
ARM: tegra: clock: update device id of SE

Update device id of SE

Bug 837124

Change-Id: If4d7badca7ed7aeafb76662082b8c4ecdc3e9bbf
Reviewed-on: http://git-master/r/84244
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R1ff70f4aa74ac37d088a908ef3b820ab8a7a2517

5 years agoARM: tegra11: Add SE driver data
Mallikarjun Kasoju [Thu, 16 Feb 2012 06:45:53 +0000]
ARM: tegra11: Add SE driver data

Bug 837124

Change-Id: I280573bd215a737845b9860c05dfebe5a7ad7d79
Reviewed-on: http://git-master/r/84243
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R816212d84a94ef37c5192fd1083d18131d86ec02

5 years agoARM: tegra: curacao: Change SE device data name
Mallikarjun Kasoju [Thu, 16 Feb 2012 06:28:51 +0000]
ARM: tegra: curacao: Change SE device data name

Change SE device data name

Bug 837124

Change-Id: Ie60ef4ea215d6f8e6bb4bd5e27de48fa9696f774
Reviewed-on: http://git-master/r/84241
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R5cdbe7a9cc4560accdeedc9a4e2a164b6c8af7f0

5 years agoARM: tegra11: clock: Add clock/reset control register X
Alex Frid [Tue, 5 Jun 2012 21:11:56 +0000]
ARM: tegra11: clock: Add clock/reset control register X

Change-Id: I8c33d456bb3191a590f553d11e59c46bbc9c5347
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb130bc12f3354dd44365adb99fbd8015f17b147d

5 years agoarm: tegra: usb_phy: remove fence read for T114
Suresh Mangipudi [Tue, 5 Jun 2012 10:38:37 +0000]
arm: tegra: usb_phy: remove fence read for T114

Fence read is not needed for T114. Hence removing the fence read for
every interrupt.

Bug 969335

Change-Id: Id36641487b1bbcf2e4da97812bf683de8553f71b
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106441
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb664afe9e7240c9c7a0742f45662d67f2c024df8

5 years agotegra: usb: remove WAR for PORTSC.SUSP before bus goes to suspend
Suresh Mangipudi [Tue, 5 Jun 2012 10:10:22 +0000]
tegra: usb: remove WAR for PORTSC.SUSP before bus goes to suspend

USB controller asserts PORTSC.SUSP bit before the bus goes to suspend,
the s/w WAR is no longer need for t114.

Bug 969265

Change-Id: I7682cd1d7e291b37e2303bf5d03b2bb5e5640d0f
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106437
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Tested-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R31b1c4aeaf3f3779ba4ffe8c80649787f5f8fe62

5 years agotegra: usb: removal of WAR for ASUS bit
Suresh Mangipudi [Tue, 5 Jun 2012 10:03:08 +0000]
tegra: usb: removal of WAR for ASUS bit

Removal of ASUS bit for t114.

Bug 969349

Change-Id: I32bd31509618f289d89cd195e6803411701a7f2e
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106434
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6f810b3945cfbed32287a0db65af245c8f5cff2d

5 years agoARM: tegra: Disable LP2 for tegra3 A01 only
Bo Yan [Thu, 31 May 2012 06:45:10 +0000]
ARM: tegra: Disable LP2 for tegra3 A01  only

Change-Id: I6986aba95daa1d82ffa47810dbe6f7145f411bdd
Reviewed-on: http://git-master/r/105608
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R959659cae9e073ee44c9b7e0ff6fe6915fbe69b2

5 years agoARM: tegra11: Support power gating CPU0 partition
Bo Yan [Tue, 29 May 2012 23:59:56 +0000]
ARM: tegra11: Support power gating CPU0 partition

If user selects CPU0 partition power gating, then force power gating
CPU0 partition only.

If user selects non-CPU partition or rail-gating, then do so in the
same way as on platforms not supporting symmetric CPU power gating.

If platform supports symmetric CPU power gating and current CPU is
not the last one, also force power gating CPU0 partition only.

Change-Id: I50155afcfa2210ea492a0e62231482888e1a5d90
Reviewed-on: http://git-master/r/105245
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0a21427dec84b97860532acb37921ff6899f306a

5 years agoARM: tegra11: clock: Re-arrange pll delays
Alex Frid [Sun, 3 Jun 2012 05:55:18 +0000]
ARM: tegra11: clock: Re-arrange pll delays

Reduced delays between steps in dynamic ramp PLLs control procedures
from 2us to 1us (with the exception of PLLX/PLLC IDDQ control).

Completely removed delay at the end of PLLC2/PLLC3 strobe (no need,
since next step after strobe is waiting for lock, anyway).

Change-Id: I23bfffdd8f297b3085c1b8ead8ab58b2704b7d95
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106111
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R237a1e795c7b870ad033354847759781f38a4152

5 years agoARM: tegra11: clock: Update PLLX/PLLC ramp steps
Alex Frid [Sun, 3 Jun 2012 05:33:47 +0000]
ARM: tegra11: clock: Update PLLX/PLLC ramp steps

Updated PLLX/PLLC ramp steps to match recent h/w changes.

Change-Id: Ie224972f7499fef7f90ffd9819c2cfb0e1b57470
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106110
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rccb3f0da0934be4a86c573e07e9ac099fa91c42b

5 years agoARM: tegra11: clock: Update PLLC2/PLLC3 configuration
Alex Frid [Sun, 3 Jun 2012 04:19:08 +0000]
ARM: tegra11: clock: Update PLLC2/PLLC3 configuration

Updated PLLC2/PLLC3 configuration to match recent h/w changes.

Change-Id: Ib023906531b41dbfcd5be4d9fca8dc7fd766dbdd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106109
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R6477398679ce87c4c89963c16761ca5659ca6689

5 years agoARM: tegra11: clock: Update PLLC2/PLLC3 dynamic ramp
Alex Frid [Thu, 31 May 2012 01:04:19 +0000]
ARM: tegra11: clock: Update PLLC2/PLLC3 dynamic ramp

PLLC2/PLLC3 dynamic ramp is not supported for new extended post
divider settings. Updated dynamic ramp procedures accordingly.

Change-Id: Id7d83b142ab3008ed38c8664c74ae1b61e83b2d0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106078
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R0f5bd6e5ee50b493d873e4cda4c8e554c685993b

5 years agoARM: tegra11: clock: Support non-linear pll post dividers
Alex Frid [Fri, 25 May 2012 06:16:09 +0000]
ARM: tegra11: clock: Support non-linear pll post dividers

Added non-linear look-up table to map PLLC2/PLLC3 post dividers
settings into divisor values, and re-factor pll set rate operation
accordingly. Apply similar re-factoring to PLLX/PLLC, although
divider settings for these plls are still limited by s/w to the
range with linear mapping.

Change-Id: I8f968f6d243d974836c98b05dd9425aa5eab7280
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106077
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb559949ec22722e30ec3ead3ed98fbba4736598b

5 years agoarm: tegra: usb_phy: add support for t114 usb_phy
Suresh Mangipudi [Mon, 4 Jun 2012 14:22:46 +0000]
arm: tegra: usb_phy: add support for t114 usb_phy

Supoorted added for t114 usb_phy driver.

Change-Id: Ib3ab79a86f1092a3073dc80e3d426105391518e7
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106211
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: Rcf6d31ebbfef94f24d5b754d5525b9b8c4fca27b

5 years agoARM: tegra: clock: Initialize wake.sclk to 250 MHz
Alex Van Brunt [Thu, 31 May 2012 21:39:17 +0000]
ARM: tegra: clock: Initialize wake.sclk to 250 MHz

The JTAG probe must drive TCLK at less than 1/6th of sclk for JTAG
to function. The JTAG probe is not able to go slower than 4 kHz in
the real world. By setting sclk to 250 MHz in design time, it runs
faster than the required 24 kHz in the real world.

Bug 983408

Change-Id: Ifd3b4d454dbe2e96222290059580947ce93ade41
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/104233
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra412dd39d9dfc83062a2b931f56efbb6c904d003

5 years agoARM: tegra11: Update cache flush/invalidate for power gating
Bo Yan [Sat, 19 May 2012 02:38:05 +0000]
ARM: tegra11: Update cache flush/invalidate for power gating

The field ENABLE_EXT in CSR register controls what power partition
to be gated. If it's CPU-partition power gating only, there is no
need to flush or invalidate L2 cache before/after power gating.
With this change, L2 cache is flushed/invalidated only when the
non-CPU partition is to be power gated or when rail gating is
selected.

Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R3108cb94a1efc64574ff58067e239bd8539e6059

5 years agoARM: tegra: Disable CPU interface in power gating
Bo Yan [Tue, 29 May 2012 23:18:37 +0000]
ARM: tegra: Disable CPU interface in power gating

CPU interface needs to be disabled to avoid race condition. Simply
disabling legacy pass-through is not enough.

Change-Id: I4202d870036b137bdfd3b1d32a5781e2ef65ead9
Reviewed-on: http://git-master/r/105235
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rfccde91150c20d801e9e016039b2e64c8a2fabaf

5 years agoARM: tegra11: Select partitions for power gating
Bo Yan [Sat, 19 May 2012 02:47:34 +0000]
ARM: tegra11: Select partitions for power gating

Select power gating partitions based on flag. With this change,
Rail-gating is used as the default power gating option for CPU0
on cluster 0, non-CPU gating is the default power gating option
for CPU0 on cluster 1.

Also fixed  power gating flags by using control macros instead of
CSR field macros.

Change-Id: I971a34cc01f0216314f4bdbafc9aa070ca0dd708
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103477
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

Rebase-Id: R90ff171fb99007996ac159955095bed568960000

5 years agoARM: tegra: t114: new sub driver changes
Krishna Yarlagadda [Mon, 28 May 2012 17:58:49 +0000]
ARM: tegra: t114: new sub driver changes

modify board file to support new usb design

Change-Id: I496a665d3ccd5a46e55a88385bc9c94c4239d318
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/104989
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R1538617630f28732b0c0b16af1e1286556b56351

5 years agoARM: tegra11: clock: Remove host1x from cbus
Alex Frid [Thu, 24 May 2012 04:18:13 +0000]
ARM: tegra11: clock: Remove host1x from cbus

According to tegra11 clock policy moved host1x clock from cbus with
scaled PLLC source to fixed PLLP clock source. This allows completely
shut-off PLLC in use-cases when all graphics clocks are disabled, and
host1x is used only by display.

Change-Id: I100b9f4a9978deea1401a004eb855c5fc5ce8dcd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104320
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rd7cac155f5056912709b323a0a0d3ade86d74d48

5 years agoARM: tegar11: clock: Support cbus users auto-migration
Alex Frid [Tue, 22 May 2012 01:26:11 +0000]
ARM: tegar11: clock: Support cbus users auto-migration

Automatically move graphics clocks between 2 buses (with PLLC2 and
PLLC3 as respective clock sources), so that at any moment the user
requesting the highest rate among all enabled cbus modules has the
slowest dvfs table on the bus it is attached to.

Configuration option for auto-migration is disabled by default.

Bug 965702

Change-Id: I837ed6de163303bc4998bdcf4c7c4a4706b1ee6c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104297
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rf647e1d746b95b316beaff8aa04f6267a74e04f3

5 years agoARM: tegra11: Fake clk-m rate as 13M in Quickturn
Bo Yan [Wed, 23 May 2012 01:10:22 +0000]
ARM: tegra11: Fake clk-m rate as 13M in Quickturn

In Quickturn environment, the detected clock rate can be 115200
or 230400. In this case, we need to fake clock rate as 13M.

Change-Id: I926bc932a002c17c463a62bebce2554194c716cd
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/104029
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rde09a61ede880cad10a3038dde9a01892c1aa430

5 years agoARM: tegra: curacao: Enable SDMMC3
Pradeep Kumar [Thu, 24 May 2012 10:53:39 +0000]
ARM: tegra: curacao: Enable SDMMC3

Enable SDMMC3 for SD 3.0 Card testing.

Bug 953433
Bug 837138

Change-Id: I38ba198c7b2e9eb1e1fd5b303b4ec371e7b2df68
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/97505
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R1d7d45b9865c28fb0939bc42f77a58b8c2dbc266

5 years agoARM: tegra: Add descriptions of the new cbus configuration options.
Alex Frid [Wed, 23 May 2012 21:51:34 +0000]
ARM: tegra: Add descriptions of the new cbus configuration options.

Change-Id: Ib61e05553755b2cab09a74f02f1f99a0a206b62a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104255
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Racffa0ede0359a3ec356296d23229653e56496d1

5 years agoARM: tegra11: clock: Add support for dual cbus
Alex Frid [Wed, 16 May 2012 03:11:02 +0000]
ARM: tegra11: clock: Add support for dual cbus

Added support for 2 buses with graphics modules sourced from PLLC2,
and PLLC3. Default bus population: 3D and 2D modules are on PLLC2,
and all others (EPP, MSENC, VDE, TSEC, SE, Host1x) are on PLLC3.

Configuration option for dual cbus is not selected, yet. Hence,
current build configuration still run all graphics modules on PLLC.

Change-Id: I2ecbf098cb6d0f305e27c3583637b8c6e1719e46
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/103715
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R536402230130c95c5dd671ecbf9987d4899d83e7

5 years agoARM: tegra11: clock: Add shared user set parent operation
Alex Frid [Thu, 17 May 2012 03:05:14 +0000]
ARM: tegra11: clock: Add shared user set parent operation

Expanded shared user operations with set parent support. Since shared
bus and its children/users have reversed rate relations - user rates
determine bus rate - switching user from one parent/bus to another may
change rates of both parents. Therefore, we need a cross-bus lock on
top of individual user and bus locks. For now limit bus switch support
to cansleep users with cross-bus mutex only.

None of current shared users can utilize this expansion.

Change-Id: Ie01a9cf6d49cece3b498809ff3467fc43714ec34
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/103714
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb90d79a3930be5814544181dd5ab089cf7bafc82

5 years agoARM: tegra: Clean up flow controller CSR macros
Bo Yan [Sat, 19 May 2012 02:55:18 +0000]
ARM: tegra: Clean up flow controller CSR macros

Group flow controller macros for CSR register in one place in sleep.h
Also strip "CPU" out of macro names because the corresponding COP CSR
register has only one field INTR_FLAG which is at bit 15, same as CPU
CSR, so there is no confusion here.

Change-Id: Ib3dea0bd3e9051d1e7b9048abc4afde5ddc8bab5
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103478
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>

Rebase-Id: R63c198f17e573818b8d44482c46cb61516bf1267

5 years agoARM: tegra: Fix argument name for GIC function
Bo Yan [Mon, 21 May 2012 23:43:15 +0000]
ARM: tegra: Fix argument name for GIC function

The argument "pass_through" of function tegra_gic_cpu_disable is
confusing. If it's true, it actually means "to disable" pass-through.
Change it to "disable_pass_through" to reflect what it really is.

Change-Id: I4a08b8965641af913ebb626c81cdac3382a995a0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103729
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rd2af746d5742fb03fd094eaf4678bf078add0ba3

5 years agoARM: tegra: Define accessor for gic version
Bo Yan [Mon, 21 May 2012 23:24:12 +0000]
ARM: tegra: Define accessor for gic version

Accessor function is defined to return GIC version in system. Since
the returned value is u32, read out the GIC version number directly
from GIC ICPIDR2 register instead of forcing it to 2 as implied in
CortexA15 implementation or 1 in CortexA9.

Change-Id: Ib7a948656faf9552aef1bb3effa28f827c17d0f1
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103728
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R7bb73e0a0c8da81a747730b7d584eaf99bf16631

5 years agoARM: tegra: Add control for power gating mode
Bo Yan [Wed, 16 May 2012 19:46:48 +0000]
ARM: tegra: Add control for power gating mode

Add a module parameter to control what power gating mode to use
for LP2. There are 4 options: non-cpu power gating, rail gating,
CPU only power gating, or emulation mode.

Change-Id: I1529b28f7b478df980aa4e8ac2557b6ffdfe8e73
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/102880
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

Rebase-Id: Rce6345b9c876ebead0699b3d1f87270ab41779b1

5 years agoARM: tegra: power: Flush L1 to hot unplug CPU
Bo Yan [Wed, 16 May 2012 19:59:22 +0000]
ARM: tegra: power: Flush L1 to hot unplug CPU

This will ensure only L1 is flushed when hot unplugging non-boot
CPUs for CortexA15

Change-Id: Id78f801e5501d34dd43618179440adcf47666739
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/102881
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R37219dc63b66ffaee6bc866e403d1da509464142

5 years agoARM: tegra11: clock: Adjust cbus dvfs table dynamically
Alex Frid [Thu, 10 May 2012 05:36:31 +0000]
ARM: tegra11: clock: Adjust cbus dvfs table dynamically

Dynamically adjusted cumulative cbus dvfs table instead of using
static table that specifies worst case voltage requirements for
all cbus clients. Table adjustment takes into account only clients
enabled when cbus rate is updated, and ignores disabled clients.
Adjustment algorithm selects the dvfs table of the slowest enabled
client as new cumulative cbus dvfs table.

Changing dvfs table in flight makes cbus clock unique from voltage
control prospective: voltage requirements may change even when rate
is not changing; moreover voltage may go down while rate is going up
and vice versa. Hence, separated cbus update from common shared bus
rate control.

Bug 965692

Change-Id: I662fd08ab0481200221c7786edfa5249df567d54
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102716
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R7af46bab4520754b0802a6128a2db2f71930f0cd

5 years agoARM: tegra: curacao_sim: Enable NVAVP
Jeff Smith [Wed, 9 May 2012 16:19:50 +0000]
ARM: tegra: curacao_sim: Enable NVAVP

Disable mediaserver

Change-Id: Idb3556b55294db5a266cb9e1ff471dba69443c48
Reviewed-on: http://git-master/r/102113
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rffcfecb34165e108638ec4b525bdf2dd9abac61e

5 years agoARM: defconfig: curacao: update the defconfig to that of android
Preetham Chandru [Tue, 15 May 2012 11:57:51 +0000]
ARM: defconfig: curacao: update the defconfig to that of android

update the defconfig to that of tegra_curacao_android_defconfig. The configs
enabled are
1. MAX77663 MFD and Regulator
2. GPIO Regulator
3. NVAVP
4. I2C
5. USB_TEGRA
6. Ethernet
7. NETFILTER_XT_MATCH_OWNER
8. SMP

Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Tested-by: Chetan Hooli <chooli@nvidia.co>
Bug 944760
Change-Id: I0be287b4f41eee242b5df9885d5cf4a6c1c718ae
Reviewed-on: http://git-master/r/102587
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R2ba4df702e5429b37da2c543069535b15a01f647

5 years agomfd: max77663: register driver only if device is present
Pradeep Kumar [Thu, 17 May 2012 04:25:31 +0000]
mfd: max77663: register driver only if device is present

Performing a dummy read to chip_id register return error
from probe of this dummy read fails.

Bug 984138

Change-Id: Ib1ec804765ab00b6e2ea7e42c30e96722343c55e
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/103013
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R9a1e86a417e95cfbc2adb914459b1b4713b376bd

5 years agoARM: tegra: implement L1 cache flush function
Bo Yan [Tue, 15 May 2012 22:27:39 +0000]
ARM: tegra: implement L1 cache flush function

The function flush_cache_all flushes all caches within level of
coherency. For CortexA9, this is ok since only L1 is defined. For
CortexA15, it will flush both L1 and L2, this behavior is not
desired when there is no need to touch L2. So a new function is
defined to just flush L1 cache.

Change-Id: Id5a651770b70496d0dde6e90b226a19df90a57d0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/102682
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R06daabe836a97de0f4cace26235bf06ffbd49501

5 years agoARM: tegra11: clock: Don't backup detached cbus clocks
Alex Frid [Thu, 10 May 2012 03:29:05 +0000]
ARM: tegra11: clock: Don't backup detached cbus clocks

Check if cbus clock is attached to cbus parent pll before switching
it to backup source - no need to backup detached clocks. At this point
cbus clients are on different pll (used by boot-loader) only in early
initialization. Similarly skip detached clients during explicit dvfs
update (when dynamic ramp is enabled).

Change-Id: Ia7bfbe67b678f020538e10307a27fd72cf4026bf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R7993d622d09dd14e9d8500f12197fd32c224978e

5 years agoARM: tegra11: dvfs: Remove core dvfs table in simulation
Alex Frid [Tue, 15 May 2012 00:09:35 +0000]
ARM: tegra11: dvfs: Remove core dvfs table in simulation

Simulation setup over-clocks graphics (cbus) modules, and Tegra11
boot would fail if preliminary dvfs tables are enforced. Remove
tables for now to unblock simulation.

Change-Id: I398490b4aa0597c3f87483c03c8102bf36c65424
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102373
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

Rebase-Id: Rb5605c2e115f1796b4bfc83b654eb5ca546c7dc5

5 years agoARM: defconfig: curacao: Enable CONFIG_USB_TEGRA
Rakesh Bodla [Fri, 11 May 2012 07:48:16 +0000]
ARM: defconfig: curacao: Enable CONFIG_USB_TEGRA

Enable tegra udc driver.

Bug 983006

Change-Id: If761a2eeb9dec01bd47ab0ca728eb43ac9ebb926
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/101924
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R048b2ea5f655b821d68b13834628fcd97fd99ccb

5 years agoARM: tegar11: clock: update the udc driver name
Rakesh Bodla [Fri, 11 May 2012 07:45:42 +0000]
ARM: tegar11: clock: update the udc driver name

Update the clocks structure to use new udc driver
name.

Bug 983006

Change-Id: I95c64b214aa845e4cbf509bca0416d80e6273aac
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/101923
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb6b365b5445e56ef9be22c65cbbdfa8ffe7fac3d

5 years agoARM: tegra11: clock: Remove non-supported emc bridge
Alex Frid [Wed, 9 May 2012 05:27:40 +0000]
ARM: tegra11: clock: Remove non-supported emc bridge

Change-Id: Ieb463e6138286b1c61ef71959b94f93f1cf4452e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101813
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3acd5e8e9e846f585d86ebd8ebf4e7b9d1c1bff4

5 years agousb: gadget: tegra: add support for FPGA
Rakesh Bodla [Fri, 11 May 2012 07:43:37 +0000]
usb: gadget: tegra: add support for FPGA

On FPGA VBUS is detected through VBUS A Session instead
of VBUS status. Updated this where ever it is necessary.
Also added the clearance of ASUS bit to prevent
auto suspend present in H/W.

Bug 983006

Change-Id: I91e4554e39703c861dc5055c24812b5d34615949
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/101514
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: Rd88ba8970196ad1c8d60f75614df474a53128556

5 years agoARM: tegra11: clock: Don't apply common limit to cbus users
Alex Frid [Sat, 5 May 2012 01:36:05 +0000]
ARM: tegra11: clock: Don't apply common limit to cbus users

The cbus dvfs table is currently constructed to guarantee safe
operations of the slowest client at any rate, and cbus maximum
rate at nominal voltage is applied as common limit to all cbus
shared users.

The latter provision is changed now: each shared user has its
own limit set equal to the maximum rate of the the respective
graphics module. Thus, individual users rate requests are no
longer throttled by the slowest one. Still final bus rate is
subject to worst case dvfs table, so this commit just allow for
unthrottled user request recording with no actual change in
final rates/voltages.

Change-Id: I89c463d2c52f4028ebaf433c69ac99b6131281e5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101863
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R37819131d668c8b056a489c19467900a97576063

5 years agoARM: tegra11: clock: Remove non-existed 3D2 clock
Alex Frid [Thu, 10 May 2012 00:24:01 +0000]
ARM: tegra11: clock: Remove non-existed 3D2 clock

Change-Id: I768b86ce93c5a2875a6f2b1406f7e02094aa55b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101812
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9e9aadb2e23ab91318e922a4d4d7008447f68d71

5 years agoARM: tegra11: clock: Don't round shared user request
Alex Frid [Thu, 3 May 2012 02:49:15 +0000]
ARM: tegra11: clock: Don't round shared user request

Keep raw individual shared user requests before aggregation - just
clip them to shared bus range. Apply bus rounding only after the
requests are aggregated.

Change-Id: I53889670e89363f47d3722825ecd5d6dd3d9fda7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101811
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Reffb58910b98e1c621ed6d0859005599f60c166a

5 years agoARM: tegra11: curacao: Set suspend mode to LP1
Bo Yan [Thu, 10 May 2012 02:14:06 +0000]
ARM: tegra11: curacao: Set suspend mode to LP1

System will disable LP2 if suspend mode is TEGRA_SUSPEND_NONE when
initializing suspend. Set it to TEGRA_SUSPEND_LP1 to unblock LP2.

Change-Id: I191d981280b7bc47378e24ecbd60f8bf586845cb
Reviewed-on: http://git-master/r/101645
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R22018e95ae812edfe8d31b4c3c6271b29bd13006