6 years agosecurity: tf_driver: integrate latest TL release
Karan Jhavar [Sat, 21 Jul 2012 02:42:55 +0000]
security: tf_driver: integrate latest TL release

Tegra 3 version: TF_TEGRA3_AB01.11.35578, TF_TEGRA3_AB01.11p1.35578
                 TF_TEGRA3_AB01.11p2.36386, TF_TEGRA3_AB01.11p3.36518
         TF_TEGRA3_AB01.11p4.36577, TF_TEGRA3_AB01.11p5.36677

1)Add memory profiling tool to debug secure services's stack and heap
2)Add support to enable dynamic clock gating feature in PL310 register
3)TEE client API at kernel level
4)Stable FIQ debugging (SDK ver 1.09)
5)clrex stability change
6)GIC controller stability settings
7)Fix LP1
8)Fix floating pt support

Bug 1021831

Change-Id: I5c2a693a27dc591b62863aa0fe4ff65163e67aba
Signed-off-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-on: http://git-master/r/117515
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R0eaf29c4f060f0ba51d39fd8d9372c2c87d14dd4

6 years agomm: failslab: Add support to force slab alloc failures based on size.
Krishna Reddy [Wed, 18 Jul 2012 21:06:50 +0000]
mm: failslab: Add support to force slab alloc failures based on size.

Any alloc request, with  size greater than PAGE_SIZE, to
slab allocator is not guarnateed to succeed, even though
enough memory is available, as memory can get fully fragmented
over the time.
This allows finding the slab allocator requests with size
greater than PAGE_SIZE early and avoid finding issues much late
in product life cyle.

Change-Id: Ibf13e626a671d41569415a56e775ac5e96b90ba3
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/116855
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 604a65f8e3c9472886b48b1a287f78f11235d1ce)
Reviewed-on: http://git-master/r/118193
Reviewed-by: Alex Waterman <alexw@nvidia.com>

Rebase-Id: Rfb2f7b8d0365dd983d67ad4e9f63735316f52207

6 years agousb: ehci: tegra: Update RUN bit properly.
Suresh Mangipudi [Tue, 24 Jul 2012 07:22:00 +0000]
usb: ehci: tegra: Update RUN bit properly.

Read the RUN bit and update it properly.
Remove unused variable.

Change-Id: I1df5dc99ce40e2ca15f0ade28d156a7262467519
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/117958
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R457a7eb43bf4737959be5902e741dd2ca4e813c9

6 years agousb: ehci: DMA buffer sync for qh/qtd descriptors
JC Kuo [Tue, 17 Jul 2012 09:57:44 +0000]
usb: ehci: DMA buffer sync for qh/qtd descriptors

When EHCI host controller driver examines qh/qtd descriptors, driver
might see stale data in cache on some ARM CPU. This patch introduces
two helper functions, ehci_sync_qh() and ehci_sync_qtd(), to
invalidate cached descriptors so that driver can always read
up-to-date descriptors from memory.

Bug 1005403

Change-Id: I2345bda7dfe29c5fe7f9550066b518cd6624d263
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/116406
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: ChihMin Cheng <ccheng@nvidia.com>
Reviewed-by: Joy Wang <joyw@nvidia.com>
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R5e1f4a516324e968a9fe099e862c1ff3ed028921

6 years agoARM: tegra: move secondary start kernel message
Jake Park [Tue, 24 Jul 2012 04:59:45 +0000]
ARM: tegra: move secondary start kernel message

Using printk before CPU online can make hang or kernel panic.

Bug 1017539
Bug 1019700

Signed-off-by: Jake Park <jakep@nvidia.com>
Reviewed-on: http://git-master/r/117924
(cherry picked from commit 9d7426fdc7e8c70079d37f529517932370355ac6)

Change-Id: Ib55ee06dcaf92af63f8d72ee74939c72dda4296c
Reviewed-on: http://git-master/r/118141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com>
Tested-by: Sang-Hun Lee <sanlee@nvidia.com>

Rebase-Id: Rc623cf4ba3eec321c2916c556c8940c412f9f9dc

6 years agoARM: tegra: cpuquiet: Fix cpuquiet notifiers
Sai Charan Gurrappadi [Wed, 25 Jul 2012 18:16:08 +0000]
ARM: tegra: cpuquiet: Fix cpuquiet notifiers

The notifiers now properly fire on every cluster switch

Change-Id: I381301cf62f25b49532326cc7759696c7f6797b7
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/118376
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rd93d027e02b4f1122becef42916b28e652c76980

6 years agousb: cdc-acm: fix packet loss issue
Steve Lin [Thu, 19 Jul 2012 19:36:18 +0000]
usb: cdc-acm: fix packet loss issue

There is race between acm_suspend and acm_read_bulk_callback. Host may
receive bulk transfer right before suspend. The packet will be discarded
if this urb is killed in acm_suspend. This patch checks the actual length
of urb and processes it in this case.

Bug 996268

Signed-off-by: Steve Lin <stlin@nvidia.com>

Change-Id: Ief2b42708160b67903f976ec60da825d46c4720b
Reviewed-on: http://git-master/r/117135
(cherry picked from commit af3e96c987fbae8a135d1ff18872b9c32e09b67f)
Reviewed-on: http://git-master/r/118105
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Steve Lin <stlin@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: Ra9c649f283042f8ab62d3d23880d0fe3445dea6f

6 years agoarm: tegra: pci: Organize pcie initialization code
Jay Agarwal [Sat, 21 Jul 2012 18:17:33 +0000]
arm: tegra: pci: Organize pcie initialization code

1. Initialize PCIe on every resume whether device
   is dock/undocked.
2. Poweroff PCIe if Poweron failed at any stage.
3. Make PCIe initialization robust so that it is
   successful anytime dock is connected i.e while
   in LP0 or after it's exit or else.

Bug 1020949

Change-Id: I79cd75f2bf7164a9b5c8906a370364dba5183ac8
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/117532
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R6c173f2d07d0fcc4000354a61f41c180612d28cf

6 years agortc: tps6591x: Prevent wrong date setting
Preetham Chandru [Fri, 20 Jul 2012 05:31:26 +0000]
rtc: tps6591x: Prevent wrong date setting

This CL handles the following:

1. Prevents setting of wrong date in tps6591x_rtc_set_time().

For example the following case was not handled in rtc driver:
if hwclock command wanted to set 31/Dec/1999 then our RTC driver was
setting the date to 31/Dec/2099 and later on when hwclock read the
date back it was getting a invalid date.
Also, the hwclock command can only handle date upto the year 2038.

2. Sets STOP_RTC bit to one when the driver is initialized

Bug 1012914
Bug 1017647
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Change-Id: If8abfebe3ee6da05498deb38d7247ab265729c0c
Reviewed-on: http://git-master/r/117298
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R9ed8236d729ba647bbc5ee8fda8d831176f04371

6 years agochar: agp: treat compile warning as error
schowdary [Tue, 24 Jul 2012 12:04:46 +0000]
char: agp: treat compile warning as error

-enable warnings as errors compilation flag

bug 949219

Change-Id: I47e2df835985f341ebccdad95f53b4e6f7763e39
Signed-off-by: schowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/118017
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R6cebd3290fcdf2201acd6a232cc884b417bc4cfb

6 years agoarm: tegra: xmm: flash modem reset functionality
Vinayak Pane [Fri, 13 Jul 2012 00:13:07 +0000]
arm: tegra: xmm: flash modem reset functionality

Flash version modem need to do reset with gpio
and start enumeration on falling edge of ap wake.

Remove unused variable enum_delay_ms.

Bug 1003141

Change-Id: Ie43c693c3fead5c89b30c1b97cf1f3e4c05e5588
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/116886
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Chang <kenc@nvidia.com>
Tested-by: Ken Chang <kenc@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: R41a06a3a1d2eb06af6bb67402ba3d9fe9b830152

6 years agoARM: tegra: thermal: fix inform edp governor bug
Daniel Fu [Fri, 20 Jul 2012 03:27:27 +0000]
ARM: tegra: thermal: fix inform edp governor bug

Fixed bug using Tj temp to update thermal zone,
It should use EDP temp to update it.

bug 1007726

Change-Id: Ibcf2520a4bad7dc977add0b5c855681d2667a7c2
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/117250
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: R6b4dbc4f99c450c8c03090684573694e11cd712c

6 years agoARM: tegra: cpuquiet: Notify the cpuquiet governor when the driver is busy
Sai Charan Gurrappadi [Wed, 11 Jul 2012 00:33:58 +0000]
ARM: tegra: cpuquiet: Notify the cpuquiet governor when the driver is busy

Added generic busy/free notifiers that the driver can invoke to let the
governor know that it cannot process further core online/offline
requests (invoked in our case whenever we switch to the LP cluster).

Change-Id: I5e3f7f28f38806a7f87050e8d0c8d2f2cf7521aa
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/114807
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Rda88486498e7d8254373ac71213ad03db6103b39

6 years agousb: ehci: tegra: HSIC remote wakeup support
Vinod Atyam [Tue, 26 Jun 2012 09:08:48 +0000]
usb: ehci: tegra: HSIC remote wakeup support

1) Returning in irq after remote wakeup resume handled
   in ehci irq function.
2) Removed the unused variables.

Bug 889618

Change-Id: I9a1fd25c753a53462bf7742065fa618caae501ab
Signed-off-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-on: http://git-master/r/111192
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R3cc766592fdd3d46d8630bd4f6b8ffdcecf97e10

6 years agoarm: tegra: usb: Fix First SOF corruption.
Suresh Mangipudi [Tue, 24 Jul 2012 07:16:47 +0000]
arm: tegra: usb: Fix First SOF corruption.

In ULPI phy first SOF after Reset may be corrupt. Fixing this issue.

Bug 1012500

Change-Id: I45ee1b4c8e0a29298c94813030d22291b79e417b
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/117635
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rdaf75514c5d03db810261ffcf5cb7f636c7b7365

6 years agopower: tps80031: charger: enable max current limit to 2.25A
Xin Xie [Wed, 11 Jul 2012 00:33:43 +0000]
power: tps80031: charger: enable max current limit to 2.25A

Current max USB bus current limit is 1.5A, add up to 2.25A support based
on TPS8003x register documentation.

BUG 1014876

Change-Id: Iae23e2473d9a7b52dac2d92029af03729e1e8a11
Reviewed-on: http://git-master/r/114801
(cherry picked from commit 04638c07f0b5a4ecea405ed914e144004b60877d)
Reviewed-on: http://git-master/r/116115
Reviewed-by: Xin Xie <xxie@nvidia.com>
Tested-by: Xin Xie <xxie@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R781d805b999c6c63eaf28b9ddb978ad6e66a6537

6 years agoARM: tegra: usb: regulator on during lp0 on T20
Krishna Yarlagadda [Wed, 18 Jul 2012 11:34:33 +0000]
ARM: tegra: usb: regulator on during lp0 on T20

Tegra 2 requires regulator to be on during lp0

Bug 1012273

Change-Id: I750892fd391be327e617c70b7da4c984019a32fa
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/116743
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R0331b0b731fd890aed4518d73a2231af2f7a28e0

6 years agousb: ehci: tegra: prevent illegal register access
Rakesh Bodla [Tue, 17 Jul 2012 05:55:51 +0000]
usb: ehci: tegra: prevent illegal register access

Make sure phy is turned ON before reading USB
registers.

Bug 993380
Bug 1006579

Reviewed-on: http://git-master/r/116045
(cherry picked from commit a1a6db7dc88880fb3d4bca0036ce421e4032adae)
Change-Id: If94e691bf9b5b46dd8f8562f27cf86e59a4d6353
Reviewed-on: http://git-master/r/117257
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R9c7246e2dae708b1f0f034ccd69c4371848db324

6 years agoARM: tegra: phy: avoid illegal access to registers
Rakesh Bodla [Fri, 20 Jul 2012 06:11:09 +0000]
ARM: tegra: phy: avoid illegal access to registers

Adding the conditions to prevent illegal register access.

Bug 993380
Bug 1006579

Reviewed-on: http://git-master/r/113138
(cherry picked from commit a3c026a229bbce614d7f40319bada1d7bf42942d)

Change-Id: I0d8e6c20aab04aa43ae484dc8ceb6fcb2c27d151
Reviewed-on: http://git-master/r/117256
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R36ee2c010b93cd1caba329955400bbd88c993563

6 years agomfd: tps80031: Use struct dev_pm_ops for power management
Laxman Dewangan [Wed, 18 Jul 2012 13:21:55 +0000]
mfd: tps80031: Use struct dev_pm_ops for power management

Make the tps80031 driver define its PM callbacks through a
struct dev_pm_ops object rather than by using legacy PM hooks
in struct i2c_driver

Change-Id: I3963426c26eb7609794c6fe761d69f31ee630cb2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/117330
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: Rece1954a33aea1702c7b0689cc2d1f963cb4ab07

6 years agoCHROMIUM: config: enable DM_CRYPT target
Kees Cook [Thu, 9 Feb 2012 00:53:31 +0000]
CHROMIUM: config: enable DM_CRYPT target

The dm "crypt" target is needed for encrypted /var support.
Additionally, since the expected hash alg will be sha256, built it in,
and ready future support for sha512 as a module.

BUG=chromium-os:22172
TEST=build, boot amd64-generic, verify target listed in "dmsetup targets"

Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/15548
Reviewed-by: Kees Cook <keescook@chromium.org>
Tested-by: Kees Cook <keescook@chromium.org>
Commit-Ready: Kees Cook <keescook@chromium.org>
(cherry-picked from commit 50180f134a6e23be3ce763524b6b5193d848c0f7)

Modified to use:
chromeos/config/config.common.chromeos

instead of:
chromeos/config/base.config

Change-Id: Iac31f59f340f52a7017948fd5add3d316d38a123
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-on: http://git-master/r/117151
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5c452e71aedaee58b17d5fd5ef4649493f660807

6 years agodrivers: net: raw-ip: Add IPv6 support.
Michael Hsu [Wed, 28 Mar 2012 21:57:53 +0000]
drivers: net: raw-ip: Add IPv6 support.

Upon receiving IPv6 packet, set ethernet header's ether type
to 0x86dd.  For transmission of IPv6, nothing extra required,
as the 14 byte ethernet header (containing the 0x86dd ether
type) is already stripped off as part of the raw-ip protocol.

Bug 1010735

Change-Id: Id574a7feeefbde0504ad0ea449dff28340e9356a
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: http://git-master/r/113761
(cherry picked from commit 8bdfd06cae7eede4856ef825ea26b69c9ea065ef)
Reviewed-on: http://git-master/r/117148
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Tested-by: Vinayak Pane <vpane@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: Ra8fb2eeb32e58acd67ad423df2960bf5515384c0

6 years agoARM: tegra: clock: Reduce Tegra3 pll post-lock delay
Alex Frid [Sun, 15 Jul 2012 03:11:04 +0000]
ARM: tegra: clock: Reduce Tegra3 pll post-lock delay

Reduced pll post-lock delay from 50us to 2us.

Rearranged wait for lock loop to delay first check of lock bit
by 2us after pll is enabled.

Added read fence for PLLM lock via PMC (in this case enable bit is
in APB bus register, but lock detect bit is in PPSB bus register).

Bug 1017271

Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/115933
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R4b90af965e631dbd0e6437946d61809836c7306d

6 years agoARM: tegra: power: Enforce CPU rate range in secondary boot
Alex Frid [Fri, 18 May 2012 05:11:55 +0000]
ARM: tegra: power: Enforce CPU rate range in secondary boot

On Tegra3 make sure cpu rate is within G-mode range before LP to G
mode switch triggered by secondary cpu boot directly from LP mode.

Bug 988544

Change-Id: I0d86fbf0727a6bbf6069159e7c532947a9d0af73
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/115930
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Greg Lo <glo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R2058bc1820b2d27c927de4b2d5b2bc03746fd668

6 years agoARM: tegra: clock: relax memory efficiency if 3d clock is off
Peter Zu [Thu, 5 Jul 2012 01:56:48 +0000]
ARM: tegra: clock: relax memory efficiency if 3d clock is off

Bug 1003509

Change-Id: I8fb2c0cff7106671f8470b836ea26c09350d6206
Signed-off-by: Peter Zu <pzu@nvidia.com>
(cherry picked from commit df2dda0438c2aed3a961d197dce7319fefdf5b30)
Reviewed-on: http://git-master/r/115468
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Re47cc8ee4befcb1e22bdcf04db65d85d9736a820

6 years agoARM: tegra: dvfs: add back 916mV & 1007mV entries
Peter Zu [Fri, 6 Jul 2012 00:01:12 +0000]
ARM: tegra: dvfs: add back 916mV & 1007mV entries

Bug 841336

Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/113751
(cherry picked from commit 833f9d47a350358000e9201f77a3c9fd655d2900)

Change-Id: I679093d9d2577625bff3e02e25ffe90d396ea5a6
Reviewed-on: http://git-master/r/116134
Tested-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rb3514f374f01689bb83f01799f602913722447e8

6 years agoARM: tegra: dvfs: update Tegra3 single-core dvfs table
Peter Zu [Fri, 22 Jun 2012 18:11:49 +0000]
ARM: tegra: dvfs: update Tegra3 single-core dvfs table

Bug 841336

Signed-off-by: Peter Zu <pzu@nvidia.com>
Reviewed-on: http://git-master/r/110587
(cherry picked from commit c0e7904245168cafc426219948ab132a4d832376)

Change-Id: I370f4af1d4ce888ebc71351519c1018b82d91913
Reviewed-on: http://git-master/r/116132
Tested-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rd81f9b26faceefa9fe4de3778cf579d36ead9f88

6 years agoarm: tegra: pci: unmap/map memory while pwroff/on
Jay Agarwal [Mon, 16 Jul 2012 11:14:15 +0000]
arm: tegra: pci: unmap/map memory while pwroff/on

Rearranged the code to release all memory and res-
ources whenever poweroff is called and re-allocate
them whenever power on is called.

Bug 963969

Change-Id: I31d9cd1e8603e638714bba765aadfdd4eed78d93
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/116048
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R4de028263ca10a49299fae993595c56ce2877ef0

6 years agoARM: tegra: reset io dpd mode
Bitan Biswas [Thu, 12 Jul 2012 13:03:37 +0000]
ARM: tegra: reset io dpd mode

Bootloader io dpd settings are cleared during kernel initialization

bug 758856

Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/115395
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R2a63cb307f02dc2870e73c6a9fcc73e8c76dca32

6 years agoarm: tegra3: usb_phy: HSIC rail consumes 4mA in suspend
srinivas [Mon, 16 Jul 2012 10:39:12 +0000]
arm: tegra3: usb_phy: HSIC rail consumes 4mA in suspend

In auto-suspend, removed power downs for HSIC from
 PADS_CFG1 register.

Bug 1011912

Change-Id: I646c196ef9b822ae8d9e12a0f918507fcdd16f0b
Signed-off-by: srinivas <sthaduvai@nvidia.com>
Reviewed-on: http://git-master/r/116044
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R29eb88ec03fed5ba3a63fcc968b6ea75ce222165

6 years agoARM: mm: cache-l2x0: Implement outer_clean_all()
Kirill Artamonov [Mon, 16 Jul 2012 14:24:00 +0000]
ARM: mm: cache-l2x0: Implement outer_clean_all()

There is already implemented full outer clean routine in
arch/arm/mm/cache-l2x0.c.

Make it possible to use it through outer_cache interface,
like other outer maintenance functions.

bug 983964

Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef
Reviewed-on: http://git-master/r/116074
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Tested-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Justin Paver <jpaver@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rf769958fea9fd10058a4805eeafe08f5f0e895dd

6 years agoarm: tegra: PLLX LP/G ports switching ON/OFF
Prem Sasidharan [Thu, 5 Jul 2012 18:56:14 +0000]
arm: tegra: PLLX LP/G ports switching ON/OFF

Enable target PLLX port(LP/G) before cluster switch and disable
the previous PLLX port(LP/G) after cluster switch is finished.
Seeing a power improvement of ~10mW when core operates at
max. voltage and max. frequency.

Bug 997358
Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com>
Change-Id: I9d05245977f9f63a8f4c53b1c6797118d2d8b903
Reviewed-on: http://git-master/r/113399
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R78b0623f2478f2b4844d5912d5dbf74b7ae7537e

6 years agoARM: tegra: dvfs: Handle Tegra3 alternative dvfs errors
Rohan Somvanshi [Tue, 3 Jul 2012 12:28:01 +0000]
ARM: tegra: dvfs: Handle Tegra3 alternative dvfs errors

Propagate error to the caller when switching between alternative
cpu dvfs tables. Change dvfs table during cpu hotplug operation
only after the new edp limit is set, and abort bringing cpu core
on-line in case of failure in applying new (less conservative)
table. When cpu core is removed change dvfs table before setting
new edp limit, and ignore error (it is safe to continue with more
conservative table).

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 951710ec179fd620a2251d0815ca7bff15da014b)

Change-Id: Ib1ad8e41093fb9bee75d3d6bd18d0ac406da8271
Reviewed-on: http://git-master/r/114779
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R4fe6ed2e586814871a5d32b07e433b16fa4c6e75

6 years agoARM: tegra: Fix build issue for no-SMP
Alex Waterman [Tue, 10 Jul 2012 00:23:50 +0000]
ARM: tegra: Fix build issue for no-SMP

Fix issues causing the kernel build to fail with CONFIG_SMP not set.

Change-Id: I8c7a49970e55354e38ce41d2d1e0dab00ba78f24
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/114317
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R559d7ca9093783fafd37928019136d0387fb08f7

6 years agoarm: tegra: usb: phy code clean up
Venu Byravarasu [Fri, 13 Jul 2012 06:08:04 +0000]
arm: tegra: usb: phy code clean up

Code clean up of usb phy driver

Change-Id: If951ed461b096be76938504d9e1073a70f59860a
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/115339
(cherry picked from commit 6d4046a6f2170dadaf5647f0bf47aa546dd705b0)
Reviewed-on: http://git-master/r/104055
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Ra759668fd0aeb4392c9a8bbc5fd0c74306d30678

6 years agochromeos: config: renormalize cfgs and drop debug_ll
Rhyland Klein [Mon, 16 Jul 2012 19:43:50 +0000]
chromeos: config: renormalize cfgs and drop debug_ll

Renormalize split configs based on current TOT k3.1 kernel and
remove DEBUG_LL to clean up the kernel log a bit.

BUG=None
TEST=Verified generated config doesn't prompt.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Change-Id: Ib13e633742a2c4e0060629d145e0571e7a7d5241
Reviewed-on: http://git-master/r/116136
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

Rebase-Id: R107fdb435c4f335d80e0f378f405d2b673f210d6

6 years agoasoc: tegra: p852: Added machine driver for P852
Nitin Pai [Fri, 6 Jul 2012 11:01:11 +0000]
asoc: tegra: p852: Added machine driver for P852

Renamed P1852 machine driver to VCM so that can be used
for P1852/P852 and E1853 as well.

Bug 1008391

Signed-off-by: Nitin Pai <npai@nvidia.com>
Reviewed-on: http://git-master/r/113886
(cherry picked from commit 5eb23e30bab716b28146b85438989e58761c7136)
Change-Id: I8d1363a6419c6381b8d23ebd38d625fb482084dc
Reviewed-on: http://git-master/r/116056
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: Rc3b61e02858e533b8f6504279d2f5d2c2776b7f4

6 years agoARM: tegra: Add copyright to Kconfig
Mohit Kataria [Wed, 20 Jun 2012 05:29:37 +0000]
ARM: tegra: Add copyright to Kconfig

ARM: Tegra3: clocks: optional se.cbus

Made se.cbus optional so that se clock can be derived
from other clocks and not just from the clocks which drive cbus.

Added config option for the same.

Bug 978870

Change-Id: I7b5bf405efb58bbb53143f52d2bfe0ebcf6b8322
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/110827
(cherry picked from commit 35e9017b79a3a4b4e0b4098cd2e63ad24018d3de)
Reviewed-on: http://git-master/r/106397
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R83d3e5f868fe81d318f38da00a8e62abc403885c

6 years agoARM: tegra: thermal: Call pm register only once
Joshua Primero [Tue, 17 Jul 2012 00:09:42 +0000]
ARM: tegra: thermal: Call pm register only once

Fixed bug where pm register was being called multiple times.

Change-Id: I32f7b10547275e0a9bdad1073f9842589180c0f8
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/116203
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Ra63e894b5cc8224ce5bc18fc01bd01de599eda54

6 years agonet: usb: raw-ip: support more rmnet interfaces
Vinayak Pane [Fri, 29 Jun 2012 23:31:15 +0000]
net: usb: raw-ip: support more rmnet interfaces

New requirement to support upto 5 rmnet interfaces with
raw-ip. Driver will be able to support dynamically multiple
number of interfaces, maximum to 5.

Bug 1006183

Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/112790
(cherry picked from commit 0dde53830d9e21004b2e90c1b997a54c89767fa1)

Change-Id: I8166c448dbfef0391491ffdef9dff2b0e2693d75
Reviewed-on: http://git-master/r/115611
Tested-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: R076aa112c1e68b667e77619687e41086d4824bed

6 years agoarm: tegra: xmm: flashed modem start with hsic_active low
Vinayak Pane [Fri, 29 Jun 2012 20:08:36 +0000]
arm: tegra: xmm: flashed modem start with hsic_active low

Flashed modem should start with hsic_active signal as low.
The hsic register is done at falling edge of ap_wake.

Bug 1006183

Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/112781
(cherry picked from commit 6437d1453d2a7694c2efa183cff135297f9f45e3)

Change-Id: I7bf355088096788b030fd861ef257a9f635c66e7
Reviewed-on: http://git-master/r/115610
Tested-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: R8391f3bcd2ef6da17538e1b35ce8780f2fc7aff7

6 years agousb: serial: baseband: buffer allocations at init
Vinayak Pane [Wed, 21 Mar 2012 22:06:43 +0000]
usb: serial: baseband: buffer allocations at init

The usb transaction buffers are allocated in module init.
In device open, close and disconnect the buffers will not be
freed. Instead they will be reused to avoid allocation failure
in low-mem conditions.

The usb driver register moved to init so that rmmod and
insmod is not required.

Bug 956211

Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/109935
(cherry picked from commit a4e8219a86f80fd06aaaae2c40a657098d5dcfa5)

Change-Id: Id88cfe3b0a75cb2e6f39176b5297f81f4f9e978b
Reviewed-on: http://git-master/r/115609
Tested-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: R1fe1602c604a4339bd845677cd87db4966a1ff31

6 years agoARM: tegra11: Fix simulation build break
Bo Yan [Fri, 27 Jul 2012 18:38:22 +0000]
ARM: tegra11: Fix simulation build break

Since warnings are treated as errors now, variables and functions
for certain configuration, for example, non-simulation build, should
be wrapped in appropriate config macros

Change-Id: I6975d93c16691052e0fb0dd5afa045940d4e880f
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/119066
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rbe333467f8b0bc8fb43d6f3ea6976479cfff7d80

6 years agoARM: tegra: curacao_sim: Enable ashmem service
Lauri Peltonen [Fri, 27 Jul 2012 13:29:16 +0000]
ARM: tegra: curacao_sim: Enable ashmem service

Enable ashmem service which is required on Android.

Change-Id: I11abf0d543260ebd7c91fb3f50c3f685ad0055eb
Reviewed-on: http://git-master/r/118985
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>

Rebase-Id: Rf07fcea47dae9805b4d9873c0450918a059c8bf7

6 years agoARM: tegra: remove duplicate file inclusions
Bitan Biswas [Fri, 27 Jul 2012 10:51:57 +0000]
ARM: tegra: remove duplicate file inclusions

Tegra2 or Tegra3 specific files are included multiple time.
Conditions used when including files are also changing. This
patch cleans the Makefile in above respect.

Change-Id: I9d21db141909ded1f44ed56590ea824d4e0b5de6
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/118943
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Ra663222da1cea8c1db9ecccea78d51c0cc152e88

6 years agotegra: dc: fix build errors
Seshendra Gadagottu [Fri, 27 Jul 2012 00:51:23 +0000]
tegra: dc: fix build errors

Fixed compilation erros with CONFIG_TEGRA_DC enable:
1. Unused variables in dc.c and board-curacao-panel.c
2. Merge issue related to window.c

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I087b6f15b68ef5fa9739c84dc3abc81db7d7b9d2
Reviewed-on: http://git-master/r/118821
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R30d8f6400c888ffe9ae7599568645b07c13c66c0

6 years agoARM: tegra11: dvfs: Update CL-DVFS clock definitions
Alex Frid [Wed, 25 Jul 2012 04:17:00 +0000]
ARM: tegra11: dvfs: Update CL-DVFS clock definitions

- Added i2c fast clock to CL_DVFS clocks
- Limited CL_DVFS parent clocks to PLLP and CLKM only
- Changed device id for CL_DVFS clocks to "cpu_cl_dvfs"

Bug 871124

Change-Id: Ife7883a096aef30c351704c960a153047d14284f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/118471
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Rf93071e2f45e9a5a8361e5c34eaa471c5a53d454

6 years agoARM: tegra11: dvfs: Re-factor CL-DVFS initialization
Alex Frid [Tue, 24 Jul 2012 03:16:14 +0000]
ARM: tegra11: dvfs: Re-factor CL-DVFS initialization

Moved clock binding for CL-DVFS control logic from common code
to SoC-specific DFLL clock initialization.

Instead of indirect access to safe dvfs table through CPU clock,
use direct access pointer in CL-DVFS object. This pointer is still
populated with CPI legacy dvfs reference.

Serialized DFLL initialization with CPU clock operations, since DFLL
is enabled as possible CPU clock source as a result of initialization.

Bug 871124

Change-Id: I90be05c27dcd9380403380f80c849f1d3f5b51e3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/118470
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9c3b40e60caa04bb35f6c9880f8a7812a4ced3d8

6 years agoARM: tegra11: dvfs: Wait for CL_DVFS pending transaction
Alex Frid [Tue, 24 Jul 2012 19:48:03 +0000]
ARM: tegra11: dvfs: Wait for CL_DVFS pending transaction

When disabling CL-DVFS output interface, wait for pending I2C
transaction to complete.

Bug 871124

Change-Id: I7afebc0d218f29bd3efec04cf8dafd9fc767ece7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/118469
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R1c2280c494d66b1bf8f890b1062a10cf017cf1f8

6 years agoARM: tegra11: dvfs: Update CL-DVFS configuration
Alex Frid [Mon, 23 Jul 2012 23:23:39 +0000]
ARM: tegra11: dvfs: Update CL-DVFS configuration

- Account for gain control scale in force value calculation
- Use hs mode rate only as mode support indicator (allow zero
hs master code to be specified)
- Round up rate dividers so that final rate is always below
requested
- Fixed I2C divisor fields definitions

Bug 871124

Change-Id: I41721432e0fa74751342baced7bdda7fcf3a560e
Signed-off-by: Alex Frid <afrid@nvidia.com>

tmp

Change-Id: I6c7eb02622889aae10e11d7a8bccd755008e43ad
Reviewed-on: http://git-master/r/118468
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R3d644e837ff258b0453b00eb8a0f9cbbba4a6aac

6 years agoarm: tegra: usb: removal of WAR for SOF
Suresh Mangipudi [Tue, 24 Jul 2012 06:19:49 +0000]
arm: tegra: usb: removal of WAR for SOF

NULL phy while switching from FS to HS will lead to incorrect line
state and a dropped packet. This issue is fixed in T11x.
Hence remove the WAR.

Bug 969330

Change-Id: I79bb3e311053252839d2c0474d6908b23337f8a4
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/117939
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R678812c3b3bd9d87d977e3383db3e408030d0efe

6 years agoarm: tegra: usb: restore the AP/modem handshaking
Suresh Mangipudi [Tue, 24 Jul 2012 06:17:40 +0000]
arm: tegra: usb: restore the AP/modem handshaking

Restore the AP/modem handshaking functions and clean up the null
phy driver.

Bug 996035

Change-Id: I5a7f4af217b1ae99b56c6b82cdc4417cc20f5ca0
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/117938
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R23c4df2ae460ab0bb2f1bee2d27dc22c99f24321

6 years agoARM: tegra11: Use CPU private timer for LP2
Bo Yan [Wed, 25 Jul 2012 01:32:12 +0000]
ARM: tegra11: Use CPU private timer for LP2

There is no new change for T20 and T30. For SoCs with arch timer
support, arch timer is used for LP2 accounting.

Also removed ARM_SMP_TWD option from Kconfig, it's no longer
necessary and deprecated.

Change-Id: I4292e333df97da296318224e0aa1411330f67900
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/118365
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: Rdcf0ab5bd8ed3cba9d22b624914be5adf79ebe36

6 years agoUSB: gadget: tegra: SW WAR for dTD issue
Krishna Yarlagadda [Mon, 18 Jun 2012 15:09:34 +0000]
USB: gadget: tegra: SW WAR for dTD issue

SW WAR implementation for h/w issue observed on all tegra platforms
Adding a dTD to a Primed Endpoint May Not Get Recognized

TD freeing will be delayed until next TD is completed

Bug 1002166
Bug 989108

(cherry-picked from  http://git-master/r/#change,109562)

Change-Id: I22690a15e2a7e83b4a3812a72242ef8c75f3626e
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/117640
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R6cd4f51cfbe3f8f89b17179e55327628a45a9c68

6 years agoARM: tegra: Increase meminfo array size
Hiro Sugawara [Tue, 24 Jul 2012 18:07:19 +0000]
ARM: tegra: Increase meminfo array size

SOCs supporting full 4GB physical memory need fragmented physical
memory information passed in kernel command line.

Change-Id: I19501a3f03db2467c746384cf1a9e390b1a6742d
Signed-off-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-on: http://git-master/r/118116
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6a30bf4f74415b2c59b417b7dd7a04a32a261f53

6 years agoARM: tegra: New macro name for LP2 timer config
Bo Yan [Tue, 24 Jul 2012 17:03:39 +0000]
ARM: tegra: New macro name for LP2 timer config

The config macro TEGRA_LP2_ARM_TWD was defined when only Cortex-A9
was used in Tegra SoC, but the feature enabled by this configuration
option is not just for Cortex-A9. In fact, any CPU with private timer
can make use of this feature. Therefore, change macro name to a more
generic one "TEGRA_LP2_CPU_TIMER" so it can be used with new CPU
architecture (CortexA15)

Change-Id: I6903dba056c554c72bb8d1416df90145a4043295
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/118099
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

Rebase-Id: R0da9d17d0281e91f5908099579b8eaaf4b01a024

6 years agoARM: tegra11: clock: Add XUSB clocks support
Alex Frid [Tue, 17 Jul 2012 05:56:56 +0000]
ARM: tegra11: clock: Add XUSB clocks support

Change-Id: I754ad041eb884dcf6f8451cb595ab6f9d3c3626c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117735
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R0d26e83c7efd2d74d033084a77623d15920a556d

6 years agoARM: tegra11: clock: Add PLLU secondary outputs
Alex Frid [Sun, 8 Jul 2012 06:57:24 +0000]
ARM: tegra11: clock: Add PLLU secondary outputs

Change-Id: Ifaedbaaff309529d763df82d1c53187c622f9fd5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117734
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rd3402b5d1f4ceabaa26eea99adbdffe54f2a4be5

6 years agoAsoc: tegra: Update ALSA driver
Vijay Mali [Sat, 21 Jul 2012 11:48:49 +0000]
Asoc: tegra: Update ALSA driver

Machine driver change for new platforms.
Fixed clocks in I2S driver for validation on FPGA.
List ALSA driver in kconfig.

Change-Id: If8dcefe2502b28eaa9fe9fbbb7af59bd2ab401a0
Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/117528
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Raf71c105a6e41d9aed17bd36e6542a367e039a6e

6 years agomfd: ricoh583: fix sectionmismatch for ricoh583_i2c_probe
Peter De Schrijver [Thu, 19 Jul 2012 12:48:35 +0000]
mfd: ricoh583: fix sectionmismatch for ricoh583_i2c_probe

ricoh583_i2c_probe calls various functions in the __devinit section. Hence
as a probe function there is no problem to also make it part of that section.

Change-Id: I520f28b72cbae4426eade6a177cd99dfc5f02cd0
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/117055
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Rdd9f61e20333ecc11b9e9e22eeb137b70e19bbf3

6 years agoarm: tegra: usb: Disable the usb WAR for MEM_ALIGNMENT
Suresh Mangipudi [Mon, 9 Jul 2012 04:09:57 +0000]
arm: tegra: usb: Disable the usb WAR for MEM_ALIGNMENT

Disable the USB WAR for T114, as the WAR's are not needed for T114.

Bug 969252

Change-Id: I5a50749dfe0fd6f73fc496c850585181c8b8db21
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/116348
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R37c3e1e2ec4ee206b45562352d44c70f34fc5c0c

6 years agopm: remove early_suspend/late_resume uses
Varun Wadekar [Wed, 25 Jul 2012 04:32:51 +0000]
pm: remove early_suspend/late_resume uses

Android kernel based on kernel v3.4, no longer uses early_suspend and late_resume
states.

Bug 959487

Change-Id: Ib2b50b91ee550824a1082046a37ba25fc98eef84
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rf61a215f5030f4ae6524a7e49c820ff9c98be453

6 years agoARM: tegra11: Save & restore timer registers
Bo Yan [Sat, 16 Jun 2012 07:17:31 +0000]
ARM: tegra11: Save & restore timer registers

Save & restore generic timer registers across cluster switch.

Change-Id: I8a7e131dede5b21259868edf4fff2df8a20c93c2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/116859
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Re84a4517e6d5379d0575af16b69e3f05e208e419

6 years agopm: EDP: adding client registration
Sivaram Nair [Tue, 3 Jul 2012 14:20:58 +0000]
pm: EDP: adding client registration

This patch adds client registration functionality to the existing EDP
framework.

Bug ID: 917926

Change-Id: I8c9fbe3e1d934a6d95745f3c3933df4c1cbea4e7
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/115706
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rd2edd8e79be5515b38ed35a7e9a9c8e135ba002f

6 years agopm: EDP: introducing EDP manager
Sivaram Nair [Tue, 3 Jul 2012 09:16:17 +0000]
pm: EDP: introducing EDP manager

This patch introduces EDP manager - the central piece of software which
dynamically allocates current sourcing capacity to EDP client drivers
for use by their devices.

Bug ID: 917926

Change-Id: I67d72c8c7738edf11ccfc8fdb73e86a02f653967
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/115696
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R26b10ccb0f37928508aa46ae7e5b8c837c9d20d7

6 years agoarm: tegra: curacao: Use DisplayB as default
Seshendra Gadagottu [Thu, 19 Jul 2012 22:06:43 +0000]
arm: tegra: curacao: Use DisplayB as default

Bug 1013917

Change-Id: Ib4d8b0df990c2d06c0d0019dbca0297278ac6d97
Reviewed-on: http://git-master/r/117173
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Recd7082a69d4151279cb250c888c7d9f4f0e1e10

6 years agoARM: tegra11: clock: Update cbus operations
Alex Frid [Sat, 14 Jul 2012 06:07:58 +0000]
ARM: tegra11: clock: Update cbus operations

When several users request the same rate, select the slowest one
as the top user (instead of selecting in order of link list parsing).

Eliminate debugfs floor user from top user selection.

Prevent top user migration if it has the same dvfs table as the
slowest user on the same bus.

Change-Id: I9b0ba04d60b9408cc68a81e1cb59baee7f37fed8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117249
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R5b64afd5a3f6277c6a2ae4268297be045b9b1418

6 years agoARM: tegra11: clock: Replace cbus cross-mutex
Alex Frid [Wed, 11 Jul 2012 06:26:03 +0000]
ARM: tegra11: clock: Replace cbus cross-mutex

Replaced cbus specific cross-mutex with generic cross-clock mutex.

Change-Id: Ifd5612ea2261a9c301270c0a10c80fab3006966b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117248
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R8097f73b4f326d3b7ec00e96b88264b5d67084d4

6 years agoARM: tegra: clock: Add cross-clock locking option
Alex Frid [Wed, 11 Jul 2012 05:59:48 +0000]
ARM: tegra: clock: Add cross-clock locking option

Added an option to serialize clock operations for several clocks
(in addition to individual clock locking). This option may be used,
for example, when moving clocks between virtual buses or to support
clocks with different dvfs tables, but common enable control.

Change-Id: I88b366d4109bdb6ae952385dd84fab392715ac10
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117247
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb5183f53b71e240234cda950cb6bddf07437c4db

6 years agoARM: tegra11: clock: Add missed PERIPH_ON_APB attributes
Alex Frid [Fri, 13 Jul 2012 03:34:10 +0000]
ARM: tegra11: clock: Add missed PERIPH_ON_APB attributes

Change-Id: I0d41e6a83dd2499f843a452051c2f1ff78c75be0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117246
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R8cf4e7c0a435552cce2833e2f163ec707408511b

6 years agoARM: tegar11: clock: Fix common initialization table
Alex Frid [Fri, 13 Jul 2012 01:50:47 +0000]
ARM: tegar11: clock: Fix common initialization table

Fixed merge artifacts.

Change-Id: I610559303afb972e52f10b04897c265cc0f8a36a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117245
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R279a540a02be14ded064c31d8dafaf58012b9aa1

6 years agoARM: tegra11: clock: Add ADX, AMX, TRACE and SOC_THERM clocks
Alex Frid [Fri, 13 Jul 2012 03:06:21 +0000]
ARM: tegra11: clock: Add ADX, AMX, TRACE and SOC_THERM clocks

Change-Id: Ifc41ee0b36b24dbb6e5029dde1b047d3c47ce96c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/117244
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rfc0fd3839f1044620b98083a675eb545f797cdc8

6 years agoARM: tegra: Use GIC IRQ/FIQ as LP2 wake event
Bo Yan [Thu, 19 Jul 2012 16:24:44 +0000]
ARM: tegra: Use GIC IRQ/FIQ as LP2 wake event

Whenever possible, GIC IRQ/FIQ should be used to wake up CPUs in LP2,
this can be done by setting up wake-up condition as WAIT-FOR-EVENT
and event sources as GIC IRQ/FIQ.

This is supported coincidentally in all SoCs with symmetric CPU power
gating.

Change-Id: I7fafee5218b5db386fc993a064c53295c9c7e60b
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/117111
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rae70d0555c60a9fd95b615309701d3edb207076c

6 years agoARM: tegra11: Disable cache before flushing
Bo Yan [Tue, 17 Jul 2012 20:50:55 +0000]
ARM: tegra11: Disable cache before flushing

This is needed before power gating Cortex A15 processor.

Change-Id: Ib6eb2dd78ea0b34c978386105a172f0c0eea8a5c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/116549
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R48b996d6971c9f43900412bf306c52f916f0ae8c

6 years agoARM: Enable LOCAL_TIMERS for ARCH timer support
Bo Yan [Tue, 17 Jul 2012 06:30:41 +0000]
ARM: Enable LOCAL_TIMERS for ARCH timer support

Just like local timer in A9, arch timer in A15 is for local CPU too.
Thus local timer support is needed even when arch timer is in system
, however, arch timer can't co-exist with SMP TWD.

Change-Id: Ibcdc73eed36035c6f5b3560d632226a74b6bc9e7
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/116350
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rfbc8085f86ebb189be9cbfea3143267e78524fe0

6 years agoARM: tegra11: Set up tegra timer as clock source
Bo Yan [Tue, 17 Jul 2012 06:23:45 +0000]
ARM: tegra11: Set up tegra timer as clock source

architected timer is set up for boot cpu in percpu_timer_setup, this
is quite late during system boot. Before it's done, it is necessary
to register clockevents using tegra timer.

The same thing is also true for ARM twd timer, which is already taken
care of in the code. This change merely enables the same code for
arch timer.

Change-Id: I2ffd1ffa9be8b71902cb6151462d5b6cb641a355
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/116349
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R279b90cf0a18fcb3d126b12056c76241a558e8ef

6 years agoRevert "ARM: tegra: make tegra_cpu_reset_handler_enable() __init"
Varun Wadekar [Wed, 18 Jul 2012 12:31:29 +0000]
Revert "ARM: tegra: make tegra_cpu_reset_handler_enable() __init"

This reverts commit c1389ce1e02c1e1f617d7cf70852ad5d9f9ef355 as it breaks
LP0 resume. Clearly, this was not tested before pushing upstream.

Change-Id: Iaf0a40f5c290c6f73c84b5d5bbba33d70c373a49
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R6aed1954d5d59ae5ff903b691ec0cf8784bbe5d3

6 years agoARM: tegra: iovmm: Fix build error w/o CONFIG_IOVMM
Hiroshi DOYU [Thu, 12 Jul 2012 12:11:20 +0000]
ARM: tegra: iovmm: Fix build error w/o CONFIG_IOVMM

Update function prototype along with:

  commit 6cbf4c7465b7b70936cb422b509da0ad0829c306
  ARM: tegra: iovmm: Allow alloc_client to take struct device

Change-Id: I11d173429413ab268f6ab789d90f321e3d33de2c
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/115391
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rf1686d7846eca009dcd4cff7d0a92750ed88b70b

6 years agoARM: tegra: iovmm: Replace IOVMM backend with IOMMU
Hiroshi DOYU [Tue, 10 Jul 2012 06:32:42 +0000]
ARM: tegra: iovmm: Replace IOVMM backend with IOMMU

Replace IOVMM backend functions with the standard IOMMU API
ones. Instead of modifying the actual C-files in drivers, MACROs in
iovmm.h does the all work.

Change-Id: I27dc893555ca1495588852261e3ba1e3e5619764
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/114460
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R8ab33aa5fe38a6618b52208a31db442b0e584f28

6 years agocpufreq: protect cpufreq_stats_free_table with spinlock
Peter Boonstoppel [Fri, 2 Mar 2012 00:04:27 +0000]
cpufreq: protect cpufreq_stats_free_table with spinlock

Prevents crash on cpufreq_stat_notifier_trans when cpufreq_stats_table
has been freed due to a core being hotplugged out.

Bug 948348

Change-Id: I2640a9a23c9a79cad8c76bfefd243a07162d2004
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
(cherry picked from commit 03070a4b0b8eb74825c99c6bbfb108ddb36a041c)
Reviewed-on: http://git-master/r/114248
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rc12de609c5e38ab486a36b7466585f4a2840c21a

6 years agoARM: tegra: p1852: Dual-display support for all SKUs
Dongfang Shi [Thu, 3 May 2012 23:40:49 +0000]
ARM: tegra: p1852: Dual-display support for all SKUs

Ported Peter's original change 86413 to main.

board-p1852-panel.c:
Add support for primary and secondary LVDS displays, and secondary HDMI display.

board-p1852-pinmux.c:
Add configuration for HDMI and LVDS

board-p1852.c:
board-p1852.h:
Support for determining which p1852 sku is in use

hdmi.c:If no edid retrieved, but there's a hardwired mode, enable it
(used to support HDMI->LVDS output on p1852 sku 2)

devices.c:added secondary display data.

Bug 977859
Bug 994011

Change-Id: Ide8fb6bf7dd873b1d50269fb98d7c1687e4d9073
Signed-off-by: Dongfang Shi <dshi@nvidia.com>
Reviewed-on: http://git-master/r/100438
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R37e7f78eb72c8c68b19a195bf68144ca57e985f9

6 years agopower: max17048: fix power polling at resume
Chandler Zhang [Fri, 13 Jul 2012 09:01:38 +0000]
power: max17048: fix power polling at resume

The state of charing is not correct because of the 1 sec delay.
Remove the delay to fix the issue.

Bug 1016683

Change-Id: I389970e32d34578bb1ec1f2019d78145f250a673
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/115632
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R8ebb53cf60901ac805361ba850f27d2bb7a3122a

6 years agoarm: tegra: usb_phy: fix hsic suspend issue on xmm
Vinayak Pane [Tue, 12 Jun 2012 01:08:14 +0000]
arm: tegra: usb_phy: fix hsic suspend issue on xmm

XMM modem fails at auto-suspend on hsic. Fixing this issue
by enabling PMC sleepwalk code conditionally and only at
phy-on and phy-off routines.

Bug 991709

Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/109324
(cherry picked from commit 100f818a16ce97411a98ddb0e2c5c9e73a9e654a)

Change-Id: If6f92b8b36f856fa633cb411ac20dbe6e862890c
Reviewed-on: http://git-master/r/115612
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rc44137939cb7ded2b0988e3ef66434c5c160eeb1

6 years agoarm: tegra: sd: enable sd dpd
Wen Yi [Thu, 21 Jun 2012 04:42:13 +0000]
arm: tegra: sd: enable sd dpd

This is a WAR solution that allows for the turning on
SD DPD feature.

The original issue is that enabling SD DPD immediately after device comes
out of LP0 causes ULPI disconnect. The root cause of that is
not known.

The WAR is to delay the enabling of SD DPD for 100ms after
device comes out of LP0.

Bug 929628

Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4
Signed-off-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9)
Reviewed-on: http://git-master/r/113392
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rd4728fda7b23fa349f48b19c054ed412bf10e089

6 years agoRevert "arm: tegra: power: disable all sd dpd"
Bitan Biswas [Tue, 24 Jan 2012 07:52:23 +0000]
Revert "arm: tegra: power: disable all sd dpd"

This reverts commit 8924926cdb77c6ab270867d4caef7a8cdacd11f2.

Bug 924452
Bug 929628

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
(cherry picked from commit 142b34993404c853579864f7b7b4f320fb92a715)

Change-Id: I9d49703799e32d410beba18938e94e4b641eea6f
(cherry picked from commit 8de60b7a832bfbbf09e75def756379dbb2d14c3e)
Reviewed-on: http://git-master/r/113387
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R5ad33e04ba72e5408bf553685b1a6efead1e2bf0

6 years agoarm: tegra: usb_phy: utmip remote wakeup issue
Venu Byravarasu [Fri, 29 Jun 2012 06:28:51 +0000]
arm: tegra: usb_phy: utmip remote wakeup issue

Do not clear sleep walk pointer for utmip port after remote
wakeup is detected. This should be cleared after control
is given to USB master from PMC.

Bug 999208

Change-Id: I9f498521989c6421f0043dc1b4364591d4907423
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
(cherry picked from commit e4dbecfe031cbacd4f22bbbcdf971ab11ad81ee8)
Reviewed-on: http://git-master/r/112938
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf1239ac22f089f86db0b85ae4916998e3bac5f6a

6 years agoARM: tegra: clock: Dynamically re-lock memory pll
Alex Frid [Sun, 24 Jun 2012 01:22:13 +0000]
ARM: tegra: clock: Dynamically re-lock memory pll

So far Tegra3 EMC DFS allowed only scaling rates that can be divided
down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM
is always running at maximum SDRAM rate set at boot time, while PLLP
rate 408MHz is fixed across all Tegra3 platforms.

This commit implements dynamic re-locking of PLLM at run time. Now
memory pll can lock either at boot rate or additional auxiliary rate
that is selected as follows: auxiliary PLLM rate must be present in
EMC DFS table, it must exactly match one of the rate steps for Tegra3
graphics bus with PLLC clock source (cbus), and must not be a proper
factor of boot PLLM rate or PLLP fixed rate.

When switching PLLM between boot and auxiliary rate, PLLC is used as
backup memory pll, and during this time cbus is locked at auxiliary
rate. In addition system bus is forced to temporarily use PLLP as
a clock source (this is necessary as sbus main clock source is PLLM
secondary divider PLLM_OUT1).

Limitations:
- only one auxiliary rate is supported, and it should be below PLLM
boot rate, but above half of boot rate
- dynamic re-lock is allowed only on LPDDR2 platforms
- no clock other than EMC and system bus could use PLLM as a source;
so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be
selected, and VI clock (not covered by PLLM restricted configuration)
must be moved to PLLP.

Bug 1005576

Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/111438
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a)
Reviewed-on: http://git-master/r/114760
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R2f1dd4c055732506fcb695d6aba37ddd3cedc832

6 years agoARM: tegra: clock: Increase boost_up_threshold for AVP clock
Vandana Salve [Tue, 10 Jul 2012 15:33:24 +0000]
ARM: tegra: clock: Increase boost_up_threshold for AVP clock

Increase the boost_up_threshold to 85 for ULP audio

bug 1009849

Change-Id: I4b1b746f445f5c2804befa52ae95c69b6b467083
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/114620
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: R8f229d91a12d145e87531c3fdfefccc7d228bbb7

6 years agocpufreq: Protected access of policy attribute
Puneet Saxena [Thu, 7 Jun 2012 13:49:59 +0000]
cpufreq: Protected access of policy attribute

It takes read RW semaphore to access policy governor

bug 997731

Change-Id: Ibdc3dd54cf6076c0fef4bc58f144e4bcb4631d76
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/107079
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R24af1f7d5e3c847ff57b1cbc2b2917591df2b0d5

6 years agobluesleep: stop/start based on HCI_DEV_REG/HCI_DEV_UNREG events
Nagarjuna Kristam [Wed, 11 Jul 2012 11:19:24 +0000]
bluesleep: stop/start based on HCI_DEV_REG/HCI_DEV_UNREG events

when BT is turned off HCI_DEV_DOWN event is received and bluesleep
protocol is stopped. On bluesleep stop, EXT_WAKE gpio will be set to
default high level. This condition does not allow BT chip to enter
low power mode. So, start and stop bluesleep based on HCI_DEV_REG
and HCI_DEV_UNREG events instead of HCI_DEV_UP and HCI_DEV_DOWN.

Also, enable and disable host wake functionality based on HCI_DEV_UP and
HCI_DEV_DOWN events, as these events indicate BT turn ON and OFF

Bug 1014590

Change-Id: I3929c1328ac024eb080359283107dabf3712e9ea
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/114984
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rf96a5abebd354ff94960580be2da304ef199f671

6 years agoARM: tegra: clock: Allow Tegra3 PLLM rate change
Alex Frid [Sun, 24 Jun 2012 06:50:54 +0000]
ARM: tegra: clock: Allow Tegra3 PLLM rate change

Allowed Tegra3 memory PLLM rate change, provided it is disabled.

Since PLLM can deviate from boot configuration now, and on Tegra3 it
is controlled by PMC override registers (not CAR module registers):

- Re-factored PLLM initialization, resume, and set rate operations
accordingly (enable and disable ops already used PMC override).

- Made sure that boot configuration is restored on entry to LP0 to
match memory timing saved in scratch registers.

Bug 1005576

Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/110937
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8)
Reviewed-on: http://git-master/r/114759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R3e931f8d56cb927dd8103386f0af36e7362a7843

6 years agoARM: tegra: clock: Record EMC clock source rate
Alex Frid [Fri, 22 Jun 2012 21:13:41 +0000]
ARM: tegra: clock: Record EMC clock source rate

On Tegra3 added source rate to EMC clock source selection structure,
and re-factored EMC DVFS initialization accordingly.

Bug 1005576

Change-Id: I155e982bef2431a76cf5e5085070d4e654a7b49b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/110935
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit bf52c26c532a9ebabc4fc8a1fb5fc9d88be85e66)
Reviewed-on: http://git-master/r/114758
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R5708811872364de455b44e99c49b9284415428f4

6 years agoARM: tegra: clock: Record shared bus backup rate
Alex Frid [Fri, 22 Jun 2012 19:31:44 +0000]
ARM: tegra: clock: Record shared bus backup rate

Added shared bus backup rate entry to clock descriptor; initialized
it for cbus (currently the only shared bus with backup source).

Bug 1005576

Change-Id: I8124aa87f1dc307e42417da8f78797cfaf71e5dc
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/110934
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit bc5ed688929c3c0ca920b5e9663cf9c6fb85c00f)
Reviewed-on: http://git-master/r/114757
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R8581697239f03d3cbbbcffdac0749914badfa445

6 years agoasoc: codecs: max98088: Headset Detection
Nikesh Oswal [Fri, 29 Jun 2012 10:56:33 +0000]
asoc: codecs: max98088: Headset Detection

Add code for headset detection according to that
state transitions mentioned for JKSNS field in the
max98088 codec datasheet

Bug: 110529
Bug: 1008246

Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/112127
(cherry picked from commit 12a2259e0e9cf7da4bf64bad2a97c32cec41477c)

Change-Id: I7d45b210dd02f181e71a08d9b3de7cff109dd88b
Reviewed-on: http://git-master/r/114445
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R73c78bd2cebdc87b60e809023bd88f88ae6f6f5e

6 years agoasoc: tegra: Change HW disabling dequence and I2S clock parent
Nikesh Oswal [Fri, 22 Jun 2012 07:24:52 +0000]
asoc: tegra: Change HW disabling dequence and I2S clock parent

Change HW disabling dequence and I2S clock parent in slave mode
for voice call use-case

Bug: 1005176
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/110529
(cherry picked from commit 4b138cdeb3374575bde9f49d0c644faa91ced68f)

Change-Id: Ia037ed5ef45d38972c3e1e1a78b4b7b7f39d8f72
Reviewed-on: http://git-master/r/114444
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R02ea5277da8b57fd405b640fc037ff72cc84dbca

6 years agoARM: tegra: iovmm: Allow alloc_client to take struct device
Hiroshi DOYU [Mon, 9 Jul 2012 08:24:57 +0000]
ARM: tegra: iovmm: Allow alloc_client to take struct device

Allow tegra_iovmm_alloc_client() to take struct device * instead of
const char *name w/ __tegra_iovmm_alloc_client(). This is necessary to
support IOVMM and IOMMU simultaneously.

Change-Id: I18df5001bfe0ece8f9f15b636eb11def9f228dfb
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/114215
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rf659abbce9a59b97fa312311d4861e32745283af

6 years agoARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GART
Vandana Salve [Tue, 13 Mar 2012 08:41:41 +0000]
ARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GART

Replace TEGRA_{SMMU,GART}_{BASE,SIZE} with TEGRA_IOMMU_{BASE,SIZE} to
deal with SMMU/GART in unified manner.

This is necessary for DMA mapping API to pass the appropriate IOMMU
address for SMMU and GART in the same code in nvmap.

[Hiroshi Doyu: Squash nvmap parts into "nvmap: API conversion" patch.]

Change-Id: I75429dd56554f880f144c375d2c20e8e8948ceee
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/114212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rb092d8bc2ebc9e1f599ecb4f299220bb9a1ec996

6 years agoARM: tegra: Remove duplicate clock inits
Sai Charan Gurrappadi [Thu, 5 Jul 2012 17:59:01 +0000]
ARM: tegra: Remove duplicate clock inits

Change-Id: I80c384d1aa4b1e45a4542acbde6b904f4a014aff
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/113679
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R4c0677ca0ce4eedfb722ee88660b4c9cf718c7b4

6 years agodrivers: misc: fixed therm estimator bug
Joshua Primero [Wed, 4 Jul 2012 02:39:13 +0000]
drivers: misc: fixed therm estimator bug

Fixed hi and lo limit bug in thermal estimator driver.

bug 1007726

Change-Id: I2be90ca7d875dbed34004b83f070fb5cbd8bc467
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/113564
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: Rdab5eb466c29286b3feceff123e2362884c265ed

6 years agoARM: tegra: thermal: fixed some skin thermal bugs
Joshua Primero [Wed, 4 Jul 2012 02:37:55 +0000]
ARM: tegra: thermal: fixed some skin thermal bugs

Fixed bug where skin cooling device is being bound to nct
device instead of skin thermal device.

bug 1007726

Change-Id: Ia6316735da8895fd4f4c20c0a76cd6796dafdf9b
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/113563
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Ra67416f841058c494b4ce0e1e4435dc0f80fbe61