5 years agoarm: tegra: Fix wrong parameter to boot error message
Hiro Sugawara [Fri, 29 Apr 2011 18:59:37 +0000]
arm: tegra: Fix wrong parameter to boot error message

This makes up disregarded objection in change 29149.

Original-Change-Id: If8c83471719c743e2a74f4fb0ee8c34240498b7b
Reviewed-on: http://git-master/r/29863
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R96ba60f7918ff09614ac93e5ea024af51afc11ea

5 years agocrypto: tegra-aes: dual core support
Sanjay Singh Rawat [Thu, 28 Apr 2011 13:25:57 +0000]
crypto: tegra-aes: dual core support

* add bsea engine support for encryption and decryption
* add arbitration semaphore id for bsea

Bug 803932

Original change: http://git-master/r/#change,29672
(cherry picked from commit 0008cdb0f38d0cd0c074671fc067c4321f340b06)

Original-Change-Id: I59fcaab29c47a8b42e7470b30486851cfe90848f
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/30190
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rb63b593aa4fe4b4d4f3607ac9471ae7e7372407a

5 years agoARM: tegra: powergate: Add hot reset sequence for powergate
Jin Qian [Thu, 21 Apr 2011 19:55:47 +0000]
ARM: tegra: powergate: Add hot reset sequence for powergate

Original-Change-Id: I0e37b788c666ae99f46e7e6995c3700b0b23d412
Reviewed-on: http://git-master/r/29901
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R24afa8e7f33265722cee139f37ad53774d1dcb96

5 years agoARM: tegra: Add EMC to DDR clock ratio config option
Alex Frid [Wed, 4 May 2011 05:34:22 +0000]
ARM: tegra: Add EMC to DDR clock ratio config option

Original-Change-Id: Ib5b7c99b483785b84ece0662ae5e9e58227d257f
Reviewed-on: http://git-master/r/30309
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>

Rebase-Id: Rbe52fcf6868d3b19a5c42d7074f977f55c8c9cae

5 years agoARM: tegra: clocks: make pclk div dynamic
Prashant Gaikwad [Thu, 28 Apr 2011 10:18:44 +0000]
ARM: tegra: clocks: make pclk div dynamic

dynamic changing of pclk divider to follow APB clock minimum
frequency requirements with respect to sclk frequency.

Bug 819796

Original-Change-Id: Id6d4f9321fe3d49922ace9b50cb6e5114f63b9b5
Reviewed-on: http://git-master/r/29643
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb722438f9370900d4536ef9e09a6bcad29521ce0

5 years agoARM: tegra: clock: Remove "sole parent" requirement
Alex Frid [Tue, 26 Apr 2011 04:21:30 +0000]
ARM: tegra: clock: Remove "sole parent" requirement

During dvfs initialization, change propagation of sleeping attribute
from "current_parent-to-child" to "possible_parent-to-child". This would
guarantee that any non-sleeping clock has only non-sleeping parents, and
it is no longer required for sleeping clock to be a sole parent of all
its children.

Original-Change-Id: I11110f6cb9c538c1e71bf00195c3f49dd09ea1f7
Reviewed-on: http://git-master/r/29706
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3916f7d951cc3ea8b80d9e22a8200f45ec54fa3d

5 years agoARM: tegra: clock: Show cansleep attribute in clock tree
Alex Frid [Tue, 26 Apr 2011 00:57:36 +0000]
ARM: tegra: clock: Show cansleep attribute in clock tree

Original-Change-Id: Iff900aa5b69329696bcd250c824e0a191f6f6299
Reviewed-on: http://git-master/r/29705
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc93662daa81d9cf5ba656b81958f95241c259b47

5 years agoARM: tegra: clock: Clip Tegra3 CPU mode rate limits
Alex Frid [Sat, 23 Apr 2011 02:41:41 +0000]
ARM: tegra: clock: Clip Tegra3 CPU mode rate limits

Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate
are clipped to the entries in cpufreq scaling table.

Original-Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07
Reviewed-on: http://git-master/r/29703
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R99b548e992c80e4850e6d7f9443db8f7d7134956

5 years agoARM: tegra: power: Check Tegra3 auto-hotplug speed balance
Alex Frid [Fri, 22 Apr 2011 04:33:12 +0000]
ARM: tegra: power: Check Tegra3 auto-hotplug speed balance

When current CPU complex frequency is above target range:
- bring new core on-line only if cpufreq governor requests for
all already on-lined CPUs are above 50% of current CPU frequency
- off-line one core (despite high pick request) if cpufreq
governor requests for at least 2 on-lined CPUs are below 25% of
current CPU frequency
- do nothing if neither of the above conditions is true

Original-Change-Id: I77e1bd543a8fadd51974f7d574f256a6e7e2979a
Reviewed-on: http://git-master/r/29702
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc5c717454d1e09ca97ccc79fff60cb33fcf854e9

5 years agoarm: tegra3: Updating pinmux table based on TRM
Laxman Dewangan [Mon, 25 Apr 2011 06:44:31 +0000]
arm: tegra3: Updating pinmux table based on TRM

On tegra3 TRM, some of the pin mux option for a given
pin group is not recommended and so not exposed in the
TRM reference table.

Updating the pinmux table accordingly. The non-recommended
pin option is set as TEGRA_MUX_INVALID.

bug 817099

Original-Change-Id: I572ee84912fe065a73e59d4f9ba0ce01223ead85
Reviewed-on: http://git-master/r/29626
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R88ad8a84c4516c8692b9266d6c073f20e35b420e

5 years agoARM: tegra: correcting vde resource end field
Sanjay Singh Rawat [Mon, 25 Apr 2011 09:57:25 +0000]
ARM: tegra: correcting vde resource end field

Original-Change-Id: I3b71ff1a57093f7e4bba311cb5632c200a80666c
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28651
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R5987a45cb62bfb22861438539125e71a4788e8a1

5 years agoARM: tegra: Decode optional chip-private feature string in cmd line
Hiro Sugawara [Thu, 14 Apr 2011 17:41:06 +0000]
ARM: tegra: Decode optional chip-private feature string in cmd line

ap20 needs to distinguish between A03 and A03p revisions.

Original-Change-Id: I726d45f5ea3c5283ae11057f01c86038eb6c2872
Reviewed-on: http://git-master/r/27777
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If14b6330ccd8bb6420e0c9118291414cc383b94d

Rebase-Id: R60cae4b7b2061deeedd0cabaa6bf95f2f379514a

5 years agoARM: tegra: power: Update Tegra3 CPU auto-hotplug
Alex Frid [Wed, 20 Apr 2011 06:38:46 +0000]
ARM: tegra: power: Update Tegra3 CPU auto-hotplug

- taking CPU core off-line: selected CPU with minimum load
- switching from ULP to G CPU mode: set CPU clock to cpufreq
target rate after the mode switch is completed

Original-Change-Id: I9bf4d0f4b48c262cf678c603aac02043dd602674
Reviewed-on: http://git-master/r/28420
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I5a19be79dd8f8fe788637870a22cd34dcfea150e

Rebase-Id: Re264ec676c5c2103f7738c9eab5f4e11a4344975

5 years agoARM: tegra: power: Set minimum LP2 target residency
Alex Frid [Tue, 19 Apr 2011 04:35:58 +0000]
ARM: tegra: power: Set minimum LP2 target residency

Added board level tuning parameter to specify minimum LP2 residency
time (previous policy allows down to zero residency targets limited
only by LP2 exit latency).

Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22
Reviewed-on: http://git-master/r/28162
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6

Rebase-Id: Rcf9efce3dd037b0a7ca13a9c342f884fac38d654

5 years agoARM: tegra: Use proper type for physical addresses
Scott Williams [Wed, 13 Apr 2011 00:47:52 +0000]
ARM: tegra: Use proper type for physical addresses

Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496
Reviewed-on: http://git-master/r/27559
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1

Rebase-Id: R070df1711ad7b02dd9dbe17edad01e13c91a3615

5 years agoARM: tegra: timer: Clean up Tegra2 timer code
Scott Williams [Tue, 12 Apr 2011 00:10:54 +0000]
ARM: tegra: timer: Clean up Tegra2 timer code

Remove extraneous code.
Clean up timer register addresses.

Original-Change-Id: I459e5b1aa7062d8454b5c064354fe71ef3a737d4
Reviewed-on: http://git-master/r/27444
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I353886d350bb8389aa12dc2da03b3a3c5a0cc7ca

Rebase-Id: R39fb8dac614aeefb1d337c4b5d817038b4ea65d6

5 years agoARM: tegra: Fix sizeATaddr display order in error message.
Hiro Sugawara [Fri, 8 Apr 2011 20:21:02 +0000]
ARM: tegra: Fix sizeATaddr display order in error message.

Also move a local variable into a closed block.

Original-Change-Id: Ifca24c640c917d3a86c27da526c482ec0b6abeb2
Reviewed-on: http://git-master/r/27241
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Original-Change-Id: I24c57262a0e6f2b32c11e4786cc5a56b9ffe866b

Rebase-Id: R8f93d4507562402fd3394276d9745738706141f3

5 years agoARM: tegra: power: Re-initialize Tegra3 EMC after LP0
Alex Frid [Wed, 6 Apr 2011 03:24:36 +0000]
ARM: tegra: power: Re-initialize Tegra3 EMC after LP0

Since EMC frequency is not restored after exit from LP0, re-initialize
EMC clock with the new warm boot configuration, and make sure that the
1st after LP0 clock change does not use stale timing cache.

Skip Tegra2 specific EMC restoration on Tegra3 platforms.

Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2
Reviewed-on: http://git-master/r/26807
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406

Rebase-Id: Rb3fcd60c0c674e10d41d4cdc4d8e53a6e124a5bf

5 years agoARM: tegra: power: Add CPU EDP support
Alex Frid [Thu, 7 Apr 2011 03:43:55 +0000]
ARM: tegra: power: Add CPU EDP support

CPU electrical design point (EDP) limits specify maximum CPU frequency
depending on number of CPU cores on-line, and chip temperature. This
commit added initial edp governor to cpufreq driver. Governor is aware
of CPU departure/arrival, but temperature dependency is yet to be added.
Therefore CPU EDP support is left disabled for now.

Original-Change-Id: Ia875aa6904df7ec25ac98863d59a173703034241
Reviewed-on: http://git-master/r/26982
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iae2e9d47c2d3fd4cb32104adbad4f4b26c46064c

Rebase-Id: Rde24788e86558e1c21b18a1857a8b52220ba8e2a

5 years agoARM: tegra: power: add partition power check before suspend
Jin Qian [Wed, 16 Mar 2011 19:30:41 +0000]
ARM: tegra: power: add partition power check before suspend

Original-Change-Id: Ie4b29d1119bc2f640891525ab781c8de1bf64ddf
Reviewed-on: http://git-master/r/23215
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Idc616485ecdb9e7c39728409d91a511e1de79e05

Rebase-Id: Rd61725b233749ea76467686439b92ac22b65f424

5 years agoARM: tegra: clock: Modify EMC maximum rate settings
Alex Frid [Tue, 5 Apr 2011 23:45:05 +0000]
ARM: tegra: clock: Modify EMC maximum rate settings

On A01 Tegra3 chip EMC rate may not reach full PLLM range - set
maximum EMC rate equal to boot rate. Use PLLM frequency as EMC
rate limit for A02+ chips.

Original-Change-Id: I0b901a29d628362b09f2a3d0ce908b4019804cfd
Reviewed-on: http://git-master/r/26786
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I741fcfca646ba0a2a8732dbccaf7a2642d839809

Rebase-Id: R9b5913cccecc96221c1541887e6e3b03a8f1316a

5 years agoARM: tegra: clock: Updated EMC clock change procedure
Alex Frid [Fri, 1 Apr 2011 06:18:11 +0000]
ARM: tegra: clock: Updated EMC clock change procedure

Original-Change-Id: I0fad4b8d931b92c8dbbdd3b6ce7dd63b42c6464f
Reviewed-on: http://git-master/r/25177
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I109a5cff6b53cfea4b48b20c9114aa4a1c02f1d8

Rebase-Id: R6416c2a2c2c1dc1fd8619842b91fea24ae10b675

5 years agoARM: tegra: irqs.h simplification
Scott Williams [Wed, 6 Apr 2011 00:53:15 +0000]
ARM: tegra: irqs.h simplification

Original-Change-Id: I8f344d368a501c7bb3c0eba6cecabd7c48a6c9a2

Rebase-Id: Rcd1b8d194e030c536d7395d8e406385f58e77489

5 years agoarm: tegra: iovmm: Move SMMU window to bottom 1GB for AVP
Hiro Sugawara [Thu, 17 Mar 2011 18:19:29 +0000]
arm: tegra: iovmm: Move SMMU window to bottom 1GB for AVP

Tegra3 A01 continues to use the high address range.
Tegra3 A02 (and after) uses the bottom 1GB.
The new AHB register bit access has no effect to Tegra3 A01.

Original-Change-Id: I90cedbb22d9aae4307908750ebeb03bef639945c
Reviewed-on: http://git-master/r/23379
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I33253f8ae32c416a9d19694e87380dbae94c2f68

Rebase-Id: Rf2d058998ea09fcbe44fe3c61493a46938505c0b

5 years agoARM: tegra: chipid: Parse and save Tegra chip ID passed by fastboot
Hiro Sugawara [Mon, 4 Apr 2011 22:53:35 +0000]
ARM: tegra: chipid: Parse and save Tegra chip ID passed by fastboot

Original-Change-Id: Ibb00d64820cc81b6af08c4ac7266d2df94bd6a1e
Reviewed-on: http://git-master/r/26631
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Idc50a6f9891bc61f19e1f282480519ffccf11ad4

Rebase-Id: R787474379574ab1e081e49528af749709856b682

5 years ago(PARTIAL) ARM: tegra: power: Disallow LP2 when regulator is updating
Diwakar Tundlam [Mon, 4 Apr 2011 22:42:46 +0000]
(PARTIAL) ARM: tegra: power: Disallow LP2 when regulator is updating

Original-Change-Id: I8012de82dfd4c47628fb202ba5ba98f3d199035f
Reviewed-on: http://git-master/r/26630
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I17065422392d01509d2a745f2cb5d188450e32cb

Rebase-Id: R6f46d3aca8a65798d1fcb7e1f60461c32ae1f99d

5 years agoARM: tegra: power: Split Tegra3 CPU-G and CPU-LP dvfs
Alex Frid [Sun, 3 Apr 2011 01:15:45 +0000]
ARM: tegra: power: Split Tegra3 CPU-G and CPU-LP dvfs

On Tegra3 CPU power is supplied by different rails in G-mode (VDD_CPU)
and LP mode (VDD_CORE) - updated dvfs dependencies respectively.

Original-Change-Id: Ifae8ae501b227a44e46ce1577bcd532e2e778322
Reviewed-on: http://git-master/r/25200
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I96e6cb7e3dcdf8514714d2900d8f947b6438c95f

Rebase-Id: R4d16a0002c701f6ee2f0f8c0f66c5313e4546d53

5 years agoARM: tegra: clock: Add clock time on statistic
Alex Frid [Sat, 2 Apr 2011 04:25:40 +0000]
ARM: tegra: clock: Add clock time on statistic

Original-Change-Id: I361e00ef84ce4ca9a9c6d7340de2d095fc67a208
Reviewed-on: http://git-master/r/25180
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If382fc3b5d2ca678df8a9319a06bae967fc3c658

Rebase-Id: Ref4182db3e144202dd2df2047a3683e478e070fc

5 years agoARM: tegra: power: Modify auto-hotplug locking
Alex Frid [Thu, 31 Mar 2011 03:31:30 +0000]
ARM: tegra: power: Modify auto-hotplug locking

Use cpufreq (cpu DFS) mutex for auto-hotplug (instead of a separate
one) to serialize cpu frequency scaling, hotplug, and CPU mode switch
operations.

Original-Change-Id: I7ea865894d1676c865294ab31a903248d9437534
Reviewed-on: http://git-master/r/24893
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I906a23561c1567079a41590a30b29b3d52fa5de8

Rebase-Id: R5d16154c91b41fd02f2a50af7ec6868a7958dc13

5 years agoARM: tegra: clock: Add Tegra3 CPU clock round rate operation
Alex Frid [Thu, 31 Mar 2011 01:02:13 +0000]
ARM: tegra: clock: Add Tegra3 CPU clock round rate operation

Original-Change-Id: I9e10c8d4ed074f915769ae7c77d915d6b021e2c9
Reviewed-on: http://git-master/r/24892
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23820e1557d304d7a99417b99afaeb4a36c9d18f

Rebase-Id: Re1b1e4f589376f52c1e9cf903ceaee7efe798ba1

5 years agoarm: tegra: TEGRA_AVP_KERNEL_ON_SMMU depends on TEGRA_IOVMM_SMMU
Hiro Sugawara [Fri, 1 Apr 2011 21:04:35 +0000]
arm: tegra: TEGRA_AVP_KERNEL_ON_SMMU depends on TEGRA_IOVMM_SMMU

Original-Change-Id: Id8a54910a792509ec8c9c163a15dc2d4cc19a9e9
Reviewed-on: http://git-master/r/25140
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I648e4e48c2b8c698ce997a966c14f47a50ba23bb

Rebase-Id: Ref275c4058dae6c064fe41e850ec61f019b27724

5 years agoARM: tegra: Specify Tegra DRAM Base/Size
Scott Williams [Tue, 29 Mar 2011 19:32:43 +0000]
ARM: tegra: Specify Tegra DRAM Base/Size

Original-Change-Id: Icb70299bafebbec75614dccbc09833dc5681b402

Rebase-Id: R1534871807017115032a8c5d246a679858cc5d5b

5 years agoARM: tegra: Update Tegra3 io memory mapping
Scott Williams [Tue, 29 Mar 2011 19:29:46 +0000]
ARM: tegra: Update Tegra3 io memory mapping

Original-Change-Id: Idc283042ec10cf1b38ca073df138125b03568e2d

Rebase-Id: R0cd40c5044f07b57ac3b415c20af7bac31cf46f8

5 years agoARM: tegra: clock: Re-factor Tegra3 cpu clocks
Alex Frid [Sun, 13 Mar 2011 08:41:14 +0000]
ARM: tegra: clock: Re-factor Tegra3 cpu clocks

Added second level virtualization (on top of virtual cpu rate control)
to support different Tegra3 CPU power modes: low power (LP) mode and
geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is
defined as a child with two parents: virtual cpu_lp and virtual cpu_g
clocks for the respective modes. Mode switch sequence was integrated
into cpu_cmplx set parent implementation. (Before this commit mode
switch was triggered outside the clock framework, which created cpu
clock/mode synchronization problems).

Each mode clock is derived from its own super clock mux (cclk_lp and
cclk_g) to statically match Tegra3 h/w layout. (Before this commit the
code had to dynamically synchronize CPU mode and active mux selection).
This change also allowed to support PLLX output divider for low power
mode as fixed 1:2 divider with bypass control embedded into cclk_lp
parent section.

Updated auto and sysfs CPU mode switch calls to use new clock framework,
and removed clock manipulation from the low level mode switch
implementation.

Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b
Reviewed-on: http://git-master/r/24734
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be

Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351

5 years agoARM: tegra: set preset_lpj to reduce time bootup secondary cpus
Jin Qian [Fri, 25 Mar 2011 01:44:48 +0000]
ARM: tegra: set preset_lpj to reduce time bootup secondary cpus

Original-Change-Id: I21bf0464275dfd218084a6858bf2fb09f1eec6b6
Reviewed-on: http://git-master/r/24237
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iad6176a44f78e68578b606b77aeb9a0624248913

Rebase-Id: R4b1299798b660a35689595cd0f031f5b066fca3d

5 years agoarm: tegra: timer: New Tegra3 IRQ mapping
Scott Williams [Mon, 14 Mar 2011 22:24:46 +0000]
arm: tegra: timer: New Tegra3 IRQ mapping

Rename timer.c to timer-t2.c for consistency with other
chip-specific implementations.

Bug 790458
Bug 790448
Bug 738259

Original-Change-Id: I7e0fceb716590cd92b64ba00c0bebe659e9beb21
Reviewed-on: http://git-master/r/22885
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I322324c2177d57657a63e9428f8e49d5df2b828e

Rebase-Id: R7312866cdc8044a71cc2f83ad4bc7aa66b07416d

5 years agoarm: tegra: Enable MC early ACK and scoreboard
Scott Williams [Fri, 18 Mar 2011 20:38:02 +0000]
arm: tegra: Enable MC early ACK and scoreboard

Bug 791803

Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432
Reviewed-on: http://git-master/r/23584
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2

Rebase-Id: R3308cf0a852ee2bf0e2adb3de17cebc81e48c71c

5 years agoUpdate copyrights
Scott Williams [Mon, 28 Mar 2011 07:34:42 +0000]
Update copyrights

Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a

Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25

5 years agoARM: tegra: power: Don't enable stats interrupt on Tegra3
Alex Frid [Fri, 18 Mar 2011 23:40:15 +0000]
ARM: tegra: power: Don't enable stats interrupt on Tegra3

Tegra3 does not use stats monitor - do not blindly enable it on exit
from LP2

Original-Change-Id: I9fbcfcefc67510f6145a78edfc35362f9c059cf9
Reviewed-on: http://git-master/r/23731
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ib4797f3ab7ec047975edbaeac7c813e48b93ec0a

Rebase-Id: R3a6ca2294ba024ffc9c822a4f4a3819c9e77c334

5 years ago[arm:tegra] Fixing Tegra physical memory reservation code
Hiro Sugawara [Thu, 10 Mar 2011 23:19:03 +0000]
[arm:tegra] Fixing Tegra physical memory reservation code

Reserving memory in lower half of 4GB address space (for SMMU) freezes
kernel.
Widely accepted convention is "@" _followed_ by address.

Original-Change-Id: Id994dab24953d3113a79adacc4795fe3200f5718
Reviewed-on: http://git-master/r/22464
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id3280ab49278a27500683042ba2b3a0bb98a892d

Rebase-Id: R1bbe1b286c4b7c9ad4ebd6bcf2b3ec24b37bfc0e

5 years agoARM: tegra: cpu: Add CPU ULP mode debug control
Alex Frid [Sat, 12 Mar 2011 05:42:46 +0000]
ARM: tegra: cpu: Add CPU ULP mode debug control

Original-Change-Id: I30e6b308e6c04e4dcb914057284a949ad255d32f
Reviewed-on: http://git-master/r/22708
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I2d221d49aa98d407a18c9d2eb0f5658f56920cbc

Rebase-Id: R84fbe564a1624e2261b4b0623a5fa9d810c1d956

5 years agoARM: tegra: dvfs: Add Tegra3 EMC and CPU rates dependency
Alex Frid [Thu, 10 Mar 2011 02:58:01 +0000]
ARM: tegra: dvfs: Add Tegra3 EMC and CPU rates dependency

Original-Change-Id: I28155e59fd6cb36ccd63d8d17ed01b70b9209f97
Original-Change-Id: Ic4ebe6007ab9ee308039ad86c0930f85d116fdd5
Reviewed-on: http://git-master/r/22531
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I4e5e939921d6d82aa8687545399a867901655069

Rebase-Id: R71c8b69183d12414112d88d60fe54a7b85a6d3de

5 years agoARM: tegra: dvfs: Add emc dfs statistic
Alex Frid [Tue, 8 Mar 2011 18:35:31 +0000]
ARM: tegra: dvfs: Add emc dfs statistic

Original-Change-Id: I191ce07b461c9283d61000ca81746b282502f786
Reviewed-on: http://git-master/r/22530
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I81d6caa3c8f6a0c267d171f38156657ef8c52688

Rebase-Id: R9d9ce785a3e65a0851b3f70159395ed6753bdf87

5 years agoarm: tegra: devices: Adding device details for spi slave
Laxman Dewangan [Fri, 11 Mar 2011 05:18:49 +0000]
arm: tegra: devices: Adding device details for spi slave

Adding device details for the spi slave driver. Also adding clock
details for these drivers.

Original-Change-Id: I38a34c289e296152339dd23858dc19bfb95db354
Reviewed-on: http://git-master/r/22411
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Original-Change-Id: Id60caffa97965ac424083353388a0e6dfd963779

Rebase-Id: R442b1ac8bacbd15325abf7d8dc96699f75cd5fda

5 years agoarm: tegra: clock: Clock support for all dsi instances
ankishore [Wed, 9 Mar 2011 15:29:02 +0000]
arm: tegra: clock: Clock support for all dsi instances

Making clock entries and adding resources for all dsi instances

Original-Change-Id: I2f5552f9a87d410360c15598340f44710798725b
Reviewed-on: http://git-master/r/22233
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: Ia9a70ea207510d09cf6263b0bed2c5465d8b2231

Rebase-Id: R308216681eeef3bda0d3fc0d6ec7646786153219

5 years agoARM: tegra: dvfs: Add Tegra3 EMC scaling mechanism
Alex Frid [Sun, 6 Mar 2011 04:59:22 +0000]
ARM: tegra: dvfs: Add Tegra3 EMC scaling mechanism

Original-Change-Id: I23954a8d005fae93866666fff0e56edb23a49d46
Reviewed-on: http://git-master/r/21940
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I31c3910d38f9999ddbf3414e042e1972d9a86c5a

Rebase-Id: Rd6ca05872b34fa23bef682b4185fb4f354632c3a

5 years agoarm: tegra: Merge changes from main branch
Vinod G [Thu, 3 Mar 2011 22:57:08 +0000]
arm: tegra: Merge changes from main branch

Changes specific to separate the codecs based on board are
integrated from rel-2010-11 branch

Original-Change-Id: I9fe2e05d5347f02cd3047f453d03437b735e2c4b
Reviewed-on: http://git-master/r/21562
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Scott Peterson <speterson@nvidia.com>
Original-Change-Id: I06473d906c1043a8fcc511cd66cfb57e311afdae

Rebase-Id: R35499b0a4c1a947e119383b53e9843f23c18cf88

5 years agoARM: tegra: timer: Restructure timer controllers usage.
vdumpa [Thu, 24 Feb 2011 01:57:49 +0000]
ARM: tegra: timer: Restructure timer controllers usage.

Restructure timer controller usage in order to add Lp2 wake timers
for all cpu's.

Bug 790458

Original-Change-Id: Ie71eb9fb8c1bee0bd059d40b1761718931c9bfe0
Reviewed-on: http://git-master/r/20692
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I16ccea6db75ec4fd0d7da264c37b311113e59fd7
Dan Willemsen: Add export.h include

Rebase-Id: Rf0292ae426d874ac8c7cd0fa988ba7314c5256a2

5 years agoarm: tegra: Update AHCI/SATA driver support
Yen Lin [Tue, 8 Feb 2011 04:00:31 +0000]
arm: tegra: Update AHCI/SATA driver support

- Added SATA pad pll and plle initialization
- Removed usage of driver's platform data
- Implemented placeholder for SATA power-gating/ungating

Original-Change-Id: I6cd7f5fca95320aa5f429edbd4de5e28fd4c0ac7
Reviewed-on: http://git-master/r/18650
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I5cea5d8ad38b85a01287e26ded759bb8c3988530

Rebase-Id: Rc29cfb95ee43f09c3ae121356271a2d327f7d5b8

5 years agotegra:watchdog: Change timer src to timer10 for watchdog.
vdumpa [Thu, 24 Feb 2011 00:10:27 +0000]
tegra:watchdog: Change timer src to timer10 for watchdog.

Fix wdt resource definition issue either.
Bug 790458

Original-Change-Id: I7c80d6c243c42a0e632603dfcc255b70995358b2
Reviewed-on: http://git-master/r/20646
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I9897fb6614d75508bd0ffd6e866acf27a24a0cb5

Rebase-Id: Re3da893171091a337f9e6536641bb2374036b013

5 years agotegra:watchdog: Use new watchdog controller.
vdumpa [Wed, 16 Feb 2011 08:01:24 +0000]
tegra:watchdog: Use new watchdog controller.

Use new watch dog controller for CONFIG_ARCH_TEGRA_3x_SOC.
Bug 790458

Original-Change-Id: I43975a2794f44f612a5f16674cd674aeebe4e6be
Reviewed-on: http://git-master/r/19715
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: Ic8c9907998a2ab1777ea2b00f1acceb6d66c10e5

Rebase-Id: Rc7878358e81b0c5cda6acf5bb30b759e26f674a7

5 years agoARM: tegra: cpu: Auto-hotplug stats control
Alex Frid [Sun, 20 Feb 2011 03:00:39 +0000]
ARM: tegra: cpu: Auto-hotplug stats control

Do not update auto-hotplug statistic when auto-hotplug is disabled;
initialize and restart updating after it is enabled.

Original-Change-Id: I3a202ab3f0d3d194207e1e881248edac1f820802
Reviewed-on: http://git-master/r/20229
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: Iabc61ecd866b421d7cd819d420051ada83c97b87

Rebase-Id: Rc8e222d920642c2c61587290c8542c69538354a8

5 years agoarm: tegra: Adding device entry for SPI5 and SPI6
Laxman Dewangan [Mon, 21 Feb 2011 14:43:49 +0000]
arm: tegra: Adding device entry for SPI5 and SPI6

Adding device entries for SPI5 and SPI6 for TEGRA3 ARCH.

Original-Change-Id: Ie9d6a1e0cb9488bf07327c403edb78626137688b
Reviewed-on: http://git-master/r/20309
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: I7706a2b32177aaa4b4ca53d4f089cb3218f51ba3

Rebase-Id: Ra0f5901afa740929c904d681f89582d04ff230c1

5 years agoARM: tegra: cpu: Update auto-hotplug policy
Alex Frid [Sun, 13 Feb 2011 01:20:43 +0000]
ARM: tegra: cpu: Update auto-hotplug policy

Do not switch to G cluster if cpufreq spikes above LP frequency limit
for a short time - currently set threshold to 100ms. Fixed timing
update for LP cluster statistic.

Original-Change-Id: Id4f00fd5c39d7fe2aa931da30cf607a5144dc3ab
Reviewed-on: http://git-master/r/19381
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: Ief6d391a5806d6cba20b6b5b407acb9846725260

Rebase-Id: Ref560d34203900e32b63d5b6104cb0fb105e4c63

5 years agoARM: tegra: Update secondary CPU power up procedure
Alex Frid [Sat, 12 Feb 2011 02:17:28 +0000]
ARM: tegra: Update secondary CPU power up procedure

- Wait for power up status confirmation after secondary CPU was
un-gated by flow controller (instead of directly UN-gating CPU
again if the 1st status check failed).
- Enable CPU clock only after power up is confirmed.
- Insert propagation delays before and after removing clamps.

Original-Change-Id: I81cd1479bdb49163eeb9a369fc165cede49eb71a
Reviewed-on: http://git-master/r/19372
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I061738a5c5f46299cccfcb264d9b5bd838694305

Rebase-Id: R8f3d1364c016aaf4d9856add97612dc7ac77aa6e

5 years agoarm: tegra: Fix initial boot to LP cluster
Scott Williams [Fri, 11 Feb 2011 22:37:19 +0000]
arm: tegra: Fix initial boot to LP cluster

Forbid cluster switch to G cluster if the G cluster doesn't exist.

Bug 791057

Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23
Reviewed-on: http://git-master/r/19302
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9

Rebase-Id: Re39a0fedb7bb0e2518cfd56d46c6565d4a6c2ef4

5 years agoARM: tegra: cpu: Add Tegra3 auto-hotplug statistic
Alex Frid [Wed, 9 Feb 2011 05:49:07 +0000]
ARM: tegra: cpu: Add Tegra3 auto-hotplug statistic

Add auto-hotplug statistic to track number of transitions and on-line
time for each CPU/cluster.

Original-Change-Id: Iefaf4f69068401eb7a9d4abbf725df4e21d35db9
Reviewed-on: http://git-master/r/19168
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I62209733054dddbc18741b7fca0c481c90f3aba7

Rebase-Id: R3ef66d1e09da307a7aac93082692d8ee27075299

5 years ago[arm:tegra] Change address printout from decimal to hex.
Hiro Sugawara [Fri, 11 Feb 2011 22:42:50 +0000]
[arm:tegra] Change address printout from decimal to hex.

We are more comfortable with hex memory addresses than decimal.

Original-Change-Id: I30b287cf494dd062d20b1d316e0c058700bbaaee
Reviewed-on: http://git-master/r/19299
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iea856d89c4a6c47614e7cea8e31eb7c2f5719224

Rebase-Id: R4aea899c824c24d009434f25c152997277d1246f

5 years agoarm: tegra: Reserve SMMU I/O window address space
Scott Williams [Thu, 10 Feb 2011 22:35:32 +0000]
arm: tegra: Reserve SMMU I/O window address space

Bug 790951
Bug 791114

Original-Change-Id: I50ac8b20c1a1cd2ed5c135f940ec1791fb3dc6c0
Reviewed-on: http://git-master/r/19145
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I3406c6cc5b0733b91965983028dc5935f2ad62f8

Rebase-Id: R5dff98dee46a0789c3c4e90008a34161c81eb7b3

5 years agoARM: tegra: Add auto-hotplug support for Tegra3
Alex Frid [Sat, 5 Feb 2011 09:11:13 +0000]
ARM: tegra: Add auto-hotplug support for Tegra3

Initial implementation of Tegra3 quad core CPU management. Add closed
control loop on top of cpufreq DFS. Target frequency range is bounded
by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and
Fmax(Vminimum) for high power cluster - currently set to 356MHz.

When CPU frequency is scaled below the target range, slave high power
CPUs are gradually brought down and eventually CPU is switched to the
low power cluster.

When CPU frequency is scaled above the target range, CPU is switched
to the high power cluster and slave high power CPUs are gradually
brought up.

The auto hotplug support is disabled on boot. It can be explicitly
enabled via sysfs interface.

Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7
Reviewed-on: http://git-master/r/18500
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827

Rebase-Id: R9cf5f5f8868c659db526cb49ddf276a79d93ef1a

5 years agoarm: tegra: atag: Board information through ATAG_SERIAL
Laxman Dewangan [Sat, 5 Feb 2011 10:56:42 +0000]
arm: tegra: atag: Board information through ATAG_SERIAL

Fastboot passes the information of board info through ATAG_SERIAL.
Using this tag information to extract board info.

Original-Change-Id: I359044236756464ee3b8084878b2fd8969956fe7
Reviewed-on: http://git-master/r/18485
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I92fe8ba752606bd52039bea4c4447f24c9e56c6a

Rebase-Id: R3c2d0c6913e9f7994048eed69a7172a399acf876

5 years agoARM: tegra: Shorten cluster switch timing reports
Alex Frid [Sat, 5 Feb 2011 05:41:50 +0000]
ARM: tegra: Shorten cluster switch timing reports

Original-Change-Id: I9e0744eb937223062e0582900fd0fb33a3ae1707
Reviewed-on: http://git-master/r/18468
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I40995652cb88c643b2e8ce5e7af707bbe7d9bfed

Rebase-Id: R13c5ece418546c7945a03edae120d366685cdae2

5 years agoarm: tegra: Add run-time cluster switch debug control
Scott Williams [Tue, 1 Feb 2011 20:52:39 +0000]
arm: tegra: Add run-time cluster switch debug control

Allow run-time control of cluster switch debug messages
so they can be enabled for debuggability and disabled for
performance measurement.

Original-Change-Id: Id2bd85d6a9d3a57430a20d93b51ce5b59fe53c71
Reviewed-on: http://git-master/r/17927
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia57424eee01276d82af7aab37d2f3d0525acc379

Rebase-Id: Rb7054dcdd910d9f1b82edb485856e868a47c5034

5 years agoarm: tegra: printing board sku correctly
Laxman Dewangan [Thu, 3 Feb 2011 14:12:15 +0000]
arm: tegra: printing board sku correctly

Printing board SKU correctly during boot.

Original-Change-Id: Ib1071ac640bf32db41cb0b8442cbd14bbe97980c
Reviewed-on: http://git-master/r/18197
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: I07741921f7cf46fbcd268ca97412ba5af78ecdd4

Rebase-Id: R6fc5a6a88e9bb75502631d427393c9386b974934

5 years agoarm tegra:Using pll_p clk source for sdmmc instances.
Pavan Kunapuli [Thu, 3 Feb 2011 07:20:22 +0000]
arm tegra:Using pll_p clk source for sdmmc instances.

Using pll_p clk source for all sdmmc instances.
Disabling clocks left over by the bootloader.

Original-Change-Id: I245347b016618c39a4ceb2323f659b09261eaf7d
Reviewed-on: http://git-master/r/17847
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: I0790f6f67c944a9ca42be9d6b9398d8093b4beef

Rebase-Id: Reb04f18203438d4d42e6f066d4c5216b692aabc2

5 years agoarm: tegra: Instrument cluster switch transitions
Scott Williams [Tue, 1 Feb 2011 03:56:16 +0000]
arm: tegra: Instrument cluster switch transitions

Original-Change-Id: I1526de69a1224f42ce3ff11ba1b6fa949c2f13a5
Reviewed-on: http://git-master/r/17787
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I43caec7348d970dc076f27cc2bb4b6ded234a38c

Rebase-Id: Ra122021184a1c12cc85e08cd3d7abe41345db058

5 years agoarm: tegra: Fix spdif driver issues for T30.
Vinod G [Tue, 1 Feb 2011 22:51:16 +0000]
arm: tegra: Fix spdif driver issues for T30.

Bug Id 786814
Bug Id 787110

Spdif is exposed as a device. Apbif channel 3 is fixed for spdif now.

Original-Change-Id: I1410fac521c7880f088e3274d3d660e20dd78223
Original-Change-Id: I63a59834c130207655544abf35424eb6ea4943be
Original-Change-Id: Ib96cd03bf30a537aaac9e11eeb9f0178c4218672
Reviewed-on: http://git-master/r/17944
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I2ab35521f4616eaec3c98e8c50e5f9b9f2f0ba93

Rebase-Id: R85fba25008a7a39b7f568726d9402cafbf97b6ef

5 years ago[ARM/tegra] HDA Driver support
Dara Ramesh [Wed, 12 Jan 2011 04:15:54 +0000]
[ARM/tegra] HDA Driver support

Adding HDA audio driver support for Tegra3

Original-Change-Id: I81a76a54f6ce5390051d96dbeadf447682f9ff0e
Reviewed-on: http://git-master/r/15405
Tested-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8525ef7317606b895818e73ec92ca174dddf609e

Rebase-Id: R22fcd501393111d656418f67928f5dfd0b38c870

5 years agoarm: config: tegra: cardhu: config for Verbier E1187
Laxman Dewangan [Mon, 31 Jan 2011 09:29:07 +0000]
arm: config: tegra: cardhu: config for Verbier E1187

Adding config variables for the Verbier E1187 configuration.
By default cardhu will be build for E1198.
The cardhu can be build for E1187 by saying config variable
CONFIG_TEGRA_VERBIER_E1187 to yes.

Original-Change-Id: I635ac29c418be6d8f59f681c8755b682d02e60f1
Reviewed-on: http://git-master/r/17663
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: Ia930e4319305923c6d4c2cf32eb6a286132f0ab9

Rebase-Id: Ra438a70ee6694e52889c9f4b51826920f53a11f8

5 years agoarm: tegra: pinmux: Supporting LOCK/OD/IORESET pin configuration.
Laxman Dewangan [Fri, 28 Jan 2011 23:51:53 +0000]
arm: tegra: pinmux: Supporting LOCK/OD/IORESET pin configuration.

Supporting the LOCK, OpenDrain (OD), IO_RESET configuration on pinmux register
through pinmux apis.

Original-Change-Id: I2459723c5fbcadd925331696c9469f64d2ba3b20
Reviewed-on: http://git-master/r/17532
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: Ibd06c9a650ffbacf51530514e58bd52d1f60b4f2

Rebase-Id: R8e593a0b1e27db641d2e0c7b57a2946d97819f25

5 years agotegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributes
vdumpa [Wed, 17 Nov 2010 23:57:13 +0000]
tegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributes

Change the cacheability attributes in the normal memory remap
register (NMRR) to inner write-back write-allocate/outer write-back
no-write-allocate to improve L2 cache performance.

Bug 728231
Bug 751146

Original-Change-Id: I992dd20b3cec3b0141ae114d5ae278122be0212d
Reviewed-on: http://git-master/r/11077
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/17475
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0de3100975c592fe4a18780c2b0eb2c5d12258d7

Rebase-Id: R430708cbf798ff30f5a5394a5235942e95bda2d4

5 years agoarm: tegra: sdhci: Do not disable sdmmc4 clock
Pavan Kunapuli [Wed, 26 Jan 2011 19:14:53 +0000]
arm: tegra: sdhci: Do not disable sdmmc4 clock

Do not switch off sdmmc4 clock. Also, removed ddr
mode temporarily from linux mmc driver.
Programming tap_delays and internal clock.

Original-Change-Id: I830bf5e94ccd47e154c5ef9909e8bff1ff7754c0
Reviewed-on: http://git-master/r/17070
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic1cff8dd85229fe903206f1dc9a967d600ba88c1

Rebase-Id: R9c15db46ec7f4073c03301dbc77ee5cb2f7800bd

5 years agoARM: tegra: clock: Prevent parent over-clocking
Alex Frid [Tue, 25 Jan 2011 06:12:28 +0000]
ARM: tegra: clock: Prevent parent over-clocking

Pre-set clock rate when changing parent to avoid parent over-clocking
during clock initialization from common/board specific tables. Drivers
however, may still hit over-clocking error.

Original-Change-Id: Ib101d85e90ab4c1194ac98680c930eebd8c56b76
Reviewed-on: http://git-master/r/16877
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I307e7eb507d885c381087812d262d56338aab861

Rebase-Id: R1c5fae8b3b048b31b2ed775a602ea33afb5c732e

5 years agoARM: tegra: clock: Add check for parent over-clocking
Alex Frid [Tue, 25 Jan 2011 04:33:16 +0000]
ARM: tegra: clock: Add check for parent over-clocking

Fail clk_set_parent() interface if switching the clock parent will set
the rate above maximum limit.

Original-Change-Id: I47c0798dafe5f8f497dcacfcd23f6957244cdb0a
Reviewed-on: http://git-master/r/16876
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ie5fef027411096a465ae5aa84fe84a08a769a613

Rebase-Id: Rce314c75bbd31c8fc579e7bd22a00777dc6e94dc

5 years agoARM: tegra: clock: Add Tegra3 PLLE support
Alex Frid [Sun, 23 Jan 2011 02:40:45 +0000]
ARM: tegra: clock: Add Tegra3 PLLE support

Original-Change-Id: Iba29ff515fd850cd0f736d5ef693877e85fb0c5c
Reviewed-on: http://git-master/r/16660
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8d6efae37847fcbda12290b6cd5d61e6a61c2777

Rebase-Id: R9a7e6567990346882ad742c43b8ab8f41cfda9d0

5 years agoARM: tegra: clock: Propagate errors in debugfs
Alex Frid [Sun, 23 Jan 2011 03:08:54 +0000]
ARM: tegra: clock: Propagate errors in debugfs

Original-Change-Id: I7d7f4f49cc1e41707032467197d53967d3ecaf06
Reviewed-on: http://git-master/r/16659
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I9e04b2833ef12466664cf6f6c2666d440600db08

Rebase-Id: Rd3ba800e548a5ccf6a756d5523a0fc240819dc64

5 years agoARM: tegra: clock: Add clock state debugfs control
Alex Frid [Sun, 23 Jan 2011 01:05:01 +0000]
ARM: tegra: clock: Add clock state debugfs control

Original-Change-Id: I2a16c36c8ee414a1f046eda2f3bdb9c1d71caf8b
Reviewed-on: http://git-master/r/16657
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Icc4b526f44697bd788d83434f6e9a62de005b09c

Rebase-Id: R34e12f5fbafa93a8f01cd00d83a33b356d0782ec

5 years ago[arm:tegra] Adding MC_DECERR interrupt handler
Hiro Sugawara [Wed, 19 Jan 2011 21:57:30 +0000]
[arm:tegra] Adding MC_DECERR interrupt handler

Adding MC_DECERR interrupt handler ported from Froyo.
This addition will not gracefully terminate a failing DMA transfer.
The handler does noting but simply reporting the error status with prink,
and the clinet software will likely hang forever waiting for a non-
completing DMA transfer. But it is still useful for debugging.

Reviewed-on: http://git-master/r/16289
(cherry picked from commit 4c66e8b978f054b332c21a97a53d89f588d24889)

Original-Change-Id: I7b19c70d8cbb62be9ab3f955bf19c707c1e5045d
Reviewed-on: http://git-master/r/16590
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibdcfe63d56d22e39d8c5398ff50eb663bd0d82f3

Rebase-Id: R5a24a2ae2ab4585c3d48c76761beef815a665649

5 years agoarm: tegra: Add SATA support
Yen Lin [Thu, 13 Jan 2011 20:37:10 +0000]
arm: tegra: Add SATA support

Original-Change-Id: I18c63f1c69e155ddc1cec1718af9684d861815b7
Reviewed-on: http://git-master/r/15863
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/16485
Original-Change-Id: I6afa5a097b4fc7d6c45614107118458da0d9d888

Rebase-Id: R18ae88707c208faafc26de033e9f34a7466fa608

5 years agoarm: tegra: Enable Tegra3 cluster control
Scott Williams [Fri, 7 Jan 2011 18:48:48 +0000]
arm: tegra: Enable Tegra3 cluster control

Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3
Reviewed-on: http://git-master/r/15269
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae

Rebase-Id: R880097280de4f9691f689ab8ab25f08020e98e23

5 years agoarm: tegra: Fix reserved memory area reporting
Scott Williams [Thu, 13 Jan 2011 22:30:20 +0000]
arm: tegra: Fix reserved memory area reporting

Also fixes:
 - possible unitialized global variable usage.
 - corruption of the LP0 code segment if there is no bootloader framebuffer.

Original-Change-Id: Ic163be339dad8b9bb3c3ffe509ccfd8ea33c8299
Reviewed-on: http://git-master/r/15875
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibc6838c412caf0e2f452a4737ec36ad67434f636

Rebase-Id: R957b8e03b5c3f1db1eabb880589357d49c65a49a

5 years agoMerge remote branch 'git-master/android-tegra-2.6.36' into 0112-1120
Dan Willemsen [Sat, 26 Mar 2011 01:49:07 +0000]
Merge remote branch 'git-master/android-tegra-2.6.36' into 0112-1120

Conflicts:
Makefile
arch/arm/configs/tegra_defconfig
arch/arm/configs/tegra_whistler_android_defconfig
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-ventana-sensors.c
arch/arm/mach-tegra/board-ventana.c
arch/arm/mach-tegra/board-whistler-panel.c
arch/arm/mach-tegra/board-whistler-pinmux.c
arch/arm/mach-tegra/board-whistler-power.c
arch/arm/mach-tegra/board-whistler-sensors.c
arch/arm/mach-tegra/board-whistler.c
arch/arm/mach-tegra/board-whistler.h
arch/arm/mach-tegra/clock.c
arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/cpu-tegra.c
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/devices.h
arch/arm/mach-tegra/dma.c
arch/arm/mach-tegra/fuse.c
arch/arm/mach-tegra/fuse.h
arch/arm/mach-tegra/headsmp.S
arch/arm/mach-tegra/include/mach/clk.h
arch/arm/mach-tegra/include/mach/iomap.h
arch/arm/mach-tegra/include/mach/system.h
arch/arm/mach-tegra/irq.c
arch/arm/mach-tegra/spi_tegra_slave.c
arch/arm/mach-tegra/suspend.c
arch/arm/mach-tegra/tegra2_dvfs.c
arch/arm/mach-tegra/tegra2_emc.c
arch/arm/mach-tegra/tegra2_emc.h
arch/arm/tools/mach-types
arch/x86/kvm/svm.c
drivers/cpufreq/cpufreq_interactive.c
drivers/crypto/tegra-aes.c
drivers/gpio/cs5535-gpio.c
drivers/hwmon/nct1008.c
drivers/misc/Makefile
drivers/net/wireless/p54/p54usb.c
drivers/regulator/max8907c-regulator.c
drivers/rtc/rtc-tegra.c
drivers/usb/gadget/fsl_udc_core.c
drivers/usb/host/ehci-tegra.c
drivers/usb/host/xhci-mem.c
drivers/usb/otg/tegra-otg.c
drivers/usb/serial/ftdi_sio.c
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/hdmi.c
drivers/video/tegra/dc/hdmi.h
drivers/video/tegra/host/dev.c
drivers/video/tegra/host/nvhost_channel.c
drivers/video/tegra/host/nvhost_intr.c
include/linux/nct1008.h
net/econet/af_econet.c
sound/soc/tegra/Kconfig
sound/soc/tegra/tegra_i2s.c
sound/soc/tegra/tegra_pcm.c
sound/soc/tegra/tegra_soc.c
sound/soc/tegra/tegra_soc.h

Original-Change-Id: I5b39fd8ea2284828e9cb3b5ce4330728e20b1662
Reviewed-on: http://git-master/r/15736
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I71ecd7c4426e7e82500f12d57b85a6bcc417065c

Rebase-Id: Rc18bd03bdd6ef4cf0a5ae6f7dc863729deb2eb27

5 years ago[arm/tegra] Enable audio device in T30
Vinod G [Fri, 14 Jan 2011 03:57:20 +0000]
[arm/tegra] Enable audio device in T30

audio device is enabled in the device file

Original-Change-Id: Id19526c0be5d77c25e81cb1e75648288174fadd0
Reviewed-on: http://git-master/r/15910
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Original-Change-Id: I3eaf368150a62df38683f79c10180078a57052c3

Rebase-Id: R865e609be363dfa234d06ff4a90914df1d491499

5 years agotegra: avp: enable AVP and moduleloader
Kaz Fukuoka [Mon, 6 Dec 2010 01:56:54 +0000]
tegra: avp: enable AVP and moduleloader

- Load AVP kernel at fixed address.
- Use nvmem= carveout to load AVP kernel.

bug 765965
bug 777221

Original-Change-Id: I60b650a395936450687cea9b881f78bcee854421
Reviewed-on: http://git-master/r/15343
Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I34b6acd03075325733a7bc3f005b71a7c1721919

Rebase-Id: Rd49ac25885533bfda0e9e346e8c9acf0a90d2e05

5 years ago[ARM] tegra: Fixing the details of config TEGRA_FPGA_PLATFORM
Kirubakaran Sampath [Mon, 10 Jan 2011 15:26:44 +0000]
[ARM] tegra: Fixing the details of config TEGRA_FPGA_PLATFORM

Adding the details like default value and help for the config
variable TEGRA_FPGA_PLATFORM in Kconfig file.

Making cardhu as depends on Tegra3 soc architecture.

Original-Change-Id: Ib395ffa09c44a8924fdc6bf514132d98acec7bc8
Reviewed-on: http://git-master/r/15408
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic797d7f5fbcec7c7763f8fe4b694afb385e3ad4c

Rebase-Id: R971b115a978dc241ee2dda9ddc72c7f9295278a7

5 years agoarm: tegra: Fix hardcoded frame buffer addresses
Scott Williams [Tue, 11 Jan 2011 18:50:52 +0000]
arm: tegra: Fix hardcoded frame buffer addresses

Dynamically obtain the carveout and framebuffer addresses.

Bug 769986

Original-Change-Id: I9b8eeb710e5198ab9ae4e7e6c7095cfd23209e66
Reviewed-on: http://git-master/r/15534
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia6f68817b65281bd5da4f8774476a947fd970950

Rebase-Id: R0b89a83745b538f0d0b8eb5ceaecacb785b643a6

5 years agoARM: tegra: clock: Add Tegra3 EMC shared bus
Alex Frid [Sun, 9 Jan 2011 05:00:54 +0000]
ARM: tegra: clock: Add Tegra3 EMC shared bus

Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94
Reviewed-on: http://git-master/r/15349
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777

Rebase-Id: R3cab0fa7760e2c6eb5d6e84bbc3dca8f6fe3d3fa

5 years agoarm: tegra: Enable DCC sysfs device node
Scott Williams [Thu, 6 Jan 2011 01:19:58 +0000]
arm: tegra: Enable DCC sysfs device node

Original-Change-Id: Ifdad566dfc809771de5f66301d3a8a98a49bb679
Reviewed-on: http://git-master/r/15079
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I47af8814b72786b52c25e824c79ccf4e52ca0b62

Rebase-Id: R2f4ae262a94e887f88f749bd0a1103b201e1b3c5

5 years agoarm: tegra: Add Tegra3 cluster-dependent PL310 timing values
Scott Williams [Thu, 6 Jan 2011 01:53:39 +0000]
arm: tegra: Add Tegra3 cluster-dependent PL310 timing values

The tag and data RAM latency values for the PL310 L2 cache controller
are different between the G and LP CPU clusters. Set the correct
cluster-dependent value whenever initializing or re-initializing
the L2 cache controller.

Original-Change-Id: I7681ebec58eaff293577269a85c51994140b1e34
Reviewed-on: http://git-master/r/15082
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I3f637783b52930f1d9303e044b645c7d136efc70

Rebase-Id: R3ca0fe222b013b22c01f1869616e729e975349ac

5 years agoarm: tegra: Add Tegra3 wakeup sources
Scott Williams [Wed, 5 Jan 2011 16:44:01 +0000]
arm: tegra: Add Tegra3 wakeup sources

Original-Change-Id: I77cb790db20cc8c8b67069130c0bc8724ba8934e
Reviewed-on: http://git-master/r/15027
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I45764ed134dc0be2a21d7641692efb9c847a9b7a

Rebase-Id: R0a34fc6fc83145c3720471d359216befb5d0bf5b

5 years agoarm: tegra3: Fix chip unique id generation
Scott Williams [Tue, 4 Jan 2011 03:17:59 +0000]
arm: tegra3: Fix chip unique id generation

Original-Change-Id: I1bb441213edfd6440e890e0eb77c07577168d2a9
Reviewed-on: http://git-master/r/14854
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id4470677f046ef4f3ff9f592cb5d7aafee460e07

Rebase-Id: R93290bbeec5c12c8fe9acf301d66c22191f5821e

5 years agoFix makefile formatting
Dan Willemsen [Fri, 6 May 2011 18:58:19 +0000]
Fix makefile formatting

Rebase-Id: Rcb25f3a7195dbda4b0b5e015581506374780c2ca

5 years agoARM: tegra: clock: Update LP-cluster related interfaces
Alex Frid [Wed, 29 Dec 2010 19:30:52 +0000]
ARM: tegra: clock: Update LP-cluster related interfaces

Original-Change-Id: Ifde476a05bd01cdce8c3f4802b268a193a832a1b
Reviewed-on: http://git-master/r/14584
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I41204d17c5d8092b1a24b3138efe12cfbd16d7e7

Rebase-Id: R9754ff5e07ecabd945edfccdbc0f9d9586be6e23

5 years agoPARTIAL arm: tegra3: Add CPU idle support
Scott Williams [Wed, 22 Dec 2010 21:44:20 +0000]
PARTIAL arm: tegra3: Add CPU idle support

Original-Change-Id: I5464b01ebb454b7fdc6fd316ba31de110a642063
Reviewed-on: http://git-master/r/14167
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I201cdb6dc4e78f762266cb96e48689d4d4f963f6

Rebase-Id: Rb3ac2fff9435330ec65c5541d369b743c9cb898f

5 years agoHACKY: Partial revert of passing latency to tegra_init_cache
Dan Willemsen [Thu, 22 Mar 2012 23:15:05 +0000]
HACKY: Partial revert of passing latency to tegra_init_cache

We use tegra_init_cache in the PM code too, so this ends up dup'ing a
good amount of detection everywhere.

This should be cleaned up somehow, but reverting during the first pass
of the 3.3 rebase.

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R3adc596da8b57936cb2c1cf598ce9a67ebdf72a1

5 years agoARM: tegra3: Swap PCIE and VDE power gate controls
Scott Williams [Tue, 21 Dec 2010 17:44:12 +0000]
ARM: tegra3: Swap PCIE and VDE power gate controls

The PCIE and VDE power gated controls are not swapped on just
Tegra2. The swapping has been enshrined as a "feature" now.

Original-Change-Id: Iad8820570414d5377d9d6eed65a57190c4eaec7f
Reviewed-on: http://git-master/r/14000
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ieb72637c659ca05ff1a3b2c363e2d76a66f48ad8

Rebase-Id: R2c55a9fc3c44526a786aaf80fb57d7dd29b12cdc

5 years ago[ARM/tegra] Add Tegra3 support
Scott Williams [Tue, 7 Dec 2010 19:19:20 +0000]
[ARM/tegra] Add Tegra3 support

Bug 764354

Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081

Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b

5 years agoARM: tegra: whistler: Power down/up core rail
Prashant Gaikwad [Thu, 21 Apr 2011 04:13:48 +0000]
ARM: tegra: whistler: Power down/up core rail

program pwren signal of max8907c regulator to power down/up core rail on
deep sleep enter/exit deep sleep mode.

core_timer and core_off_timer changed as per K32.

separate_req set to false as whistler pmu has combined power requests.

Bug 817378

Original-Change-Id: Ia95a61360079f919a039572cf8fd4597db9efd50
Reviewed-on: http://git-master/r/28435
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R51bd290332e65f90d7e3013389d1456a99809051

5 years agoARM: tegra: add bsea to tegra_aes_resources
srawat [Tue, 19 Apr 2011 09:28:48 +0000]
ARM: tegra: add bsea to tegra_aes_resources

Bug 803932

Original-Change-Id: I52703d6281bf613d7ccf67c38daf6412ac790c74
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28173
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rfb1254b3896712f74f3bc99bea8e5f605ee99036

5 years agoARM: tegra: add address map for bsea
srawat [Tue, 19 Apr 2011 09:22:04 +0000]
ARM: tegra: add address map for bsea

Bug 803932

Original-Change-Id: I61cf41423d08d2f2c19f314269be9e8ee6255b9b
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28172
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R02b7966e10b12832c50b237743ff003a68821e95