5 years agoARM: tegra: Get cluster ID by reading MPIDR
Bo Yan [Sat, 15 Dec 2012 22:53:50 +0000]
ARM: tegra: Get cluster ID by reading MPIDR

This is to avoid MMIO access, thus save a few processor cycles.

Change-Id: Ib4a2aaf8e991885baab51cd74a37387e91cfb5a8
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/171656
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra11: clock: Change SCLK high rate clock source
Alex Frid [Tue, 11 Dec 2012 22:36:35 +0000]
ARM: tegra11: clock: Change SCLK high rate clock source

Changed SCLK high rate clock source from secondary PLLM output
(pll_m_out1) to secondary PLLC output (pll_c_out1), when PLLM
scaling option is selected. Updated pll_c_out1 flags.

Bug 1188643

Change-Id: I899cf5b6d04cc27f63de7f01fb7aa78636e61ea6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171527
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Change default VI clock parent
Alex Frid [Tue, 11 Dec 2012 21:21:24 +0000]
ARM: tegra11: clock: Change default VI clock parent

Changed default VI clock parent to PLLP when PLLM scaling option
is selected (boot-loader leaves VI on PLLM, which is not allowed
in this case).

Bug 1188643

Change-Id: Ia2018855b05c9751c136211203325f5c0698aa91
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171526
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Verify clock parents
Alex Frid [Tue, 11 Dec 2012 01:05:13 +0000]
ARM: tegra11: clock: Verify clock parents

Updated Tegra11 clock parents allowed policy, and verified that all
clocks are compliant with the policy after board clock initialization
is completed. Generated WARN() for any non-compliant clock.

Bug 1188643

Change-Id: Ie2258336b9ea960d4cd5fa9c27bb4d663ce993db
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171525
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: dalmore: Set TPS51632 ops mode to change control mode
Laxman Dewangan [Fri, 14 Dec 2012 06:32:42 +0000]
ARM: tegra: dalmore: Set TPS51632 ops mode to change control mode

Change-Id: I2a3106e1fa4674c8005245bbfd64f94ad38618f5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/171311
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoregulator: tps51632: add support for change control mode
Laxman Dewangan [Fri, 14 Dec 2012 06:30:27 +0000]
regulator: tps51632: add support for change control mode

TPS51632 output can be control through register write via i2c or
through input pwm signal.
Adding support for switching the control mode to I2C or PWM
dynamically.

Change-Id: I57d72eff5c819a2b84f25ba82482bb9723c2c452
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/171310
GVS: Gerrit_Virtual_Submit

5 years agoregulator: add support for changing control mode of regulator
Laxman Dewangan [Fri, 14 Dec 2012 06:27:52 +0000]
regulator: add support for changing control mode of regulator

Some of device supports to control the regulator output to
be set either through register write via I2C or through PWM.
Add supports to switch the mode dynamically.

Change-Id: I3214a6ff89f85592b1ada8e64f0946693ef4f4cc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/171309
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: add base address & size for 2d and 3d
Mayuresh Kulkarni [Fri, 7 Dec 2012 10:01:19 +0000]
arm: tegra: add base address & size for 2d and 3d

bug 1041377

Change-Id: I2f3d0eb0b2e92a70ec641be2920ae61a57cd4417
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/169347
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: init irq from device-tree
Mayuresh Kulkarni [Wed, 12 Dec 2012 07:32:32 +0000]
ARM: tegra: init irq from device-tree

- enable the intc node
- hook irq init via device-tree for boards that support DT
- for non-DT boards, fallback to non-dt method
- deprecate tegra_init_irq and change tegra_dt_init_irq
to check if dtb is passed. If passed, use it to init irq
otherwise fall-back to non-dt path

bug 1164943

Change-Id: Idd87945df250c3cdef38226a9dbf2d6ffd34ce48
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/147496
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Add memory PLLM scaling option
Alex Frid [Sat, 8 Dec 2012 02:29:49 +0000]
ARM: tegra11: clock: Add memory PLLM scaling option

Added an option to scale memory PLLM using PLLC as a fixed rate
backup pll, as an alternative to current policy that keeps PLLM
at fixed rate and scales PLLC. By default this new option is not
selected, and PLLC scaling is still used.

Bug 1188643

Change-Id: I35736a477bea6537d237a4c70f097bac09eaf7e5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171524
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agousb: gadget: tegra: Fix race condition
Rakesh Bodla [Fri, 14 Dec 2012 12:03:25 +0000]
usb: gadget: tegra: Fix race condition

There is race condition in turning ON the
PHY. Due to this phy is not turned ON in
some cases. Fixing this will make sure PHY
is turned ON and off properly.

Bug 1197760

Change-Id: I033359b4dc177db6e7c1b2b3f7bd6e7e2ed68ad6
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/171412
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra11: dvfs: Update CL-DVFS debug interface
Alex Frid [Fri, 14 Dec 2012 05:39:32 +0000]
ARM: tegra11: dvfs: Update CL-DVFS debug interface

- Added Vmin read-only entry to CL_DVFS debugfs interface:
/d/clock/dfll_cpu/cl_dvfs/vmin_mv

- Updated rate monitor to account for output scaler at low rates.

Change-Id: If51294f3ce673c471223f38931f0a642a8c53141
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171336
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra11: clock: Fix system bus clock rounding
Alex Frid [Wed, 12 Dec 2012 01:24:16 +0000]
ARM: tegra11: clock: Fix system bus clock rounding

Made sure system bus clock (SCLK) round rate operation follows the
same policy on fractional divisors as set rate operation - either both
operations allow fractions, or both does not support them (otherwise,
clock rate stats are confused).

Change-Id: I3814d66905c01f2ff84b0402be9b9a3d0b113fd6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171213
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: dma-mapping: Skip cache_maint if !page
Hiroshi Doyu [Thu, 13 Dec 2012 12:40:52 +0000]
ARM: dma-mapping: Skip cache_maint if !page

cache_maint shouldn't be done against !page. Skip cache_maint with
attr.

Bug 1182882
Bug 1024594

Change-Id: I3d9c46febd95d3c6a71f267f26063b95981bd4bc
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/170993
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: tegra: pcie: check return value
Sri Krishna chowdary [Thu, 13 Dec 2012 11:17:21 +0000]
arm: tegra: pcie: check return value

coverity id: 20824

Bug 1046331

Change-Id: I2968097ec817101df8566b3e3889d0410e936f9a
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/170966
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra11: dvfs: Add 1.2V core voltage entry
Alex Frid [Thu, 13 Dec 2012 04:54:05 +0000]
ARM: tegra11: dvfs: Add 1.2V core voltage entry

Bug 1161126

Change-Id: I95703e50adff2a75e89802de31af4969fd34cba3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170866
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Update LP CPU tables and bins
Alex Frid [Thu, 13 Dec 2012 04:32:10 +0000]
ARM: tegra11: dvfs: Update LP CPU tables and bins

Bug 1161126

Change-Id: I994cb995b9f39f5e315ed04dde722bbb31364139
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170865
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: dvfs: Update SCLK, VI, Host1x tables and bins
Alex Frid [Thu, 13 Dec 2012 04:06:35 +0000]
ARM: tegra11: dvfs: Update SCLK, VI, Host1x tables and bins

Bug 1161126

Change-Id: I24793b8c8c6f1fcdc4947a24e96b1550b7963abf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170864
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: dvfs: Update cbus modules tables and bins
Alex Frid [Thu, 13 Dec 2012 02:52:20 +0000]
ARM: tegra11: dvfs: Update cbus modules tables and bins

Bug 1161126

Change-Id: I5a34a7c1513728d487195ec3090bd20882e6c4f0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170863
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Set speedo ID in core dvfs table
Alex Frid [Thu, 13 Dec 2012 01:13:33 +0000]
ARM: tegra11: dvfs: Set speedo ID in core dvfs table

Allow to set speedo id for each core dvfs table entry, instead
of common default -1 (don't care) setting. For now it is still
set to -1 for all entries.

Bug 1170986
Bug 1161126

Change-Id: I10d34266429f54605506ac1ee5d72666ee5e02d5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170862
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: board: Add missing tegra_smmu_init()
Hiroshi Doyu [Wed, 12 Dec 2012 07:51:33 +0000]
ARM: tegra: board: Add missing tegra_smmu_init()

Add missing tegra_smmu_init() for T30+ boards

Bug 1182882
Bug 1024594

Change-Id: I02396fa52cee90efd06eb5c1dafca4ed1f99f2a3
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/170397
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: dvfs: Add CL-DVFS cooling device
Alex Frid [Fri, 7 Dec 2012 02:44:06 +0000]
ARM: tegra11: dvfs: Add CL-DVFS cooling device

Added CL-DVFS cooling device to keep operational voltage at cold
temperature above specified minimum threshold.

Bug 1177204

Change-Id: I31240ef7be6a28f18b401b89a90d4c38e3dad103
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169925
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoRevert "ARM: Revert "ARM: 6878/1: fix personality flag propagation across an exec""
Aly Hirani [Thu, 6 Dec 2012 05:00:23 +0000]
Revert "ARM: Revert "ARM: 6878/1: fix personality flag propagation across an exec""

This reverts commit 25cd08cd1fb5888fe0d9bcc1e58b9d6b8378e1fd.
ADDR_COMPAT_LAYOUT is set on zygote to prevent Unity games from
crashing in K3.4. However, since the propagation of personality was
disabled, this flag never ended up being set on the fork()ed
processes.

Additionally, in order to prevent Bug 894472 to resurface with this
revert, mask out READ_IMPLIES_EXEC from being propagated to child
processes.

Bug 1023189

Change-Id: I01d5b7b3778b9e99815146bd2345bda1266e6309
Signed-off-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-on: http://git-master/r/168956
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Liang Cheng (SW) <licheng@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoARM: Tegra: Turn off SD phase in for T114
Mitch Luban [Fri, 16 Nov 2012 01:05:21 +0000]
ARM: Tegra: Turn off SD phase in for T114

Recently, on T114 we enabled SD updates on vpulse2 instead of
vblank. As a result, it no longer necessary to have
software or hardware phase in enabled.

Bug 1156207

Reviewed-on: http://git-master/r/166641

Change-Id: Ib398284cb708ad212ea22772bc454092036bc329
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/164163
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: isomgr: Init isomgr early.
Krishna Reddy [Thu, 13 Dec 2012 21:51:53 +0000]
arm: tegra: isomgr: Init isomgr early.

Init isomgr earlier than device drivers.

Change-Id: I9b8b080a9f0e72ebae91c0557270624ac030d883
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/171166
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Fix XUSB HS clock initialization
Alex Frid [Fri, 14 Dec 2012 03:19:13 +0000]
ARM: tegra11: clock: Fix XUSB HS clock initialization

XUSB HS clock initialization overwrote XUSB SS clock source settings
(both clocks share the source register). This is fixed now.

Change-Id: I722e55933534a954fde1012d88907ab7340dc81d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/171272
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: mm: Remove unnecessary CMO in Cortex A15 startup
Bo Yan [Wed, 12 Dec 2012 19:18:35 +0000]
ARM: mm: Remove unnecessary CMO in Cortex A15 startup

Cortex-A15 flush L2 cache after reset, there is no need to do this
in software, if L2 is already invalidated in bootloader and
cache is disabled. For secondary startup, there is no reason to
flush L2 as well.

This change assumes the setup code is always entered as the result
of CPU reset.

Change-Id: I6d58f8b4a638b70acfb35b97c87a09266aceef41
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/170563
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: Tegra: Roth: Update Configs for New Boards
Laxman Dewangan [Thu, 13 Dec 2012 11:25:35 +0000]
ARM: Tegra: Roth: Update Configs for New Boards

Update KBC and Left Speaker for A01 P2454 and A02 P2453

Change-Id: I39782086d8b257b8570456580a01f64a7185b991
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/170969
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoasoc:tegra: fix dam cif programming
Dara Ramesh [Thu, 13 Dec 2012 09:48:24 +0000]
asoc:tegra: fix dam cif programming

as per dam spec file chout is fixed to 32bits
so accept chout and ch1 input as 32bit always.

Change-Id: If1de02c2634fca45b4ffc1a51b8f75161e5a2645
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/170931
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Scott Peterson <speterson@nvidia.com>

5 years agocdc_ncm: fix bind failures for Icera devices
Neil Patel [Wed, 12 Dec 2012 20:00:48 +0000]
cdc_ncm: fix bind failures for Icera devices

The Icera 5AN, 5AN BSD, and Nemo devices are composite devices that
include a NCM interface. Therefore, the NCM match flags should have
the VID, PID, Class, Subclass, and Protocol set to avoid bind()
failures for non-NCM interfaces.

Bug 1197415

Change-Id: If68a6ffaa4e1871c6a22ec8839806949804f502c
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/170576
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
Tested-by: David Norman <dnorman@nvidia.com>

5 years agopower: max17042: added shutdown functionality
Gaurav Batra [Tue, 20 Nov 2012 00:24:29 +0000]
power: max17042: added shutdown functionality

Change-Id: Ie0ec4e2970c645decde1c50e9858c9d4b2c41fd8
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/164812
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: t114: pinmux lp0 sequence with NOR_BOOT fix
aghuge [Fri, 14 Dec 2012 05:59:22 +0000]
ARM: tegra: t114: pinmux lp0 sequence with NOR_BOOT fix

Programming pinmux to avoid pad glitches during LP0.
Added fix for NOR_BOOT hang issue.

Bug 1053587

Change-Id: I6338f2e4fa621f2216dbe83e7bcccca4567973be
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/161226
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoarm: errata: 761320: Full cache line writes to the same memory region from at least...
Krishna Reddy [Wed, 12 Dec 2012 20:16:46 +0000]
arm: errata: 761320: Full cache line writes to the same memory region from at least two processors might deadlock processor

Under very rare circumstances, full cache line writes
from (at least) 2 processors on cache lines in hazard with
other requests may cause arbitration issues in the SCU,
leading to processor deadlock. This erratum can be
worked around by setting bit[21] of the undocumented
Diagnostic Control Register to 1.

Change-Id: I83f919ead5ef4f90f50fa3f38f2cc31ab6bfc31e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/170582
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra11: clock: Optimize traversing EMC DFS table
Alex Frid [Sun, 9 Dec 2012 06:39:09 +0000]
ARM: tegra11: clock: Optimize traversing EMC DFS table

Used last rounded EMC DFS table index to skip unnecessary
looping through the table.

Bug 1188643

Change-Id: I0dad723f2f6f58258fd79e33d95d7502ff0abf67
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170605
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Skip lowering voltage on EMC backup
Alex Frid [Sun, 9 Dec 2012 02:42:41 +0000]
ARM: tegra11: clock: Skip lowering voltage on EMC backup

If EMC backup rate is below current rate, skip lowering voltage when
switching to backup clock source, Final voltage will be set correctly
after main clock source is re-locked, and EMC clock is switched to
main source.

Bug 1188643

Change-Id: I82a4a85449dbd589c7692f6640e1bd5e08e0bc9b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170604
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoarm: tegra: enable arm errata 761320 for T2 and T3.
Krishna Reddy [Wed, 12 Dec 2012 20:21:05 +0000]
arm: tegra: enable arm errata 761320 for T2 and T3.

Change-Id: Ifc5b2344875b33eccdc30896255f88b7c6b3bd47
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/170583
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra: Rework timer for clusterswitching
Peter De Schrijver [Wed, 12 Dec 2012 16:44:10 +0000]
ARM: tegra: Rework timer for clusterswitching

This patch introduces a separate timer for clusterswitching. The timer will
queue the usual workitem on expiry. This allows all other operations to
happen immediately without having to cancel a delayed workitem. It also allows
the timer itself to be canceled when the conditions for a clusterswitch are
no longer fulfilled.

bug 1178947

Change-Id: Ieb63baf5a38ebcca29ad938365e46530f755a105
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/170533
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoregulator: bq24192: Disable supply by default
Rakesh Bodla [Tue, 11 Dec 2012 14:44:10 +0000]
regulator: bq24192: Disable supply by default

Disable voltage supply by default.

Bug 1179219

Change-Id: I6b157c7146f7a014099e9a142461b9130a7e3da1
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/170130
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: pluto: fix LP0 resume handling error for wake0
Neil Patel [Mon, 10 Dec 2012 21:58:34 +0000]
arm: tegra: pluto: fix LP0 resume handling error for wake0

During resume from LP0 due to MDM_COLDBOOT going low,
tegra_wake_to_irq() returns an error after seeing -EINVAL at index
0 of the tegra_wake_event_irq array. Since a gpio wake source is
mapped to index 0 in the tegra_gpio_wakes array, the value should
be -EAGAIN.

Bug 1195187

Change-Id: I534002727f0956867d5fdb182af2e63c1f023f0e
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/169809
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoarm: tegra: isomgr: cleanup isomgr implementation.
Krishna Reddy [Mon, 10 Dec 2012 19:29:30 +0000]
arm: tegra: isomgr: cleanup isomgr implementation.

Add more comments.

Change-Id: I42ea1accfac673231224b522fc4d41cf23837562
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/169778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agoARM: tegra: gizmo: Fix prefetch CFG5 address
Pavan Kunapuli [Mon, 10 Dec 2012 08:41:07 +0000]
ARM: tegra: gizmo: Fix prefetch CFG5 address

Fixing prefetch CFG_5 register address offset
Using AHB prefetcher for SDMMC only on T114 and
T148 SOCs. SDMMC controller is removed from AHB
interface in later versions of Tegra.

Bug 1188541

Change-Id: Id74dc3839b80e0e394a589916d0669ae935125ef
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/169657
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra: dalmore: update emc DVFS table
Ray Poudrier [Thu, 6 Dec 2012 02:33:31 +0000]
ARM: tegra: dalmore: update emc DVFS table

Bug 1189313

Change-Id: I17db9a8cfd896e2125d495d74f9fc61d4ce2729f
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/168927
Tested-by: Hunk Lin <hulin@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoUSB: gadget: f_mtp: allocate mtp buffers using dma
Rohith Seelaboyina [Tue, 27 Nov 2012 06:15:37 +0000]
USB: gadget: f_mtp: allocate mtp buffers using dma

Allocate mtp_requests using dma

Bug 1158861

Change-Id: Ib12f7b9dc686e967f8d3e9603e4dc9ba7bcdf3f1
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/161615
(cherry picked from commit 5eca89ad1da23de729f5ae8a4077f6d5cb19db7d)
Reviewed-on: http://git-master/r/168692
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: t11x: Enable hazard detection timeout
Bo Yan [Mon, 3 Dec 2012 18:22:41 +0000]
ARM: t11x: Enable hazard detection timeout

bug 1159132

Change-Id: Ie7987f590926a9c246e8b3312020af406d1ac7ef
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/168101
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoarm: tegra: enable deferred cache maintenance
Kirill Artamonov [Wed, 21 Nov 2012 16:44:11 +0000]
arm: tegra: enable deferred cache maintenance

Enable deferred cache maintenance optimization.

bug 983964
bug 994226

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I4f7128392e2c790386b52790fa8fc88bda93910e
Reviewed-on: http://git-master/r/165464
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoarm: tegra: config: Enable bq2419x charger driver
Syed Rafiuddin [Wed, 12 Dec 2012 11:57:01 +0000]
arm: tegra: config: Enable bq2419x charger driver

Enable bq2419x battery charger driver

Bug 1179923

Change-Id: Ie7453b7f13167733fa924c810377cee3f68d149b
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/170516
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: dvfs: Update CPU dvfs tables and bins
Alex Frid [Wed, 12 Dec 2012 05:19:04 +0000]
ARM: tegra11: dvfs: Update CPU dvfs tables and bins

Based on characterization results:
- Integrated new cvb dvfs coefficients
- Expanded DFLL operating voltage range to 0.9V ... 1.35V with
  1.0V as dynamic tuning threshold
- Added speedo_id 2 to differentiate fast parts
- Duplicated CPU EDP table for new speedo_id

Bug 1170986
Bug 1178825
Bug 1161126

Change-Id: I49ccdb7c3d734dcdd3bb9f2542683d418d21ab5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170368
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Restore SCLK and HCLK rate limits
Alex Frid [Tue, 11 Dec 2012 06:54:05 +0000]
ARM: tegra11: clock: Restore SCLK and HCLK rate limits

Set back minimum 12 MHz rate for system and AHB clocks (SCLK and
HCLK) - partial revert of cf02b47b2dfdbe1e19a40df6bd28620a0c422ce9
Bug 1057646 requires HCLK:PCLK 2:1 ratio only starting from 60MHz.

Change-Id: Ic82cac35b9861dccbc66b29c9d507c1100c73d7c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169967
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: isomgr: add null implementaion for isomgr api
Krishna Reddy [Mon, 10 Dec 2012 19:20:25 +0000]
arm: tegra: isomgr: add null implementaion for isomgr api

this is to handle isomgr config option disable case.

Change-Id: I37ad6e60005a631aeb1295bf6282a9a3aadb78e1
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/169777
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agobluesleep: it should depend on Tegra HSUART
Mursalin Akon [Fri, 7 Dec 2012 22:56:51 +0000]
bluesleep: it should depend on Tegra HSUART

blueseep has code dependency on Tegra HSUART.
KConfig should reflect that dependency.

Bug 1193147

Change-Id: I66fe597f9554138c5387b2e070238cdf81b5cf32
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/169514
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agotty: serial: tegra: Export symbols for bluesleep
Mursalin Akon [Fri, 7 Dec 2012 21:33:26 +0000]
tty: serial: tegra: Export symbols for bluesleep

The bluesleep modules uses couple of symbols
which are not exported. As a result, bluesleep
cannot be built as module.

Bug 1193147

Change-Id: I47bc31cb6ff525e346df29264698031fd94032c7
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/169513
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoARM: config: tegra11: enable PWM_FAN config
Anshul Jain [Sat, 8 Dec 2012 01:04:46 +0000]
ARM: config: tegra11: enable PWM_FAN config

bug 1179033

Change-Id: Ib3ec36bca0ceec6d260c3d5e093b5dda7c2f42b6
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/169234
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: config: tegra11: enable FAN_THERM_EST config
Anshul Jain [Tue, 11 Dec 2012 22:31:22 +0000]
ARM: config: tegra11: enable FAN_THERM_EST config

Bug 1159205

Change-Id: Ic17a7344387ac3eaa507ac5d144fde8a750d28df
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/169223
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra11: dvfs: Add CPU rail DFLL mode trip-point
Alex Frid [Thu, 6 Dec 2012 07:41:19 +0000]
ARM: tegra11: dvfs: Add CPU rail DFLL mode trip-point

Added CPU rail DFLL mode trip-point necessary to limit minimum CPU
voltage at cold temperature. The respective cooling device is not
implemented, yet.

Bug 1177204

Change-Id: I6abe1bc3ace81935c25968385af1998052455da0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/168999
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agogpio: tegra: add tegra_is_gpio
aghuge [Tue, 4 Dec 2012 11:36:27 +0000]
gpio: tegra: add tegra_is_gpio

Added tegra_is_gpio function to
return true if pin is configured as gpio

Bug 1172972

Change-Id: Ieac0af9a6ee000cbeb73e714395169799ae18e3b
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/168285
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: tegra: Dalmore: Shutdown SMPS
Prem Sasidharan [Tue, 27 Nov 2012 22:25:22 +0000]
arm: tegra: Dalmore: Shutdown SMPS

Shutdown SMPS8 in LP0

Bug 1176125

Change-Id: I78a67a74da12d3bb7e9ab375652e84f1a65491a3
Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com>
Reviewed-on: http://git-master/r/166694
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: Initial runtime pre-silicon support
Jeff Smith [Fri, 3 Aug 2012 22:11:17 +0000]
ARM: tegra: Initial runtime pre-silicon support

* Add runtime calls to determine pre-silicon config
* Determine mode from minor revision in tegra id
* Export mode through fuse sysfs for user mode tests/code

Change-Id: I500d4ae14b70322f558ab48634fb758d3014bca2
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161324
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: Add PRE_SILICON_SUPPORT option
Jeff Smith [Thu, 2 Aug 2012 23:14:53 +0000]
ARM: tegra: Add PRE_SILICON_SUPPORT option

New option for enabling pre-silicon quirks and
differentiating between the various supported
platforms at run time instead of compile time.

After all features are ported from the PLATFORM
config, that option will be removed.

Change-Id: I0b1fcd1425a95bfb48ac4f64e306b4503955ac4f
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161287
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agomedia: video: tegra: nvavp: Fix nvmap handle issue
Gajanan Bhat [Wed, 12 Dec 2012 20:06:04 +0000]
media: video: tegra: nvavp: Fix nvmap handle issue

In open call we were assigning the driver's nvmap handle to
the nvavp's client context which would get released in release
call to driver. This will cause driver's nvmap handle to be
invalid if a parallel client context is running and driver does
any nvmap operation.

Bug 1013063
Bug 1192772

Change-Id: Id02520ae8ec511bb8c50bc4d3908ea3e75e1ea6b
Signed-off-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-on: http://git-master/r/170585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agodrivers: tegra: imx091/max77665: fix edp issue
Charlie Huang [Tue, 11 Dec 2012 20:17:10 +0000]
drivers: tegra: imx091/max77665: fix edp issue

Fix the potential NULL pointer usage in the case there is no edp client
allocated.

bug 1193275

Reviewed on: http://git-master/r/#change,170249

Change-Id: I8cf6670edfd8ddd8f60a5200efe80a49767296bf
(cherry picked from commit 4be68a5750f55ea9b8e1062d6d2b6789891ee371)

Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Change-Id: Iabb40765c7f5b935bb5938c24397fda54581638f
Reviewed-on: http://git-master/r/170560
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: Tegra: Print raw MC error code
Antti P Miettinen [Wed, 12 Dec 2012 14:04:19 +0000]
ARM: Tegra: Print raw MC error code

Print raw error code too for better diagnostic.

Change-Id: Iaf1268eeff3ad1077a6035755302fde1c650e76e
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/170558
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomedia: video: tegra: imx091: Fix pll_mult value
Sudhir Vyas [Wed, 12 Dec 2012 08:56:04 +0000]
media: video: tegra: imx091: Fix pll_mult value

The pll_mult value for imx091 new mode [524x390]
is incorrectly set. Which is being used to derive
VtPixelClk and later this clock is used to calculate
coarse-time, frame-length and frame-rate, hence all
are being calculated to wrong values.
Slow-mo faces the incorrect fps issue when same mode
needs to be programmed with different fps.

Bug 1180474

Change-Id: I673f6ad77fbb52225c0b427f5c78bd53bc473bea
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/170414
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Purwar <apurwar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM: Tegra: Fix MC error reporting
Antti P Miettinen [Wed, 12 Dec 2012 07:33:44 +0000]
ARM: Tegra: Fix MC error reporting

Check that array indexing is within bounds.

Change-Id: I36f4edf1567eec395a16c46711b3b25ead88cf98
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/170384
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: Skip unnecessary L1 flush for all tegra chips
Bo Yan [Mon, 10 Dec 2012 18:32:13 +0000]
ARM: tegra: Skip unnecessary L1 flush for all tegra chips

Change-Id: I52b7ae07c42f0f76b5e1e6d8564c9cb518c359a6
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/169768
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: tegra: usb_phy: Fix race condition in resume
Abhishek Shukla [Sun, 9 Dec 2012 02:50:35 +0000]
arm: tegra: usb_phy: Fix race condition in resume

Resume could fail if remote wake is detected
by  PMC after controller has been put in suspend
during resume code. Restart bringing up host
controller as in case of remote wake if this hapens.

Bug 1179329

Change-Id: I7df4fcb73c565aedc4b22ff9cf229d3b50b99d15
Signed-off-by: Abhishek Shukla <abhisheks@nvidia.com>
Reviewed-on: http://git-master/r/169602
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoALSA: hda: powergate HDA when clock gating
Jon Mayo [Fri, 7 Dec 2012 01:19:51 +0000]
ALSA: hda: powergate HDA when clock gating

Use powergating APIs to ensure that HDA and display play nice.
Export powergate APIs so snd-intel-hda can be built as a module.

Bug 1178366

Change-Id: I30559b9288fcbd86615a674756e70f04c9fb5d83
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/169245
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: tegra: dalmore: Runtime panel detection
Vineel Kumar Reddy Kovvuri [Thu, 6 Dec 2012 12:31:33 +0000]
arm: tegra: dalmore: Runtime panel detection

Bug 1182416

Change-Id: I362f892c32e0f3e8e32e136b3595c71b696b2bae
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/169066
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Don't preset EMC VREF bits
Alex Frid [Tue, 11 Dec 2012 01:13:35 +0000]
ARM: tegra11: clock: Don't preset EMC VREF bits

Don't preset VREF bits in XM2DQSPADCTRL3 registers during EMC clock
change procedure.

Change-Id: I3abb6d07d93632b61363e2b0f7de37e1d7312af0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Use tabulated EMC clock register
Alex Frid [Fri, 7 Dec 2012 23:58:59 +0000]
ARM: tegra11: clock: Use tabulated EMC clock register

Instead of constructing settings for EMC clock source/divider
register, use value specified in the EMC DFS table.

Bug 1188643

Change-Id: I4d28ed00c0b049d4ab5ad645cbf721ef6453be8b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169556
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Add latency entry to EMC DFS table
Alex Frid [Thu, 6 Dec 2012 20:44:26 +0000]
ARM: tegra11: clock: Add latency entry to EMC DFS table

Bug 1189313

Change-Id: I4e39647c0c4702f05f03ecd00c82aa568f5fedf6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169138
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agofixup debug clock getting
Dan Willemsen [Fri, 1 Feb 2013 22:29:44 +0000]
fixup debug clock getting

Change-Id: Ieef5ca0d92ae9dce9b32713301c7451d861d5e7e
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoHACK Revert "regulator: core: Mark all DT based boards as having full constraints"
Dan Willemsen [Fri, 1 Feb 2013 00:37:37 +0000]
HACK Revert "regulator: core: Mark all DT based boards as having full constraints"

This reverts commit 86f5fcfc3e400b2ac1562cb0fd6aabc9f83ee3e2.

Change-Id: I2aae15af8f1a648d68e5a1e2a12fdf67208de5bf
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoHACK: disable our delay functions, causing hang
Dan Willemsen [Thu, 31 Jan 2013 10:15:05 +0000]
HACK: disable our delay functions, causing hang

Change-Id: Ic3e2960d29d9ccc51d57fe23a2a0b309f665a12b
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup tegra11x_init_early
Dan Willemsen [Thu, 31 Jan 2013 10:11:17 +0000]
fixup tegra11x_init_early

Change-Id: If124ad54e72cce9c4e241496e55ce014e5bef9e4
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup tegra11_clocks upstream uart changes
Dan Willemsen [Thu, 31 Jan 2013 10:10:02 +0000]
fixup tegra11_clocks upstream uart changes

Change-Id: I5908329b69e681171bf91123611aa4b6369dc751
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup tegra11_clocks pwm driver name
Dan Willemsen [Thu, 31 Jan 2013 10:09:49 +0000]
fixup tegra11_clocks pwm driver name

Change-Id: I2a4c4cd7ea691033b9f2211c84511a8badaaea96
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup tegra11_clocks apbdma driver name
Dan Willemsen [Thu, 31 Jan 2013 10:09:28 +0000]
fixup tegra11_clocks apbdma driver name

Change-Id: I53a61011c96b3f03d71451658cf37c194786459b
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup sound tegra30_i2s regmap changes
Dan Willemsen [Thu, 31 Jan 2013 07:26:15 +0000]
fixup sound tegra30_i2s regmap changes

incomplete, but a start

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup tegra_rt5640 compile
Dan Willemsen [Thu, 31 Jan 2013 07:19:01 +0000]
fixup tegra_rt5640 compile

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup hda_intel platform driver
Dan Willemsen [Thu, 31 Jan 2013 07:14:37 +0000]
fixup hda_intel platform driver

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup hda_intel pci driver
Dan Willemsen [Thu, 31 Jan 2013 07:14:10 +0000]
fixup hda_intel pci driver

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup hda_intel pci
Dan Willemsen [Thu, 31 Jan 2013 07:13:00 +0000]
fixup hda_intel pci

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agousb: otg: tegra: Updates for 3.6
Dan Willemsen [Thu, 31 Jan 2013 07:10:39 +0000]
usb: otg: tegra: Updates for 3.6

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup usb: host: tegra: update ehci to use common phy
Dan Willemsen [Thu, 31 Jan 2013 07:06:05 +0000]
fixup usb: host: tegra: update ehci to use common phy

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup usb: host: tegra: update ehci to use common phy
Dan Willemsen [Thu, 31 Jan 2013 07:02:11 +0000]
fixup usb: host: tegra: update ehci to use common phy

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agousb: gadget: tegra: Updates for 3.6
Dan Willemsen [Thu, 31 Jan 2013 06:59:25 +0000]
usb: gadget: tegra: Updates for 3.6

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup regulator: palma: Disable smps10 boost during suspend
Dan Willemsen [Thu, 31 Jan 2013 06:52:57 +0000]
fixup regulator: palma: Disable smps10 boost during suspend

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoARM: config: tegra11_android: Run savedefconfig
Dan Willemsen [Thu, 31 Jan 2013 05:56:16 +0000]
ARM: config: tegra11_android: Run savedefconfig

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup: mfd: max77663: mfd_add_devices addition
Dan Willemsen [Thu, 31 Jan 2013 05:31:26 +0000]
fixup: mfd: max77663: mfd_add_devices addition

See 0848c94fb4a5cc213a7fb0fb3a5721ad6e16f096

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup: mfd: max8831: mfd_add_devices addition
Dan Willemsen [Thu, 31 Jan 2013 05:26:04 +0000]
fixup: mfd: max8831: mfd_add_devices addition

See 0848c94fb4a5cc213a7fb0fb3a5721ad6e16f096

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup: mfd: bq2419x: mfd_add_devices addition
Dan Willemsen [Thu, 31 Jan 2013 05:25:10 +0000]
fixup: mfd: bq2419x: mfd_add_devices addition

See 0848c94fb4a5cc213a7fb0fb3a5721ad6e16f096

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup timer
Dan Willemsen [Thu, 31 Jan 2013 05:11:38 +0000]
fixup timer

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup timer arch_timer registration
Dan Willemsen [Thu, 31 Jan 2013 05:10:28 +0000]
fixup timer arch_timer registration

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup: crypto: testmgr - Adding ofb(aes) and cmac(aes) tests
Dan Willemsen [Thu, 31 Jan 2013 05:09:10 +0000]
fixup: crypto: testmgr - Adding ofb(aes) and cmac(aes) tests

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoARM: PCI: remove unused sys->hw
Dan Willemsen [Mon, 14 Jan 2013 22:31:17 +0000]
ARM: PCI: remove unused sys->hw

See upstream commit 8084de8ad53332ed6e0ffe5db85533b8150d7d6b

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup: tegra30_i2s compile fix
Dan Willemsen [Mon, 14 Jan 2013 05:04:23 +0000]
fixup: tegra30_i2s compile fix

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup/HACK sound changes
Dan Willemsen [Mon, 14 Jan 2013 04:05:30 +0000]
fixup/HACK sound changes

* switch to regmap
* switch to runtimepm
* remove hand register cache (may need to move to regmap)
* rename txcif/rxcif
* disable i2s due to not being updated for DT, where upstream requires
   DT

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agofixup hda_intel.c: compiler errors due to function split
Dan Willemsen [Mon, 14 Jan 2013 02:31:24 +0000]
fixup hda_intel.c: compiler errors due to function split

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

5 years agoRevert "LOOK Partial Revert "ALSA: hda: Support disabling of clocks for Tegra""
Dan Willemsen [Mon, 14 Jan 2013 02:25:20 +0000]
Revert "LOOK Partial Revert "ALSA: hda: Support disabling of clocks for Tegra""

This reverts commit a70fbb1efdf02c50699576f6e67c030dc2d5ceca.

5 years agofixup boot_hsic_class: Convert to dev_err
Dan Willemsen [Mon, 14 Jan 2013 02:08:21 +0000]
fixup boot_hsic_class: Convert to dev_err

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>