5 years agoARM: tegra: dvfs: Add predict peak voltage interface
Alex Frid [Tue, 8 Oct 2013 00:17:47 +0000]
ARM: tegra: dvfs: Add predict peak voltage interface

With introduction of thermal dvfs, frequency-to-voltage mapping may
be changed at run time with temperature. Therefore, s/w layers that
rely on inverse voltage-to-frequency tables to determine frequency
caps, should use peak voltages across all thermal dvfs ranges. Hence,
this commit:
- added the respective peak_millivolts entry in dvfs structure
- added tetra_dvfs_predict_peak_millivolts() interface
- modified EDP table calculation to use peak voltage prediction
- modified core cap table construction to use peak voltage prediction,
changed warning reported when voltage for minimum frequency is above
core Vmin to info - this maybe true in some thermal dvfs range
- modified override range calculation to use peak voltage prediction,
added dvfs safe-guard in rail override mode to make sure that override
limit is not violated in any thermal range

For now, dvfs peak millivolts entries are not populated at all, and
predicted peak voltage are based on dvfs table active at the moment in
current thermal range (the same as standard predict voltage interface).

Bug 1307919

Change-Id: Ia8d962c66efbcb98d227dab55b36bbba8d93ef5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/289480
Reviewed-on: http://git-master/r/298527
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Fix pll_c_out1 flags
Kaz Fukuoka [Tue, 1 Oct 2013 00:51:39 +0000]
ARM: tegra12: clock: Fix pll_c_out1 flags

Ported from Tegra11 change I899cf5b6d04cc27f63de7f01fb7aa78636e61ea6

Change-Id: I9a8808bc1cf09846b928abf74aa743352fb23bf9
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/299004
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Use AVP clock integer divisor
Kaz Fukuoka [Wed, 25 Sep 2013 23:32:47 +0000]
ARM: tegra12: clock: Use AVP clock integer divisor

Only integer divisors are allowed from now on for AVP/SCLK clock
sources.

Ported from Tegra11 Change-Id: I5d846e8c304c18cff2e2da5a8ff2d2ed821ea727

Change-Id: I1b2f1d39e0a0800bbf96ecbe163b56a6cc674ad9
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/299003
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: add utmip-pad clock entry for xusb
Kaz Fukuoka [Thu, 26 Sep 2013 23:54:59 +0000]
ARM: tegra12: clock: add utmip-pad clock entry for xusb

utmip-pad entry was missing for xusb and so devm_clk_get is
failing. Adding the same for xusb interface.

Ported from Tegra11 Change-Id: I257fccf974bc5bededbe0a5c3e96d171ad4f5077

Change-Id: I0fbe00be4d181ff8dfd7a1a9125c42d7c0463a8d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298507
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: Modify temperature margins for T12x
Diwakar Tundlam [Thu, 17 Oct 2013 22:25:07 +0000]
ARM: tegra: Modify temperature margins for T12x

Temperature threshold Values taken from new tegra12x margining
spreadsheet.

Updated Shield-ERS and Loki board-files with thresholds for T580 SKU
and Laguna board-file with thresholds for T570 SKU.

Bug 1393423

Change-Id: I3044fc6e571f81d0ddc09a5ff14469c411e8dd1a
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/299048

5 years agoRevert "staging: iio: adc: palmas: add DT support"
Sridhar Lavu [Tue, 22 Oct 2013 16:34:56 +0000]
Revert "staging: iio: adc: palmas: add DT support"

This reverts commit a90856a6626d502d42c6e7abccbdf9d730b36270
since it introduces automated sanity regression

Bug 1393292 : sanity regression

Change-Id: I6e2990d69a6f3566e1dd96f893fedcae49947133
Signed-off-by: Sridhar Lavu <slavu@nvidia.com>
Reverts-what-was-Reviewed-on: http://git-master/r/302361
Reviewed-on: http://git-master/r/302416
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: edid: Verify checksum of edid
Mike J. Chen [Tue, 1 Oct 2013 01:36:19 +0000]
video: tegra: edid: Verify checksum of edid

We've seen invalid edid reads and should retry instead
of using it.

Change-Id: I7d74a41f702be02464c7f43904805142153d4da0
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/301312
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: clock: Keep PLL_REFE enabled during init
Kaz Fukuoka [Tue, 1 Oct 2013 00:26:59 +0000]
ARM: tegra12: clock: Keep PLL_REFE enabled during init

Enabled PLL_REFE in early kernel initialization, to provide clock for
h/w sequencers initialization. PLL is disabled in late init.

Ported from Tegra11 change Ie79a3f0989fb3a40714659c7ed082dce2d004d5c

Change-Id: I056f40e1410668fd494e474e1ba56af9a43545ef
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298502
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agostaging: iio: adc: palmas: add DT support
Laxman Dewangan [Tue, 22 Oct 2013 12:40:27 +0000]
staging: iio: adc: palmas: add DT support

Add DT support for the Palmas ADC driver.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
(Cherrypicked commit b11a33b8a6d95d0e5e5f27d0854fc053c2fbeb6f)

Change-Id: I4e5a3df1e72f388cf56dbd97f2485af105202659
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/302361
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: add port FF to GPIO ID's for T124
Ashwini Ghuge [Tue, 22 Oct 2013 08:40:17 +0000]
ARM: tegra: add port FF to GPIO ID's for T124

Change-Id: I6aa539b0073731bf047b4b611ab3bb3345952535
Reviewed-on: http://git-master/r/302217
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: ardbeg: Add versioned dts file
Nitin Kumbhar [Fri, 6 Sep 2013 06:47:46 +0000]
ARM: tegra: ardbeg: Add versioned dts file

Add a new dts file for latest ardbeg fab version.

Bug 1056577

Change-Id: I24f00ef024179f806fcbc93867c1640ffb8776fd
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/288884
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: pcie: Apply CLKREQ# WAR for PM358/9
Jay Agarwal [Tue, 22 Oct 2013 07:27:12 +0000]
ARM: tegra: pcie: Apply CLKREQ# WAR for PM358/9

CLKREQ# WAR is not supported on PM358/9 platforms
Apply WAR to always enable refclk for these only.

Bug 1356695

Change-Id: Iaa97c4964f0f3ac0295a8a1172c037e713f332c0
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/302175
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: add regulator supply properties for gyro and compass on DT
Laxman Dewangan [Tue, 22 Oct 2013 10:03:24 +0000]
ARM: tegra: add regulator supply properties for gyro and compass on DT

Gyro and compass drivers are registerd from DT and so adding the
power supply properties of these devices in dt node.

Removing the non-required entry in regulator consumer as client driver
moved to DT.

Change-Id: Iecf14ee819a8c1dcd42d041472f734189492350d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/289157

5 years agovideo: tegra: host: Enable ISP & VI power gating
Terje Bergstrom [Thu, 26 Sep 2013 11:29:02 +0000]
video: tegra: host: Enable ISP & VI power gating

Change-Id: I03e86e1ccbf7d4ac81596a6babb1066e7bae4c65
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288830

5 years agovideo: tegra: host: Fix race in gr3d scaling
Arto Merilainen [Tue, 1 Oct 2013 12:33:24 +0000]
video: tegra: host: Fix race in gr3d scaling

The scaling code used cancel_work_sync() while holding a mutex. As the work
itself uses the same mutex, we risk causing a deadlock.

This patch refactors the code so that the mutex is not hold while calling
cancel_work_sync().

Bug 1371500

Change-Id: I3aa0de168cebcc1d8d1843813caee5e82fe3df06
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/280730
(cherry picked from commit 763125fba1c9a8a67a9968c8502c17465665eb35)
Reviewed-on: http://git-master/r/289051
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agostaging: iio: light: stm8t143: hide prints
Sri Krishna chowdary [Mon, 21 Oct 2013 12:35:02 +0000]
staging: iio: light: stm8t143: hide prints

proximity values were printed to check the
frequency of updates during sensor bringup.
Not required now, hence change pr_info to pr_debug.

Bug 1362876

Change-Id: I4435c5be9e6c287782ff871ea3d80da86677f78e
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/301790
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agocpufreq: don't leave stale policy pointer in cdbs->cur_policy
Jacob Shin [Thu, 27 Jun 2013 20:02:12 +0000]
cpufreq: don't leave stale policy pointer in cdbs->cur_policy

Clear ->cur_policy when stopping a governor, or the ->cur_policy
pointer may be stale on systems with have_governor_per_policy when a
new policy is allocated due to CPU hotplug offline/online.

[rjw: Changelog]
Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

(cherry picked from commit 419e172145cf6c51d436a8bf4afcd17511f0ff79)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Change-Id: Iada00880f8c98ed1beb372bf4b84ff9a7d43e3ea
Reviewed-on: http://git-master/r/300402
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoasoc: rt5639: Update drivers
Scott Peterson [Thu, 10 Oct 2013 22:56:08 +0000]
asoc: rt5639: Update drivers

Update the Realtek rt5639 drivers to
improve the headphone performance.

Change-Id: I32ab81b07c952f8887c629e68e8fdaf52ec6a143
Signed-off-by: Scott Peterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/299697
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Tested-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: create a DT header defining GPIO IDs
Stephen Warren [Wed, 13 Feb 2013 00:24:04 +0000]
ARM: tegra: create a DT header defining GPIO IDs

All Tegra GPIOs are named after the GPIO bank and GPIO number within
the bank. Define a macro to calculate the GPIO ID based on those
parameters. Make the macro available via all Tegra .dtsip files.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
(cherry picked from commit 9798e47ff232c48b3c25b9a6b9395b505e389475)
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>

Change-Id: I7bf7e20b44492da0cb5acba963905027e980b29f
Reviewed-on: http://git-master/r/302216
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: loki: Fix modem pinmux
Raj Jayaraman [Mon, 21 Oct 2013 23:26:03 +0000]
arm: tegra: loki: Fix modem pinmux

Bug 1390847

Change-Id: I4ed1bfa1a5bd86592edd71d51141b2db8b464ee4
Signed-off-by: Raj Jayaraman <rjayaraman@nvidia.com>
Reviewed-on: http://git-master/r/302000
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra12: Update audio pinmux settings
Scott Peterson [Tue, 15 Oct 2013 19:27:49 +0000]
ARM: tegra12: Update audio pinmux settings

Update the audio pinmux settings for Loki

Bug 1382160

Change-Id: I6003da94b4bf1e2989f0ac22d131e27e7036fee1
Signed-off-by: Scott Peterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/299588
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com>
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Remove incorrect RTC node
Ajay Nandakumar [Mon, 21 Oct 2013 09:32:40 +0000]
ARM: tegra: Remove incorrect RTC node

Removing incorrect RTC node as it might cause crashes/hang
if the RTC driver registers with this incorrect node.

Change-Id: Ic8829b3e0341487fee0a481b6e5e9d72618ba2a1
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/301726
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Thor 1.95: Change orientation vector
Xiaohui Tao [Thu, 17 Oct 2013 21:02:06 +0000]
ARM: tegra: Thor 1.95: Change orientation vector

Fake the sensor as if it is on the display. It is the same thing
we did for shield 1.

Bug 1385809

Change-Id: I4f03e8145c26438160a23b56acd30b5b4f872cfd
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/300687
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: tn8: Add a new dts for sensor moudle
Daniel Fu [Wed, 16 Oct 2013 12:51:04 +0000]
ARM: tegra: tn8: Add a new dts for sensor moudle

First version of TN8 using E1794 sensor moudle, but the new TN8
using E1845 sensor moudle. Handle this change with following updates.
- Move E1794 sensors DT entry from common dtsi to tegra124-tn8.dts
- Add new tegra124-tn8-a03-00.dts with E1845 sensors(mpu6515 & ak8963)
- Add nvidia-boardids property to both TN8 dts

Bug 1364407
Bug 1389167

Change-Id: I2975444e7b1fc1c3d407efe27c8eb0b4a170e7f6
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/300019
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Hayden Du <haydend@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

5 years agoARM: Tegra: Cautious debugging in early resume
Antti P Miettinen [Wed, 16 Oct 2013 12:21:30 +0000]
ARM: Tegra: Cautious debugging in early resume

Doing prints early in resume can be costly. Let's use
pr_debug instead of pr_info.

Bug 1381343

Change-Id: I5fdc61e7cc95d0864e2e81e36c8b6b2a425fb356
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/299970
(cherry picked from commit cf28de40659781154ebdfed922900b160912a3ca)
Reviewed-on: http://git-master/r/301523
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: pcie: Fix LP0 Power management WARs
Jay Agarwal [Thu, 3 Oct 2013 13:34:58 +0000]
ARM: tegra: pcie: Fix LP0 Power management WARs

1. Remove the WAR of removing pcie devices in
suspend and creating them from scratch in resume
2. Remove bypassing pcie config space access in
pcie bus noirq suspend/resume calls
3. Convert tegra pcie suspend/resume to noirq calls
except enable_features in resume
4. Make pcie sd4 regulator always ON with external
control
5. Avoid adding pcie host device for runtime power
management as it conflicts with noirq calls

Change-Id: Ia6236f15e124a63a08a36b167a346c8282f5271a
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/300465
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: gk20a: optimize gr ucode load
Prashant Malani [Mon, 30 Sep 2013 23:10:51 +0000]
video: tegra: host: gk20a: optimize gr ucode load

Use a quicker method to start up the fecs and gpccs
falcons. Load a quicker bootstrap routine into the
falcons, and then have the ucode DMAed in by them.

Change-Id: Ibf0c5a851f73a084a2b8af2d2a7f1e3185967922
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/290033

5 years agovideo: tegra: host: gk20a: Improve PMU error stats
Neil Gabriel [Mon, 21 Oct 2013 16:01:00 +0000]
video: tegra: host: gk20a: Improve PMU error stats

To debug FECS-related PMU EXTERR failures, it is necessary to
know the internal FECS error code. This value is stored in
PWR_PMU_BAR0_ERROR upon failure. This change reads that register
and reports its value in PMU error stat messages.

Change-Id: Idefb5312568dfcead478ca237197c801e37fe966
Signed-off-by: Neil Gabriel <ngabriel@nvidia.com>
Reviewed-on: http://git-master/r/301840
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Fix pmu init sequence
Prashant Malani [Mon, 21 Oct 2013 21:18:41 +0000]
video: tegra: host: gk20a: Fix pmu init sequence

The second part of pmu initialization, like the first,
should only be executed if there is PMU support, otherwise
it should return immediately.

Bug 1392583

Change-Id: Ic04994f0a460ea84e08002efa7703f5c0a534f11
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/301960
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: dsi: Enable waiting on sync points
Vineel Kumar Reddy Kovvuri [Thu, 17 Oct 2013 09:05:14 +0000]
video: tegra: dsi: Enable waiting on sync points

Fixes busy wait and enables waiting on sync points

Bug 1367115

Change-Id: I107500fca8e8703a8c5db954c4a74227bd25d475
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/300489
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: ardbeg: make global variables static
Colin Cross [Tue, 15 Oct 2013 22:46:43 +0000]
ARM: tegra: ardbeg: make global variables static

Make global variables static so that board-ardbeg.c can be copied
without causing build failures.

Change-Id: Ic6427991e83b49f55c6fed68f363f6dace95b362
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit AOSP kernel/tegra e3042a7cde16f2ae2eff1f513f16fda5f9648c52)
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/300905

5 years agoARM: tegra: ardbeg: use fiq debugger
Colin Cross [Fri, 11 Oct 2013 23:35:05 +0000]
ARM: tegra: ardbeg: use fiq debugger

Use the fiq debugger instead of the debug serial driver on uartd
when CONFIG_TEGRA_FIQ_DEBUGGER is set.

Change-Id: I4a2d64603fb4734c4103c3f169fd2de01fac2fbb
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit AOSP kernel/tegra 80c73cb8ba3f2368a1746f8e572d8ef4efb8473c)
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/300904

5 years agoARM: tegra: fiq_debugger: add support for irq mode
Colin Cross [Fri, 11 Oct 2013 23:33:59 +0000]
ARM: tegra: fiq_debugger: add support for irq mode

Modern Tegra chips with TrustZone don't currently support fiqs.
Add a function to initialize the fiq debugger in irq mode.

Change-Id: Ia7be1032bbf27110a2f3f434c78351b3186af6f7
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit AOSP kernel/tegra 71377e5e4a9f03080e13a21398082fbd85e6b127)
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/300903
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Courbot <acourbot@nvidia.com>

5 years agoarm: tegra: update cpu edp calculation parameters
Xue Dong [Fri, 18 Oct 2013 22:11:51 +0000]
arm: tegra: update cpu edp calculation parameters

bug 1330937

Change-Id: I34d0fc5ff4a15538417eb216dedd8b93414eba07
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/301412
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarch: config: tegra update mods defconfig
Tope Yang [Thu, 17 Oct 2013 02:32:11 +0000]
arch: config: tegra update mods defconfig

add loki support and CONFIG_NFS_V4
remove TEGRA_GPU_DVFS and CONFIG_ANDROID_PARANOID_NETWORK

Bug 1355741

Change-Id: Ic216227ff2aa55c82e37c465f934fd11812ce8c1
Signed-off-by: Tope Yang <topey@nvidia.com>
Reviewed-on: http://git-master/r/300293
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Anders Ma <andersm@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: host: gk20a: Handle EXTERR intr
Neil Gabriel [Tue, 15 Oct 2013 19:43:23 +0000]
video: tegra: host: gk20a: Handle EXTERR intr

Continue to dump the falcon stats if the interrupt fires as it
is never expected to, but clear the interrupt to avoid an
interrupt storm.

Change-Id: I39f50eff500aec1842bac6f37ec720288decb785
Signed-off-by: Neil Gabriel <ngabriel@nvidia.com>
Reviewed-on: http://git-master/r/299586
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: tegra: clock: Lock DFLL 1st during cluster switch
Alex Frid [Tue, 15 Oct 2013 03:09:39 +0000]
ARM: tegra: clock: Lock DFLL 1st during cluster switch

During LP=>G CPU cluster switch lock DFLL in closed loop mode first,
and then disable LP CPU clock. This order change allowed to reduce
delay for G CPU to reach its target frequency.

Change-Id: If47779e2172cec8ccf9d66d74bbc2b219f7ddda2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299683
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Support variable GPU Vmin
Alex Frid [Sat, 5 Oct 2013 06:13:58 +0000]
ARM: tegra12: dvfs: Support variable GPU Vmin

Replaced constant GPU minimum voltage limit with variable Vmin
adjusted based on particular chip speedo value and temperature range.
CVB polynomial equation used for Vmin calculation is the same as for
each GPU DVFS frequency, just coefficients are different. Still apply
absolute Vmin at cold (below 15C) to GPU rail for the entire Tegra12
family.

Bug 1273253

Change-Id: I61925886131647f42ba1a6db233044dc1f3351ed
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/289548
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm:tegra: set cma data for nvmap platform data
Vandana Salve [Thu, 19 Sep 2013 13:24:04 +0000]
arm:tegra: set cma data for nvmap platform data

Pass the cma dev pointers, resize flag and
CMA chunk size in nvmap platform data
for the reserved contiguous memory using CMA

Bug 1279160

Change-Id: I5420bcdf859c463fed6e7c8715b82da71922c2ed
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/289421
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoARM: tegra12: clock: Allow EMC backup if scaling disabled
Kaz Fukuoka [Thu, 26 Sep 2013 18:06:47 +0000]
ARM: tegra12: clock: Allow EMC backup if scaling disabled

Re-arranged EMC backup procedure so that backup is allowed even if
EMC scaling is disabled. This is necessary to re-lock main EMC pll
at maximum rate. Without backup, EMC may stuck at rates lower than
maximum while scaling is disabled.

Ported from Tegra11 Change-Id: Ie7f7b481d077c1f696d3cd42f3786300fd96fc80

Change-Id: If6212c1ebb18f151739fd637fb20a50448129282
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298513
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Skip lowering voltage on EMC backup
Kaz Fukuoka [Wed, 25 Sep 2013 23:38:08 +0000]
ARM: tegra12: clock: Skip lowering voltage on EMC backup

If EMC backup rate is below current rate, skip lowering voltage when
switching to backup clock source, Final voltage will be set correctly
after main clock source is re-locked, and EMC clock is switched to
main source.

Bug 1188643

Ported from Tegra11 Change-Id: I82a4a85449dbd589c7692f6640e1bd5e08e0bc9b

Change-Id: Ida94aa31c9b67fab7aaa8c4df4ea66996b7c8443
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298512
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agopower: Prefer min over max for online cpus
Sai Gurrappadi [Mon, 21 Oct 2013 17:44:23 +0000]
power: Prefer min over max for online cpus

We prefered min_online_cpus over max_online_cpus if min > max.
min_wins is now true for online cpu PmQoS requests.

Bug 1270839

Change-Id: I2888538dd1a4616babb7cd1532264272de5cfe64
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/301871
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoRevert "video: tegra: host: add power domain for host1x"
Sridhar Lavu [Mon, 21 Oct 2013 17:01:50 +0000]
Revert "video: tegra: host: add power domain for host1x"

This reverts commit 674927b93952b919195a691c4226391007cfd026
since it is causing sanity failure for suspend sanity.

Bug 1384396 : original change
Bug 1392433 : sanity regression

Change-Id: I3647050c51ccc8c24eead2a234fae64a15d07599
Signed-off-by: Sridhar Lavu <slavu@nvidia.com>
Reverts-what-was-Reviewed-on: http://git-master/r/299959
Reviewed-on: http://git-master/r/301857
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: remove unnecessary fuse header files
Shardar Shariff Md [Wed, 16 Oct 2013 06:36:20 +0000]
arm: tegra: remove unnecessary fuse header files

Removing unwanted fuse.h header inclusion

Bug 1380004

Change-Id: I6cd7ceac380a6e418705965823f7127ad39dd548
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/299810
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: fuse: replace globals with functions
Shardar Shariff Md [Thu, 17 Oct 2013 06:48:18 +0000]
arm: tegra: fuse: replace globals with functions

Replace globals tegra_sku_id, tegra_chip_id &
tegra_bct_strapping with below functions
u32 tegra_get_sku_id(void);
u32 tegra_get_chip_id(void);
u32 tegra_get_bct_strapping(void);

Bug 1380004

Change-Id: I43eb2523e4af5d06bc1aa1f03c02c5168577878c
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/300401
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: t124: spi: Fix in setting RX_TAP_DELAY
Shardar Shariff Md [Mon, 21 Oct 2013 10:46:10 +0000]
arm: t124: spi: Fix in setting RX_TAP_DELAY

RX_TAP_DELAY should be set even if controller data(cdata)
as tap delay should be set depending on speed

Change-Id: Ia584be5c6bfd1e71166b4241ff127c22e1a7aeaf
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/301756
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: Fix compile warnings
Terje Bergstrom [Mon, 21 Oct 2013 10:12:34 +0000]
video: tegra: host: Fix compile warnings

Some "unsigned long"s were converted to u32. for_each_set_bit()
requires unsigned long, so convert some instanced back.

Fix how include files are included.

Forward declare nvhost_set_error_notifier.

Fix parameter to nvhost_memmgr_put() to be handle and not id.

Fix tracing to use %llx and casting to u64 to print dma_addr_t.

Change-Id: I8ab3c3f2012c2efdb519b17027dbaf20715e81f2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/301743
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agoarm: t124: spi: set rx tap delay
Shardar Shariff Md [Mon, 21 Oct 2013 10:33:56 +0000]
arm: t124: spi: set rx tap delay

Set rx tap delay as per characterisation data

Bug 1381154

Change-Id: Ic6faf9dea58e77e9624fdff2d4273e5bc806d898
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/301752
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: t124: spi: Improve slew rate of SPI signals
Shardar Shariff Md [Mon, 21 Oct 2013 09:14:21 +0000]
arm: t124: spi: Improve slew rate of SPI signals

As per characterisation data set pad groups
AT2, UAD, UAA with below settings
0x70000874 = 0x03f37000
0x70000924 = 0xf1717000
0x700008B8 = 0xf1717000

Bug 1381154

Change-Id: Ic2580a51c40f68e7875b6158668c7c10faad66d4
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/301723
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: add power domain for host1x
Prashant Gaikwad [Mon, 7 Oct 2013 10:29:07 +0000]
video: tegra: host: add power domain for host1x

If we enter LP0 from cpuidle all the context of host1x will
be reset as VDD_CORE is turned off in LP0.

Use generic power domain to save and restore the context of
host1x. If host1x is runtime suspended for 2s then it will
get suspended and context is saved. If some request or remote
weakeup is received for it then it is restored.

Bug 1384396

Change-Id: I6313ee49287379820b4f936c0d7cb8433934ce2c
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/299959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoregulator: fixed: enable regulator if it is always on
Laxman Dewangan [Tue, 8 Oct 2013 12:55:48 +0000]
regulator: fixed: enable regulator if it is always on

If regulator is always ON then make sure it is enabled
at the time of registration.

Change-Id: Idec9756c144ca9ae560b51662ef81dc37f56a213
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/289156
Reviewed-by: Automatic_Commit_Validation_User

5 years agoRevert "arm: tegra: update iso efficiency calculation"
Terje Bergstrom [Mon, 21 Oct 2013 06:55:49 +0000]
Revert "arm: tegra: update iso efficiency calculation"

Bug 1392092

This reverts commit 8d82e31458712d16b5a8ad4cd31072d4e1daa288.

Change-Id: Id6036b116620314d6fccbe309f2f293c6806caa3
Reviewed-on: http://git-master/r/301669
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra12x: iomap: Fix NOR size
Ashwin Joshi [Fri, 11 Oct 2013 10:11:25 +0000]
arm: tegra12x: iomap: Fix NOR size

Make Tegra NOR size configurable since different Automotive boards have
different NOR sizes and that needs to be mapped by the kernel.

Bug 1386803
Bug 1373849

Change-Id: Ib2dca855a5eb23c484c054772227cb2a3d562a49
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/301681
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agopower: bq2419x: Export sysfs node to set output current
Darbha Sriharsha [Tue, 15 Oct 2013 14:22:21 +0000]
power: bq2419x: Export sysfs node to set output current

Export sysfs node to set the output charging current
value.

Bug 1385836

Change-Id: Id9ea71e7c012754d4318e5d607e02263aaafe145
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/300425
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopower: bq2419x: Restart charging after charge complete
Darbha Sriharsha [Fri, 4 Oct 2013 13:42:21 +0000]
power: bq2419x: Restart charging after charge complete

Add support for restart of charging a certain time interval
after the charging complete interrupt is generated.

Bug 1354923

Change-Id: I3685bc6f52ea3fd114c69e115f28a69731c0f71e
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/300424
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopower: bq2419x: Provided low batt voltage notification
Darbha Sriharsha [Fri, 4 Oct 2013 12:06:17 +0000]
power: bq2419x: Provided low batt voltage notification

Print the low battery voltage notification in the interrupt
service bq2419x interrupt service routine.

Bug 1354813

Change-Id: I1cff88161f3ccfbf79615baf52c4c94bf914e5fe
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/300423
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: Pass irq number to bq2419x charger
Darbha Sriharsha [Fri, 4 Oct 2013 11:36:58 +0000]
arm: tegra: Pass irq number to bq2419x charger

Pass interrupt number through device tree file
to bq2419x charger driver on TN8 platform.

Bug 1354813

Change-Id: I89cb4e6c83c0e64329980413231d61def8af5e46
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/300422
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: Transfer bq2419x platform data to DT
Darbha Sriharsha [Mon, 30 Sep 2013 06:14:27 +0000]
arm: tegra: Transfer bq2419x platform data to DT

Remove bq2419x platform data from the board file
and add it to the devicr tree files for tn8.

Bug 1375730
Bug 1367264

Change-Id: Iecd2aede72ea76477c4917487f793b1d7b1a5aa7
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/300421
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopower: bq2419x: Add device tree support
Darbha Sriharsha [Wed, 25 Sep 2013 07:18:37 +0000]
power: bq2419x: Add device tree support

Add device tree parsing support in bq2419x battery charger driver

Bug 1367264

Change-Id: I54ae21c98304553b8f1ba65a6618bc2dc6aade99
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/300420
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: gk20a: split pmu init
Prashant Malani [Sat, 28 Sep 2013 22:34:57 +0000]
video: tegra: host: gk20a: split pmu init

Split pmu init into two parts. One before, and one
after graphics init. This way, we don't have to waste
time waiting on the first wait queue, which consumes
a lot of time.

Change-Id: Ia82a5720d0f28e710c1fbdd939c6875eb9578689
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/289275
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: Register gk20a for touch boost
Terje Bergstrom [Wed, 9 Oct 2013 12:22:53 +0000]
video: tegra: host: Register gk20a for touch boost

Register gk20a device to be notifier on touch event.

Bug 1364240

Change-Id: I044fd919132fb5c825462029db1f1f8c0ba6d901
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288812

5 years agoPM / Domains: Check if device wants to wake up
Terje Bergstrom [Wed, 9 Oct 2013 12:22:02 +0000]
PM / Domains: Check if device wants to wake up

If a a define is marked as "NO_POWER_OFF", and it's suspended, wake
it up.

Bug 1364240

Change-Id: Ic51e69db01a88e2deefa4c3c0884d14ccc29272b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288811

5 years agoPM / QoS: Add notifier for flags
Terje Bergstrom [Wed, 9 Oct 2013 12:21:42 +0000]
PM / QoS: Add notifier for flags

dev_pm_qos has a notifier for DEV_PM_QOS_LATENCY. Add a similar
notifier for DEV_PM_QOS_FLAGS.

Bug 1364240

Change-Id: Ica4c58708855938818a1e75896503b9023b96573
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288810

5 years agoinput: cfboost: Add GPU wake-up
Terje Bergstrom [Wed, 9 Oct 2013 10:14:49 +0000]
input: cfboost: Add GPU wake-up

Add interface for registering a GPU device. Whenever touch event is
received, ask the domain not to be powered off.

Bug 1364240

Change-Id: I2e61b6969ecdf89dcf00f57565eefdf0a93b3acd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288809
Reviewed-by: Automatic_Commit_Validation_User

5 years agoPM / QoS: add dev_pm_qos_update_request_timeout()
Terje Bergstrom [Wed, 9 Oct 2013 08:33:38 +0000]
PM / QoS: add dev_pm_qos_update_request_timeout()

Add dev_pm_qos_update_request_timeout() that works in the same way as
pm_qos_request_timeout().

Bug 1364240

Change-Id: I9da700df443f48099eac929055e9fe2db4c2f540
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288808

5 years agoinput-cfboost: use RT kthread for PM QoS request
Yogish Kulkarni [Tue, 5 Feb 2013 12:01:08 +0000]
input-cfboost: use RT kthread for PM QoS request

It has been observed that input drivers worker thread gets scheduled
before boost worker thread, specifically in case of Raydium touch.
The delayed scheduling of boost works adds to first touch latency
when cpu is idle and running at lower clock rate. Hence use RT
kthread for fast scheduling of boost work. Thread Priority is set to
MAX_RT_PRIO-10 so that the highest RT priority level is left for
EMC DVFS.

Bug 1245419
Bug 1229219
Bug 1364240

Change-Id: I342161532a7b8407d1ecfad29710e13a47331bff
Signed-off-by: Yogish Kulkarni <yogishk@nvidia.com>
Reviewed-on: http://git-master/r/249716
(cherry picked from commit 851e0df306161be573b1a94c6eb3fdfdb5107167)
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288807
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: Fix deadlock in rl update
Arto Merilainen [Thu, 17 Oct 2013 14:37:27 +0000]
video: tegra: host: Fix deadlock in rl update

Engine recovery was initiated if the runlist update failed. The
recovery is performed in asynchronous fashion and it accesses runlist
data structures that are protected by runlist lock. Runlist update routine,
however, did not release lock at this point and therefore it effectively
caused deadlock.

This patch makes the runlist routine to release the mutex if it needs to
initiate engine recovery

Change-Id: Ifa990117fa34a31cff73ce3ea64e67720f28aede
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/300625
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Don't wait timedout ch
Arto Merilainen [Thu, 17 Oct 2013 14:34:07 +0000]
video: tegra: host: gk20a: Don't wait timedout ch

gk20a channel finish used to always wait until the channel has done all
syncpoint increments. However, if the channel has timeouted, it surely
will not make those increments. This patch modifies channel finish to
skip syncpoint wait if the channel has timeouted.

Change-Id: I4807f40cae82992d5a7a8d15b8b9e958a3b47c3c
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/300624
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: SM faults trigger recovery
Arto Merilainen [Thu, 17 Oct 2013 13:11:48 +0000]
video: tegra: host: SM faults trigger recovery

We used to ignore SM faults when debugger was not attached. This
patch makes us now to correctly trigger channel recovery routine.

Bug 1334322

Change-Id: Ife29a07c5fc82baa5d8c00ee689afc741bbc9118
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/300585
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Recover GR on faults
Arto Merilainen [Tue, 15 Oct 2013 10:36:14 +0000]
video: tegra: host: gk20a: Recover GR on faults

GR faults used to trigger channel free which is illegal operation
inside (threaded) ISR. Channel free requires pre-emption of a
channel and given that operation likely will fail if GR already
has generated an interrupt.

This patch modifies the code to trigger GR recovery in exceptions.

Bug 1334322

Change-Id: Ic9cbbbd06e48d5c093db6fe3b85d1747cce4f933
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/300584
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Imm TLB invalidation
Arto Merilainen [Thu, 17 Oct 2013 13:03:35 +0000]
video: tegra: host: gk20a: Imm TLB invalidation

PMU assumes that the pages that it requests to be mapped are available
immediately. However, we currently postpone TLB invalidation to channel
submission and therefore the hw may end up accessing the pages
before the TLB contains the pages.

This patch adds TLB invalidation when we are mapping memory to non-
existent address space (i.e. pmu and fecs memory).

Bug 1334322

Change-Id: I1ed48d224589474a0cd438076478ff1c6ffecc5a
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/300583
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Add FECS debug dump
Arto Merilainen [Fri, 18 Oct 2013 13:04:21 +0000]
video: tegra: host: gk20a: Add FECS debug dump

We currently do not have good diagnostic tools for FECS. This patch
adds a debug dump to FECS so that we print some useful registers of
FECS when
1) we get chsw error or
2) PMU dump is performed (PMU crashes)

Bug 1369878

Change-Id: I4921c5726190b3a15951f076af8509bc5da9588a
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/301249
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoRevert "usb: gadget: tegra: Updates for 3.6"
Rohith Seelaboyina [Tue, 15 Oct 2013 08:51:59 +0000]
Revert "usb: gadget: tegra: Updates for 3.6"

This reverts commit 7be795c532fd0b699978638bc68cc28d96882802.
udc->transceiver should be NULL in case otg failed
to register, this avoids unnecessary checks and
improves the reability of the code.

Change-Id: I62673770f5efd1eef392ccde0afd726e8ac0d6e2
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/299387
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: dalmore: Add vdd_lcd_bl disable delay
Vineel Kumar Reddy Kovvuri [Fri, 4 Oct 2013 09:14:06 +0000]
ARM: tegra: dalmore: Add vdd_lcd_bl disable delay

Adds delay for vdd_lcd_bl regulator to fix unexcepted
behaviours during quick disable and enable cycle.

Bug 1346985

Change-Id: I1e31c6ea5cac6c8fa9d15d6f961a45fc75281578
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/288743
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoregulator: core: introduce regulator disable time
Laxman Dewangan [Mon, 21 Oct 2013 07:02:58 +0000]
regulator: core: introduce regulator disable time

It is observed that some regulators do not get re-enabled without
waiting for the duration of disable time to completely turn off
Introduce the regulator disable time to make sure regulators are
disabled before enabling it.

Bug 1346985

Change-Id: I0bfff8f32dab7986ffab901b735fad6b4ec79c6f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/288742

5 years agovideo: tegra: host: gk20a: protect elpg debugfs
Prashant Malani [Mon, 14 Oct 2013 18:46:08 +0000]
video: tegra: host: gk20a: protect elpg debugfs

Protect a possible race on accessing of registers
in the elpg debugfs node by surrounding the access
with module_busy/module_idle calls.

Bug 1349649

Change-Id: If7fd544daf05b9298307f2b39bcd5c966d88f4e0
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/299038
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: Implement error notification
Kirill Artamonov [Thu, 10 Oct 2013 12:29:03 +0000]
video: tegra: host: Implement error notification

Implement interface to pass gk20a error notification
to userspace.

bug 1297417
bug 1232244

Change-Id: If271a6f9c464e7b558de119d9746a7382d09fd62
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/299476
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: loki: enable clock debug init.
Jiejing Zhang [Thu, 17 Oct 2013 08:22:25 +0000]
ARM: tegra: loki: enable clock debug init.

Add late_init call to support clock debug init etc.

Change-Id: I9322c3354616384f508679600a2dbae0a5bb0032
Signed-off-by: Jiejing Zhang <jasozhang@nvidia.com>
Reviewed-on: http://git-master/r/300461
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra11: disable DEBUG_LL/EARLY_PRINTK in defconfig
Matt Craighead [Fri, 18 Oct 2013 20:54:44 +0000]
ARM: tegra11: disable DEBUG_LL/EARLY_PRINTK in defconfig

This seems to have gotten turned on erroneously as part of the
K3.10 transition, and is inconsistent with tegra12_defconfig.

Change-Id: Ia61bb7738bce6e056fa615c34e7fd2a75ac9c4af
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/301371
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

5 years agoARM: tegra: don't enable both SMC91X and SMSC911X
Matt Craighead [Fri, 18 Oct 2013 20:58:47 +0000]
ARM: tegra: don't enable both SMC91X and SMSC911X

Some defconfigs were enabling both, which could lead to strange
problems because they would both try to use the same IRQ.

Bug 1351589

Change-Id: I1f34711e18fb4f72b3c73b364324b53918fb44ce
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/301374
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoarm: tegra: change iso mgr efficiency for T114
Xue Dong [Wed, 16 Oct 2013 22:37:20 +0000]
arm: tegra: change iso mgr efficiency for T114

bug 1162232

Change-Id: Ic9b03095ef5a1b15bc7c3f9bbdfb2d38b89af383
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/300186
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: update iso efficiency calculation
Xue Dong [Tue, 10 Sep 2013 01:48:31 +0000]
arm: tegra: update iso efficiency calculation

bug 1162232

Change-Id: I3c50129cb7fe823663c45239be8815da4470587c
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/299590
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoRevert "input: sensor: compass: Add sec-salve-id for compass"
Mitch Luban [Fri, 18 Oct 2013 23:38:10 +0000]
Revert "input: sensor: compass: Add sec-salve-id for compass"

This reverts commit 925b5913a6d7f1108ae8cbe0eb263bdf07bf1a3b.

Change-Id: Ie879e7cd77897497e32323e16b7004317e6f5163
Reviewed-on: http://git-master/r/301456
Tested-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoarm: tegra: dalmore - Bruce modem platform data
Julien Vuillaumier [Fri, 18 Oct 2013 08:05:43 +0000]
arm: tegra: dalmore - Bruce modem platform data

Cold boot GPIO (MDM_COLDBOOT) IRQ handler to be declared as oneshot
for K3.10

Bug 1391146

Change-Id: I53539b35f31b50824126711eaa15b458dedcc8e3
Reviewed-on: http://git-master/r/301110
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>

5 years agoarm: tegra12: soctherm: use high precision mode
Diwakar Tundlam [Mon, 14 Oct 2013 19:08:52 +0000]
arm: tegra12: soctherm: use high precision mode

Enabling high precision mode for T12x as it supports high precision
temperature sensing with 0.5C resolution of temperatures and 1C
resolution of thresholds.

Bug 1291108

Change-Id: Ie4d9e1273f793c581e88e5061176f74e87e7cd00
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/299047

5 years agoarm: tegra: skip carveout base and size prints
Krishna Reddy [Thu, 17 Oct 2013 21:10:56 +0000]
arm: tegra: skip carveout base and size prints

When NVMAP_USE_CMA_FOR_CARVOUT is enabled, don't print
carveout base and sizes as they are not known in board
specific files.
Bug 1279160

Change-Id: I7e90c530416ea051e719a77897497eb944f7465d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/300691
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agoinput: sensor: compass: Add sec-salve-id for compass
Xiaohui Tao [Tue, 17 Sep 2013 17:53:00 +0000]
input: sensor: compass: Add sec-salve-id for compass

Bug 1356943

Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/272840
Reviewed-on: http://git-master/r/273830
Reviewed-on: http://git-master/r/275874
(cherry picked from commit 9f42dfc3cda19db08aec5a01ed124789240c4970)
Reviewed-on: http://git-master/r/290021

Change-Id: I804f363ae38aad8c0f239dc9fa1800becd6f0f2e
Reviewed-on: http://git-master/r/300698
GVS: Gerrit_Virtual_Submit
Reviewed-by: Xiaohui Tao <xtao@nvidia.com>
Tested-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoinclude: linux: nvmap: add carveout resize params
Vandana Salve [Thu, 17 Oct 2013 21:16:54 +0000]
include: linux: nvmap: add carveout resize params

Add cma chunk size and resize params in
nvmap_platform_carveout.
Prepare nvmap to support carveout resizing.

bug 1279160

Change-Id: I2fc201281a1a2b0b19ffa29d0912a5b2d1ade8af
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/300693
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agopower: PM QoS support for bounded constraints
Sai Gurrappadi [Tue, 1 Oct 2013 17:37:35 +0000]
power: PM QoS support for bounded constraints

Extended PM QoS to allow binding of two constraints. Bounded constraints
add the following functionality:

- Priority for min/max bound requests. Targets bounds are set
  to satisfy all priorities (intersection of all ranges). If it
  is not possible to do so, higher priorities prevail
- Timeouts for bound requests
- Userspace interface that exposes bound requests

PM QoS still supports its original kernelspace and userspace interfaces

Bug 1270839
Bug 1349096

Change-Id: Ic83444912b330fc71335d9a5b59077b1d16496bd
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/299037
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agopmqos: Replace spinlock with mutex for pm_qos_lock
Sai Gurrappadi [Tue, 1 Oct 2013 17:01:27 +0000]
pmqos: Replace spinlock with mutex for pm_qos_lock

Using a spinlock (taken with irqsave) meant that pm_qos_lock couldn't be
used to synchronize on the notifiers in order to ensure proper order of
the notifications. This is needed in case where there might be two near
simultaneous pmqos client requests for a bound on the same constraint;
the notifiers in pm_qos_update_target for the two clients could
potentially engage in a race.

Example:

Assume two requests are made (A, B with A coming first) for max cpufreq
and these are the only requests currently available.

Current behavior can result in:

notify(max_cpu_freq, minof(A, B))
notify(max_cpu_freq, minof(LONG_MAX, A))

Expected behavior:

notify(max_cpu_freq, minof(LONG_MAX, A))
notify(max_cpu_freq, minof(A, B))

Most of the PM QoS and Dev PM QoS requester clients were reviewed and
none of them were found to be calling pm_qos_add/update/remove request
from interrupt or atomic context since those calls include the blocking
notifier call which cannot be done in atomic context.

Change-Id: I2fb43cc38da4c701e4872b937dd82cd38f1a1c1e
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/299036
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agovideo: tegra: host: convert dmabuf to fd
Krishna Reddy [Thu, 17 Oct 2013 20:13:16 +0000]
video: tegra: host: convert dmabuf to fd

convert dmabuf to fd when handles are represented with
fd's.

Change-Id: Ic4b17afc62c9ccc8fd461e782f077dd0091a5707
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/300684
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agovideo: tegra: dc: set syncpt max to N+1 in dc disable
Xue Dong [Thu, 17 Oct 2013 23:45:59 +0000]
video: tegra: dc: set syncpt max to N+1 in dc disable

bug 1388480

Change-Id: I7fc2c41e329651e0fbf3fbe8ee22755ad42b9da8
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/300896
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Increase VDD_GPU safe step up
Alex Frid [Wed, 16 Oct 2013 20:49:34 +0000]
ARM: tegra12: dvfs: Increase VDD_GPU safe step up

Increased VDD_GPY safe step up to maximum voltage - effectively
removed any stepping up.

Bug 1387622

Change-Id: I3a118ba908ba304d7ee1a342d007a609fff772b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/300137
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Increase VDD_CORE safe step up
Alex Frid [Wed, 16 Oct 2013 20:26:44 +0000]
ARM: tegra12: dvfs: Increase VDD_CORE safe step up

Increased VDD_CORE safe step up to maximum voltage - effectively
removed any stepping up.

Bug 1387622

Change-Id: Ieb6acf3f0b980315a76f2f689a5db9c02fddd4fd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/300136
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: loki: read wifi MAC address from file
Michael Hsu [Thu, 10 Oct 2013 02:06:33 +0000]
arm: tegra: loki: read wifi MAC address from file

Read wifi MAC address from factory partition (/mnt/factory).

Bug 1340767
Bug 1385793

Change-Id: I28095c4e6fc7ae9fdfe8c1df277715343a966082
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: http://git-master/r/299728
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoARM: Tegra: Utilize burst policy for LP1 wakeup
Antti P Miettinen [Sun, 13 Oct 2013 19:52:35 +0000]
ARM: Tegra: Utilize burst policy for LP1 wakeup

Running SCLK from CLKS makes LP1 wakeup latencies horrible.
However, we can utilize IRQ bursting to switch automatically
to CLKM upon LP1 wakeup IRQ. This maintains low power for LP1
but improves wakeup latencies significantly.

Bug 1381343

Change-Id: I9a3fcd81999d1b593bf242bfa7ef8505f9848d43
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/298749
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra12: clock: Put PLLE under h/w control
Kaz Fukuoka [Tue, 1 Oct 2013 01:08:11 +0000]
ARM: tegra12: clock: Put PLLE under h/w control

Ported from Tegra11 change Ifa0621f2d3bb7c0f8f52a0f9947990b789e1241b

Change-Id: Ie954f38dd52f098cfcad7f99449662e1d23c1be2
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298499
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: Tegra: Clock: Clean up soc clock
Krishna Sitaraman [Fri, 4 Oct 2013 23:32:44 +0000]
ARM: Tegra: Clock: Clean up soc clock

set max freq of sclk to 408Mhz
set max freq of hclk to 408Mhz
set max freq of pclk to 204Mhz (half of hclk)
set max freq of cop to be same as sclk

Change-Id: Iff46067b215d79fba1b8c891b6c5ad2e32fdfa2a
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/299018
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoinput: touch: radyium: code drop v60.8
Xiaohui Tao [Wed, 9 Oct 2013 17:03:32 +0000]
input: touch: radyium: code drop v60.8

Fix potential deadlock
Add Loki panel support

Bug 1350878
Bug 1380477
Bug 1357654
Bug 1365494

Change-Id: I1b997217cab4abb3eb974230811e6df06588801b
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/290022
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoRevert "tty: serial: 8250: tegra fix spurious interrupts"
Edgardo Handal [Tue, 15 Oct 2013 19:40:56 +0000]
Revert "tty: serial: 8250: tegra fix spurious interrupts"

This reverts commit c131ba5b6169ae02c51c67e470df35e7ef71e21a.

Bug 1229695
Bug 1339412

Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Change-Id: I1ff590e58c82c7f4238e292fd6160502a8a8088c
Reviewed-on: http://git-master/r/299585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>