5 years agoARM: tegra: power: Update to EDP table
Peter Boonstoppel [Thu, 11 Aug 2011 00:38:44 +0000]
ARM: tegra: power: Update to EDP table

 - updated EDP table for AP30 A02 2.5A to match data from Bug 844268
 - updated EDP cap for single core on AP30 A02 to 1.3Ghz
 - changed EDP table for A01 to match AP30 A02

Original-Change-Id: I1722768f235d63a2f311d082d8126ba071226eb6
Reviewed-on: http://git-master/r/46482
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc98aaffd4568b9ad642696eef5f559d9c7fd7237

5 years agoARM: tegra: la: use lower LA for display clients
Jon Mayo [Wed, 10 Aug 2011 23:16:10 +0000]
ARM: tegra: la: use lower LA for display clients

In order to prevent display underflow until latency allowance scaling is
enabled, use the LA value corresponding to low threshold, instead of max
LA for full FIFO.

Bug 840688

Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
Reviewed-on: http://git-master/r/46342
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>

Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1

5 years agoARM: tegra: clock: Use rounded ActMon maximum rate
Alex Frid [Sat, 6 Aug 2011 01:56:04 +0000]
ARM: tegra: clock: Use rounded ActMon maximum rate

Used round rate API to determine maximum frequency of Tegra3 activity
monitoring shared users, instead of maximum rate directly. The former
takes into account available PLL/dividers and return actually
reachable frequency.

Bug 860618

Original-Change-Id: I48292c65bfbf58906ab59f86959b0e7155117558
Reviewed-on: http://git-master/r/45711
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Tested-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R2be5b1549b53d2b203ccfe6ea1d1cd2368359d91

5 years agoARM: tegra: cardhu: switch off PMU at high temperature
venu byravarasu [Wed, 3 Aug 2011 11:21:57 +0000]
ARM: tegra: cardhu: switch off PMU at high temperature

Add board support needed for PMU switch off when tsensor
detects temperature > TH3 threshold set.

bug 850047

Original-Change-Id: I7a283cedc735264dd8ea52801f7f1a103e9293cb
Reviewed-on: http://git-master/r/41531
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rddb801325d32043d1dd127a8850adc50c67b4fee

5 years agoarm: tegra: devices: Add PMC IO address in SE resources
Kasoju Mallikarjun [Wed, 3 Aug 2011 18:17:12 +0000]
arm: tegra: devices: Add PMC IO address in SE resources

Added PMC IO registers as platform resources of
Security Engine for storing context save buffer
address in PMC registes during context save.

Bug 855476

Original-Change-Id: I3bd5791743b157139d61ecea3d3e1ef131d8cce5
Reviewed-on: http://git-master/r/44808
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>

Rebase-Id: Rd5030cf1659887cedd9f60b00224ad7dddd7cd8c

5 years agoARM: tegra: la: Add debugfs to latency allowance.
Jon Mayo [Thu, 21 Jul 2011 01:49:00 +0000]
ARM: tegra: la: Add debugfs to latency allowance.

add /sys/kernel/debug/tegra_latency/la_info to print programmed latency
allowance settings.

Original-Change-Id: I65a7a04c42f8ac27aaf2c1c953d695bc0bba0c77
Reviewed-on: http://git-master/r/42285
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R540ef9a4ed274eae52800edcd6ad590e16b67e09

5 years agoARM: tegra: Disable PL310 double line fill feature
Scott Williams [Thu, 4 Aug 2011 04:56:02 +0000]
ARM: tegra: Disable PL310 double line fill feature

Bug 854424

Original-Change-Id: I53a86b023920978cee0e6804985dd35d1f286de5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/44930
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R0c3899291fd85be56c6e93c02d072fd9cd6dd116

5 years agoARM: Tegra: dvfs: Proc array indep of new T30 char SKUs
Diwakar Tundlam [Thu, 23 Jun 2011 04:17:19 +0000]
ARM: Tegra: dvfs: Proc array indep of new T30 char SKUs

- Make process_ids array independent of SKU to avoid confusion when
  detecting SKU, speedo_id and parsing process_id.
- Added SKU definitions for characterization SKUs of AP30, T30, T30S

Bug 855816

Original-Change-Id: I925d54ab6d35e8af038cbfe84ef4b4c076cd596d
Reviewed-on: http://git-master/r/43096
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R832f8fb1a34ab700af0c6389fbe5307f334cc54c

5 years agoarm: tegra3: Keep DAP2 in maximum driver strength
Laxman Dewangan [Tue, 2 Aug 2011 08:46:48 +0000]
arm: tegra3: Keep DAP2 in maximum driver strength

Setting maximum driver strength of DAP2 in all tegra3
based system by default.

bug 820361

Original-Change-Id: I2f992f4779e7babe76a5dc7a679bee53b3369c9a
Reviewed-on: http://git-master/r/44497
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R03343987d0b060291c323558f5eaf96b63cd2321

5 years agoarm: tegra: enterprise: EDP support
Diwakar Tundlam [Mon, 25 Jul 2011 22:50:18 +0000]
arm: tegra: enterprise: EDP support

Added EDP support for Enterprise board via ext temp sensor nct1008

Bug 824621

Original-Change-Id: I476b9ad2cb46620d4775e6ee6e102b45f2b4dc27
Reviewed-on: http://git-master/r/43144
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0a59e82334166da1abfbc5a748ff4285e66590a4

5 years agoarm: tegra: fuse: tsensor specific fuse public API added
Bitan Biswas [Thu, 21 Jul 2011 12:02:53 +0000]
arm: tegra: fuse: tsensor specific fuse public API added

Defined public fuse API to extract tegra3 tsensor configuration
parameters.

bug 851791

Original-Change-Id: Ia14e2d515ee1d695556492464e8ceaf4b0d13477
Reviewed-on: http://git-master/r/42367
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1090e6ad78bcef23670ff647de86e695780f5b76

5 years agoARM: tegra: power: Add package mask to IO pad control
Alex Frid [Sun, 24 Jul 2011 03:14:25 +0000]
ARM: tegra: power: Add package mask to IO pad control

Modified dynamic IO pad configuration control to support SoC package
dependencies: set into "no-io-power state" IO pads that are not bonded
out on the particular package. Updated IO power detect table to account
for differences in Tegra2 and Tegra3 architecture.

Bug 853132

Original-Change-Id: I5f0aedfa784173cc37251ccf4e1dfb4d919db96e
Reviewed-on: http://git-master/r/42785
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R46208845c32e25340de6b1cebfb6b617c6c7ce4d

5 years agovideo: tegra: dc: fix tiled memory efficiency
Xin Xie [Thu, 7 Jul 2011 21:05:04 +0000]
video: tegra: dc: fix tiled memory efficiency

Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3.
This patch adds one memory controller API to retrive tiled memory efficiency.

BUG 847731

Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1
Reviewed-on: http://git-master/r/40074
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb0846a0b29dc838a3bb1e76c3a59da0bfc5bbf12

5 years agoarm: tegra: fuse: declare tegra_fuse_regulator_en() as extern
Varun Wadekar [Tue, 19 Jul 2011 09:26:23 +0000]
arm: tegra: fuse: declare tegra_fuse_regulator_en() as extern

platforms need to implement their fuse power on
functions if they do not use regulators to power
on the fuse block

Bug 836963

Reviewed-on: http://git-master/r/#change,41737
(cherry picked from commit 02747e1ddd8391dbb73ee04493417846508ebfbc)

Original-Change-Id: I1f462c1e92574e8f64ce2158a4fee8be7f5441ce
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/42821
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rf223f5756750cd010c55c69d68628107d46c5fa0

5 years agoARM: tegra: power: Control IO pad configuration dynamically
Alex Frid [Wed, 20 Jul 2011 23:15:25 +0000]
ARM: tegra: power: Control IO pad configuration dynamically

Tegra IO pads are automatically re-configured when IO power level is
changed. Current code keeps auto-detection cells in default, active
state all the time. This change will allow turning off cells when IO
power is stable, and activate them only during power transitions.

In addition IO pads will be set into "no-io-power" state after the
respective regulator is disabled, and re-configured back for regular
operations before regulator is re-enabled.

Dynamic IO pad control introduced in this commit is still disabled
by default on all tegra platforms.

Bug 853132

Original-Change-Id: Ifc7bbe2ac34929c14f8f8e9feaa4290b78fe6cf6
Reviewed-on: http://git-master/r/42263
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R8b7c7863c1580816a2f3b28bdb3c228a97a18736

5 years agoarm: tegra: ahci/sata: enable sata rails/partition at init
Yen Lin [Sun, 10 Jul 2011 23:07:39 +0000]
arm: tegra: ahci/sata: enable sata rails/partition at init

Enable sata rails and sata partition when driver initializes
- add sata_oob and cml1 clocks to sata powergate partition.
- set sata and sata_oob clock source using clk_set_parent API.
- fix a bug in while(timeout) loop

Bug 836589

Original-Change-Id: Iddc08bf851ffc83d45bd6aed4df85cde3b13f0e4
Reviewed-on: http://git-master/r/41314
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R500e99ac50d1e3c0851958b1c83316dded00d617

5 years agoARM: tegra: power: Add throttling enable reference counting
Alex Frid [Sun, 10 Jul 2011 06:22:12 +0000]
ARM: tegra: power: Add throttling enable reference counting

Added throttling enable reference counting, so that it can be
controlled by drivers for different thermal sensors (e.g, on
chip and device skin sensors).

Fixed possible dead-lock when cancel delayed work synchronous is
called while locked with the very same mutex that protects work
function.

Bug 837005

Original-Change-Id: If2aa8aa16f4a3b3497def592503213522fd38e54
Reviewed-on: http://git-master/r/40534
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R893b5a7b402d327b40acb7adbadb53f930804c0d

5 years agoARM: tegra: clock: Unify CPU set rate paths
Alex Frid [Sun, 10 Jul 2011 04:33:37 +0000]
ARM: tegra: clock: Unify CPU set rate paths

Made sure that CPU thermal and edp limits are applied on all CPU set
rate paths: cpufreq governor, thermal throttling, edp notification,
power management notification. Also included auto-hotplug governor
state update in all these paths (current code does not apply the
limits, or does not include auto-hotplug on some rate change paths).
One exception - keep current functionality for suspend notification:
set pre-defined CPU rate, and force auto-hotplug idle state.

Original-Change-Id: I54531f8f919ce248b2b56f5aa56f39e2efcb568a
Reviewed-on: http://git-master/r/40533
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R1471a5f318644fa5a7f436d8ed73c12de8b76245

5 years agoARM: tegra: power: Re-factor power headers.
Alex Frid [Sun, 10 Jul 2011 01:38:04 +0000]
ARM: tegra: power: Re-factor power headers.

Renamed and moved tegra cpu related function prototypes from power.h
to tegra-cpu.h. No functional changes.

Original-Change-Id: I24c25c9434bf7008e0875d1f74be502cd902c4ba
Reviewed-on: http://git-master/r/40532
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3d90799453a86a5a9ed012d2bfe373715de6d5c3

5 years agoARM: tegra: Add GPIO_PEE3 for Tegra3
Harry Hong [Fri, 8 Jul 2011 06:18:35 +0000]
ARM: tegra: Add GPIO_PEE3 for Tegra3

Original-Change-Id: I9a02b7a79b4bbf0139b5f0a6ad26f7c2eaf9582d
Reviewed-on: http://git-master/r/40144
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R79516993533f5681445de76470cb90025e073474

5 years agoARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz
Alex Frid [Fri, 15 Jul 2011 04:35:48 +0000]
ARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz

Original-Change-Id: I8cd5cfef8a040ffa5f0959b5a294b25a21fcfa8b
Reviewed-on: http://git-master/r/41141
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R47886089e5b3b73c58372645ec7ea282a0cfa698

5 years agoARM: tegra: power: Added global EDP Capping table
Peter Boonstoppel [Fri, 15 Jul 2011 17:54:05 +0000]
ARM: tegra: power: Added global EDP Capping table

 - Added table with EDP Capping values for different SKUs/regulator
   currents in new file edp.c
 - New entry point tegra_init_cpu_edp_limits()
 - Added DebugFS entry under debug/edp to list the currently
   selected EDP table
 - Populated EDP table in edp.c with data from Bug 844268
 - edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c
   both read from there

Bug 840255

Original-Change-Id: I55c2ee16278be8cd3005218bedebe76846d137d8
Reviewed-on: http://git-master/r/40938
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc598b39c3517e10c3c5052258e5a3e444f092b96

5 years agoARM: tegra: clock: Fix activity monitor resume
Alex Frid [Mon, 18 Jul 2011 23:20:54 +0000]
ARM: tegra: clock: Fix activity monitor resume

Move call to clock get rate API (can sleep) outside of activity
monitor resume section protected by spin lock.

Original-Change-Id: I78d5bb8728f3a728a6ff952b1f3cba19b9dec0a0
Reviewed-on: http://git-master/r/41626
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1ab0bb59a88f078f85f125b968546c09aab9d176

5 years agoarm: tegra: Console suspend for all boards
Laxman Dewangan [Mon, 18 Jul 2011 06:17:13 +0000]
arm: tegra: Console suspend for all boards

Added the board level suspend/resume and call the console
suspend from board level suspend/resume.

bug 820536

Original-Change-Id: I246265241246dc0682870571c927bd23023e5aca
Reviewed-on: http://git-master/r/41448
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: R8cde19092af981f1ac31a423aa035924b4353142

5 years agoarm: tegra: suspend: Add board specific suspend/resume calls
Laxman Dewangan [Tue, 12 Jul 2011 10:46:14 +0000]
arm: tegra: suspend: Add board specific suspend/resume calls

Adding board specific suspend and resume call apis through platform
data.
Added call of these function at appropriate stage of suspend/resume.

Added mechanism to select the uart debug channel base address through
variable so that board file can directly change this.

bug 820536
bug 832273

Original-Change-Id: Ia9ff3b8a8d2faa1071a8ff634960e6a6c8a43d40
Reviewed-on: http://git-master/r/34494
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R5c4d212ab07463ecbdf263412d4c7a5962dac5a3

5 years agoARM: tegra: power: Don't use suspended kernel time
Alex Frid [Wed, 13 Jul 2011 19:56:13 +0000]
ARM: tegra: power: Don't use suspended kernel time

Do not use kernel time to time-stamp Tegra3 CPU ULP/G mode switch in
late suspend/early resume when timekeeping is suspended.

Original-Change-Id: Idb6c8f8c2dd2cfc1e00cec53392de12131d6bbe1
Reviewed-on: http://git-master/r/40958
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R6ce7a5e7e06949f3536524ea675aa9c0fc2ab097

5 years agoarm: tegra: fuse: accept strings starting with 0x/x
Varun Wadekar [Thu, 14 Jul 2011 09:41:51 +0000]
arm: tegra: fuse: accept strings starting with 0x/x

some users might enter fuse data starting
with 0x/x. this will mess up the fuse programming.
do not consider 0x/x while programming the fuses.

also fix some compilation warnings

Reviewed-on: http://git-master/r/#change,38933

Original-Change-Id: I36b525c71b6d5c437affbaf0724667f8e5984aa6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41016
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rb6a134adfa8049865bb4154353763d43f743e052

5 years agoARM: tegra: clock: Clean tegra3_emc.c macro style
Alex Frid [Wed, 13 Jul 2011 02:34:35 +0000]
ARM: tegra: clock: Clean tegra3_emc.c macro style

Original-Change-Id: I472be800ad84b79783577264b51c6478aa4bb41b
Reviewed-on: http://git-master/r/40769
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0b3b4124618ecafc6f83ff165634ebba664a24a1

5 years agoARM: tegra: clock: Support Tegra3 EMC DFS table revision
Alex Frid [Tue, 12 Jul 2011 05:55:04 +0000]
ARM: tegra: clock: Support Tegra3 EMC DFS table revision

Support Tegra3 EMC DFS table revision 3.1 that includes two additional
EMC shadow registers (reserved with previous table revision 3.0).

Bug 836260

Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb
Reviewed-on: http://git-master/r/40749
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478

5 years agoARM: tegra: clock: Fix Tegra3 EMC clock change procedure
Alex Frid [Tue, 12 Jul 2011 04:43:45 +0000]
ARM: tegra: clock: Fix Tegra3 EMC clock change procedure

Fixed EMC clock change procedure to skip XM2CLKPADCTRL register during
shadow burst write, and set it within unshadowed section.

Bug 836260

Original-Change-Id: Ief92c7d3957c9685b8c528297da2e905159a530d
Reviewed-on: http://git-master/r/40748
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R5016ffd224db2b3eb6639a6b33063d1c27456b24

5 years agoARM: tegra: add support for hardware statistic counter
Prashant Gaikwad [Tue, 12 Jul 2011 11:32:54 +0000]
ARM: tegra: add support for hardware statistic counter

Tegra2 chip has a hardware statistic counter for CPU/AVP/VDE/SYS
modules. This commit adds the support for AVP statistics gathering and
controlling avp clock during video playback.

Bug 831892

Reviewed-on: http://git-master/r/35647
(cherry picked from commit 145885b03cd9fc625f2ff3460c59ebbb3d93c98e)

Original-Change-Id: I441acbaf2cb8dd776529bafd4e13f50e31849afa
Reviewed-on: http://git-master/r/39657
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7271973f142f14fc8a11bdbc33ae6f76f6fd38b0

5 years agoARM: tegra: clock: Add Tegra3 emc high voltage bridge
Alex Frid [Wed, 29 Jun 2011 03:50:29 +0000]
ARM: tegra: clock: Add Tegra3 emc high voltage bridge

On Tegra3 platforms emc configurations for DDR3 rates below 300MHz
can not work at high core voltage; the intermediate step (bridge) is
mandatory when core voltage is crossing the 1.2V threshold (fixed for
Tegra3 arch). In addition emc must run above bridge rate if any other
than emc clock requires high voltage.

EMC bridge is implemented as a special emc shared user: its rate is set
once during emc dvfs table initialization; then, the bridge is enabled
or disabled when sbus and/or cbus voltage requirement is crossing the
threshold (sbus and cbus together include all clocks that may require
voltage above threshold - other peripherals can reach their maximum
rates below threshold).

Bug 846693

Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf
Reviewed-on: http://git-master/r/39919
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff

5 years agoarm: tegra: enterprise: init modem according to modem_id
Steve Lin [Mon, 11 Jul 2011 19:45:06 +0000]
arm: tegra: enterprise: init modem according to modem_id

Init baseband modems according to the modem_id passed from the bootloader.

Bug 842870

Original-Change-Id: Ib8cd37877eb50ac67a337ef20dd6c6f631169578
Reviewed-on: http://git-master/r/39273
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb3484d422dd0fbfbd80ac5ef62fe1aa7fa574c52

5 years agoarm: tegra: fuse: support to burn fuses on the field
Varun Wadekar [Thu, 16 Jun 2011 11:08:30 +0000]
arm: tegra: fuse: support to burn fuses on the field

- follow the new sequence shared by the hardware team
- merge Tegra2 and Tegra3.0 odm fuse burning into a single file

Bug 796825

Original-Change-Id: Ia06d589eba95254a410016dce244375f27e22be0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/38404
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R740d7bd47eaa6231954ae98686272a755a4bce14

5 years agoARM: tegra: clock: Use bus lock to protect shared bus update
Alex Frid [Mon, 27 Jun 2011 21:36:58 +0000]
ARM: tegra: clock: Use bus lock to protect shared bus update

Protected shared bus update with bus lock - common for all shared bus
users (update procedure was already covered by individual shared users
locks, but it did not prevent concurrent access to shared rates list).

Original-Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507
Reviewed-on: http://git-master/r/39918
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0e0ee997ce9347470e207910f7b4f6c42143717f

5 years agoARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3
Karan Jhavar [Thu, 9 Jun 2011 21:50:35 +0000]
ARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3

By defalut PCIE and SATA partitions are powergated. If needed,
respective drivers should un-powergate these partitions. Also
3D,3D1 and MPE are not powergated at startup.

Original-Change-Id: Ibc74868eb59af7c0e8b5a1ecd78e6f993dd5d3a6
Reviewed-on: http://git-master/r/35955
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra55d87d7d816d7cf0bea0d28e7865fa7760f869f

5 years agoARM: tegra: power: Restore Tegra3 EMC power setting after deep sleep
Alex Frid [Wed, 6 Jul 2011 07:23:49 +0000]
ARM: tegra: power: Restore Tegra3 EMC power setting after deep sleep

Bug 836334

Original-Change-Id: I19587e97af0addc62217466ee977c5afc33a6028
Reviewed-on: http://git-master/r/39854
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R2748dbb3f7308ae491e137062e2b0f940fb8185e

5 years agoarm: tegra: devices: Set emc rate for avp
Prashant Gaikwad [Fri, 8 Jul 2011 09:25:19 +0000]
arm: tegra: devices: Set emc rate for avp

Set emc clock rate for avp client as required by the platform.

Original-Change-Id: I10374e1967cda6a9f497ba0a95bd62c3b58ecc40
Reviewed-on: http://git-master/r/40167
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R54697789f03d9465339029b49cba336cb9592c88

5 years agoARM: tegra: la: Add support for latency allowance.
vdumpa [Tue, 14 Jun 2011 20:20:01 +0000]
ARM: tegra: la: Add support for latency allowance.

Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91
Reviewed-on: http://git-master/r/36570
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9

5 years agotegra: clocks: Fix in clock settings
mchourasia [Mon, 27 Jun 2011 06:34:21 +0000]
tegra: clocks: Fix in clock settings

clk_disable_locked should not be called when
clk_enable_locked is failed.

Original-Change-Id: I2524ec0198f62de2487723676ca7657d15757eda
Reviewed-on: http://git-master/r/38273
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R1598bf84619449922c599d611a84dec791047837

5 years agoarm: tegra: cardhu: Fix the issue of boot screen corruption.
Kevin Huang [Wed, 6 Jul 2011 01:27:43 +0000]
arm: tegra: cardhu: Fix the issue of boot screen corruption.

- The issue is due to the corruption of bootloader fb during kernel
initialization. This change reserves the bootloader fb and then
frees it until bootloader fb is copied to fb for Cardhu, Ventana,
Whistler, Enterprise and Aruba.
- Change color depth of Cardhu and Harmony to 32-bit.

Bug 828271
Bug 832016

Original-Change-Id: I05ef5930ee68dcbd672a5cb59b4568a2c88a2e55
Reviewed-on: http://git-master/r/34966
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R92cd2153c44ac907fdf153a028429e7a5fa3fc23

5 years agoarm: tegra: tsensor: driver instantiation
Bitan Biswas [Fri, 10 Jun 2011 07:39:00 +0000]
arm: tegra: tsensor: driver instantiation

Tegra internal tsensor driver supported for fuse revision 0.8
and above.

Bug 661228

Original-Change-Id: I820f6b5f20c20bb2d1ba04266148f5969ab84444
Reviewed-on: http://git-master/r/36054
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R62574ff1667ad009dcf13f98e00b7af0ecca2016

5 years agoarm:tegra:tsensor: device definitions
Bitan Biswas [Tue, 22 Feb 2011 13:13:43 +0000]
arm:tegra:tsensor: device definitions

Tegra internal temperature sensor addresses defined

Bug 661228

Original-Change-Id: I061ac9e7da3115d1e832e645582353f93378d291
Reviewed-on: http://git-master/r/36119
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R62de8521a55164f582eb2b0f8ad5a83bbc02876c

5 years agovideo: tegra: nvmap: fix GART pin lockups
Kirill Artamonov [Wed, 15 Jun 2011 00:40:32 +0000]
video: tegra: nvmap: fix GART pin lockups

Fix GART lockups caused by fragmentation by evicting
mapped areas from iovm space after unsuccessful array
pinning attempt.

Fix double unpin error happening during interrupted
submit.

Fix possible sleep in atomic context in iovmm code
(semaphore inside spinlock) by replacing spinlock
with mutex.

Fix race between handle_unpin and pin_handle.

bug 838579
bug 838073
bug 818058

Original-Change-Id: I420447ffb4e02fb78a7987e22a537eefc16ff524
Reviewed-on: http://git-master/r/36129
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rd7c287d1a2ad3da50188788324ad908e19f34bb8

5 years agoARM: tegra: sysfs write permission for user only
Manoj Gangwal [Fri, 1 Jul 2011 10:09:43 +0000]
ARM: tegra: sysfs write permission for user only

Giving read-write permission for user only for sysfs attributes.
Group and other will have only read permission.
-clock: syncevents

Bug 828100

Original-Change-Id: I14affc209e954a58de055e291093e31dc1dbfe16
Reviewed-on: http://git-master/r/39364
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R97f4eadb711717e788be7c4e4e8993d048cf1428

5 years agoARM: tegra: power: Refactored kernel powergate code
Karan Jhavar [Tue, 17 May 2011 00:00:43 +0000]
ARM: tegra: power: Refactored kernel powergate code

This change provides a centralized location for powergating modules.
It would take care of switching on/off clocks while un-powergating/
powergating modules respectively.

Bug: 814267
Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710
Reviewed-on: http://git-master/r/31776
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Re0c233ed4bacc27feb7b210cddc6ff3e487c528f

5 years agotegra: power: correct LP0 sequence
Jay Cheng [Tue, 16 Aug 2011 18:57:59 +0000]
tegra: power: correct LP0 sequence

Change-Id: I5f548f11059039cbd830be483ecfa0c6671002e7
Reviewed-on: http://git-master/r/47365
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd7ef967c8b40295a04a0447eb8bbc8e2d577a48e

5 years agoARM: tegra: power: setup TTB0 for cacheable memory
Jin Qian [Tue, 16 Aug 2011 02:32:23 +0000]
ARM: tegra: power: setup TTB0 for cacheable memory

Bug 862494

Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3
Reviewed-on: http://git-master/r/47246
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58

5 years agoARM: tegra2: power: fix LP2 statistics reporting
Jin Qian [Tue, 16 Aug 2011 01:07:40 +0000]
ARM: tegra2: power: fix LP2 statistics reporting

Bug 863108

Change-Id: I5cc4e3ba58daeaeb527871026c85bdca5f6362f2
Reviewed-on: http://git-master/r/47232
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R843a5cf74874bad3999bc55caa0eb8cad04cc555

5 years agoARM: tegra: Fix build error when CONFIG_SMP is not selected
Scott Williams [Wed, 17 Aug 2011 18:47:58 +0000]
ARM: tegra: Fix build error when CONFIG_SMP is not selected

Change-Id: I2420730290c7ecb407e6f30c8a6159ceadfabbbe
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47589
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb177b1e8ed9ce89c732319f49525588c5c0dd9d0

5 years agoARM: tegra: Delete obsolete tegra_audio_device declaration
Scott Williams [Wed, 17 Aug 2011 19:19:09 +0000]
ARM: tegra: Delete obsolete tegra_audio_device declaration

Change-Id: I119fdbbc2440f8a7e64e2f3b5cec2ae4b182ee36
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47592
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R891ed7225b634dc01aaf3f13dbe79fc1eae1c27c

5 years agoARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selected
Scott Williams [Wed, 17 Aug 2011 18:49:57 +0000]
ARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selected

Change-Id: I65e18395eef3a36f6dd537d64d98ab970f166460
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47590
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2643d7665780442e71444999f21d96a508c7a062

5 years agoARM: tegra: workqueue: Unify spelling of 'freeze'+'able' to 'freezable'
Gaurav Sarode [Tue, 16 Aug 2011 09:42:41 +0000]
ARM: tegra: workqueue: Unify spelling of 'freeze'+'able' to 'freezable'

In K39 , 'freezeable' is changed to 'freezable'.
Reference Commit Id 58a69cb47ec6991bf006a3e5d202e8571b0327a4.

Change-Id: Ie3f95db453205c05da4cf4e655ba8b12a126255b
Reviewed-on: http://git-master/r/47487
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R530643b91e8c252eb606ce7e789cfe34101f6edd

5 years agoarm: tegra: Use new platform types
Yudong Tan [Fri, 1 Jul 2011 18:26:17 +0000]
arm: tegra: Use new platform types

This change is needed to support three different platforms, silicon,
 fpga and simulation.

Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce
Reviewed-on: http://git-master/r/36351
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19

5 years agoarm: tegra: Add platform types for Tegra
Yudong Tan [Mon, 13 Jun 2011 20:14:01 +0000]
arm: tegra: Add platform types for Tegra

Change-Id: Ib9ef42efcbc24d1424a1b43e7d4ad46b97255aaa
Reviewed-on: http://git-master/r/36350
Reviewed-by: Yudong Tan <ytan@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R99f25c1b92fe4a9322d83e00c9560fc7ada2b641

5 years agoARM: tegra: clock: Change default sampling period to 12ms
Tom Cherry [Tue, 5 Jul 2011 22:08:53 +0000]
ARM: tegra: clock: Change default sampling period to 12ms

Bug 845349

Original-Change-Id: I0ce1a5da9a80cea6a4e55bc92490e6ae8508e22f
Reviewed-on: http://git-master/r/39704
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rfc2bfc89082778e43d15406b0b5e53bdf845f08e

5 years agoARM: tegra: power: Restore cpufreq governor target
Alex Frid [Sat, 25 Jun 2011 04:06:22 +0000]
ARM: tegra: power: Restore cpufreq governor target

Restored cpufreq governor target frequency on exit from suspend.
Otherwise, CPU would stay at frequency set underneath the governor
by tegra driver on suspend entry.

Original-Change-Id: Iad96c7771bf89b78cdeb3e8f4e2c40b36e845b57
Reviewed-on: http://git-master/r/38390
Reviewed-by: Alex Courbot <acourbot@nvidia.com>
Tested-by: Alex Courbot <acourbot@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R12135cc7f8f940eac1653432786826bf2affec16

5 years agoARM: tegra: clock: Expand Tegra3 shared bus modes
Alex Frid [Fri, 24 Jun 2011 23:22:26 +0000]
ARM: tegra: clock: Expand Tegra3 shared bus modes

Implemented 3 different modes of combining rate requests from shared
bus users :
- SHARED_FLOOR: cumulative floor request is determined by maximum rate
among all users in this mode and minimum bus rate
- SHARED_BW: cumulative bandwidth request is determined by adding rates
of all users in this mode together
- SHRED_CEILING: cumulative ceiling request is determined by minimum
rate among all users in this mode and maximum bus rate

Final shared bus rate is determined as minimum rate between cumulative
ceiling request and maximum of floor or bandwidth cumulative requests.

Up to now shared bus clocks supported only SHARED_FLOOR mode, and this
mode is kept as default mode for all users. Hence, no change in actual
shared bus operations.

Bug 837005

Original-Change-Id: I29f8215ba7bab4998fdd23b74c4f96611f5848fe
Reviewed-on: http://git-master/r/39139
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re9f9f87d58419a6756b7985c59743356c6a634bc

5 years agoARM: tegra: dvfs: Update Tegra3 cpufreq table selection
Alex Frid [Sat, 18 Jun 2011 07:35:46 +0000]
ARM: tegra: dvfs: Update Tegra3 cpufreq table selection

- For selection of cpufreq scaling table used top-most rate in G CPU
dvfs table, instead of G CPU max rate. Commonly the above rates are
the same, however, in case when PMU limitations on core voltage
indirectly (VDD_CPU on VDD_CORE dependency) lower cpu max rate, the
top-most dvfs rate should be used for table selection, and the max
rate clipped to table entry.

- Replaced BUGs in table selection implementation with errors. Thus,
when no table is found cpufreq is not installed, but the system boots
with respective error messages.

- Step up suspend frequency index in cpufreq tables to reduce suspend
entry latency (the selected rate is still low enough to work under
Vmin voltage setting).

Original-Change-Id: I45db19dbf5b48cef80db35663db2df3b68473993
Reviewed-on: http://git-master/r/37415
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R59fb213db14d868bec0ca701e1c73dd9d1918e82

5 years agoARM: tegra: Fixed the wrong 'if' statement.
Jubeom Kim [Mon, 20 Jun 2011 11:39:30 +0000]
ARM: tegra: Fixed the wrong 'if' statement.

Removed the semicolon after 'if'.

(cherry picked from commit 9a118fd001bfbe23a7b825aa66cb19ebe7c12c7c)

Original-Change-Id: I058d58f6bad2ec08cf5a509361dbc3fc52801ce1
Reviewed-on: http://git-master/r/38228
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R1221658aa101f439a88df3cdae8a2d8c9c659cfb

5 years agoarm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLK
Harry Hong [Mon, 20 Jun 2011 04:46:37 +0000]
arm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLK

SFIO3 on VI_MCLK pin is needed to output vi_sensor clk.

bug 839517

Original-Change-Id: Ied7408a8711b0256b8fe98eea67c873a7b168bcb
Reviewed-on: http://git-master/r/37426
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>

Rebase-Id: Ra0c9550efc2ff7af8075eaf7962be94f2d299c2b

5 years agoARM: tegra: clock: Add shared bus users rate printout
Alex Frid [Sun, 26 Jun 2011 02:15:28 +0000]
ARM: tegra: clock: Add shared bus users rate printout

Original-Change-Id: Icb1a5028d575155427f1fd7fa5b3ee2a145934f4
Reviewed-on: http://git-master/r/38421
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: Rf473061330e8b6d63948c9a0ed247e37e3534a52

5 years agoARM: tegra: power: trace C states and CPU mode switches
Peter De Schrijver [Wed, 18 May 2011 08:10:08 +0000]
ARM: tegra: power: trace C states and CPU mode switches

Original-Change-Id: I7915d356f18ac830c93b736463406b907d8c1cef
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31958
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R341f7619d11f81fd7dfbab2ceb1c6fdaab6ead78

5 years agoARM: tegra: power: Overlap Tegra3 cpu off delay
Alex Frid [Sat, 14 May 2011 07:11:31 +0000]
ARM: tegra: power: Overlap Tegra3 cpu off delay

Overlap cpu off delay during G-to-LP mode switch with LP mode
residency.

Original-Change-Id: I8e93a5af3983e7daad46ae026fc510ce6c2fef99
Reviewed-on: http://git-master/r/31641
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R9260cc70b0fd5cf5266c7331a7b37d045f87fbfd

5 years agoARM: tegra: power: Use CPU LP mode for Tegra3 deep sleep
Alex Frid [Fri, 13 May 2011 05:51:34 +0000]
ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleep

Original-Change-Id: If23b48fb414332f5dd25307a098569a5474283c6
Reviewed-on: http://git-master/r/31471
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6ba9ce7c7b355da4148ce0ebc9bc357bf5fc0b13

5 years agoARM: tegra: power: Idle Tegra3 auto-hoplug on suspend entry
Alex Frid [Fri, 13 May 2011 04:08:34 +0000]
ARM: tegra: power: Idle Tegra3 auto-hoplug on suspend entry

Original-Change-Id: I7f4fb6447c882a54d95ee3fb4c6149f4e0357d69
Reviewed-on: http://git-master/r/31457
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Gerrit_Virtual_Submit

Rebase-Id: Rbe2ac5f11065109d34a04793f93c873441e261be

5 years agoarm: tegra: pinmux: Handling unfitted RSVD pinmux option.
Jin Park [Fri, 17 Jun 2011 06:17:19 +0000]
arm: tegra: pinmux: Handling unfitted RSVD pinmux option.

When call tegra_pinmux_set_func with unfitted RSVD pinmux option,
to prevent unexpected potential problem, handle to finding more
preferred value.

Bug 839423

Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Original-Change-Id: Idf8a1ece4317d14e94a69df0d1c8d450d7762c14
Reviewed-on: http://git-master/r/37185
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>

Rebase-Id: Rfb625aa025048c88c44fd96da1e8b0a3db8d013d

5 years agoARM: tegra: clock: Add Tegra3 AVP activity monitor support
Alex Frid [Thu, 16 Jun 2011 02:03:22 +0000]
ARM: tegra: clock: Add Tegra3 AVP activity monitor support

Added AVP clock control using Tegra3 activity monitoring device.
The target AVP frequency floor is set based on average load and
short term boost. Average AVP load time (time when AVP is not
halted by flow controller) is determined by fixed frequency count
provided by monitoring h/w featuring 1st order IIR activity filter.
The boost frequency is calculated by s/w - exponentially increasing/
decreasing when sampled AVP activity has crossed upper/lower boost
watermarks.

The implementation is interrupt driven - periodic sampling is hidden
by h/w. The tune-able debugfs parameters are:

/sys/kernel/debug/tegra_actmon/avp/boost_step - boost rate increase
step (% of max AVP frequency)
/sys/kernel/debug/tegra_actmon/avp/boost_rate_inc - boost rate
increase factor (%)
/sys/kernel/debug/tegra_actmon/avp/boost_rate_dec - boost rate
decrease factor (%)

/sys/kernel/debug/tegra_actmon/avp/boost_threshold_up - upper
activity watermark for boost increase (AVP active time in %)
/sys/kernel/debug/tegra_actmon/avp/boost_threshold_dn - lower
activity watermark for boost decrease (AVP active time in %)

Original-Change-Id: Ia82247176531f2fb67acfc277e63b9f16916a488
Reviewed-on: http://git-master/r/37175
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R995949fe30f188c16c3fa39e292a2ca56256f2a3

5 years agoARM: tegra: clock: Add Tegra3 EMC activity monitor support
Alex Frid [Sun, 12 Jun 2011 06:29:55 +0000]
ARM: tegra: clock: Add Tegra3 EMC activity monitor support

Added EMC clock control using Tegra3 activity monitoring device.
The target EMC frequency floor is set based on average activity
and short term boost. Average EMC activity is obtained directly
from monitoring h/w featuring 1st order IIR activity filter. The
boost frequency is calculated by s/w - exponentially increasing/
decreasing when sampled EMC activity has crossed upper/lower boost
watermarks.

The implementation is interrupt driven - periodic sampling is hidden
by h/w. The tune-able debugfs parameters are:

/sys/kernel/debug/tegra_actmon/emc/boost_step - boost rate increase
step (% of max EMC frequency)
/sys/kernel/debug/tegra_actmon/emc/boost_rate_inc - boost rate
increase factor (%)
/sys/kernel/debug/tegra_actmon/emc/boost_rate_dec - boost rate
decrease factor (%)

/sys/kernel/debug/tegra_actmon/emc/boost_threshold_up - upper
activity watermark for boost increase (% of current EMC frequency)
/sys/kernel/debug/tegra_actmon/emc/boost_threshold_dn - lower
activity watermark for boost decrease (% of current EMC frequency)

Original-Change-Id: I385c6e0a75da42dada792db6b4018b68fea8f23b
Reviewed-on: http://git-master/r/36790
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R0ac50b162b8e86237986885e115996f755b1e00a

5 years agoARM: tegra: generate status events for all clocks
Peter De Schrijver [Mon, 2 May 2011 12:43:06 +0000]
ARM: tegra: generate status events for all clocks

Original-Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31530
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R25afcccf5ff8d7a88b705ce7f68ab83e818ae1e4

5 years agoARM: tegra: sysfs write permission for user only
Sachin Nikam [Thu, 16 Jun 2011 07:46:26 +0000]
ARM: tegra: sysfs write permission for user only

Giving read-write permission for user only for sysfs attributes.
Group and other will have only read permission.
- tegra_mc_stats: enable and quantum
- susend: mode
- clock: rate, parent, state

File System Permission CTS expects this to pass.

Bug 840409

Original-Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/36867
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R3360698aa910479a0eccb460656d104912af99bb

5 years agoARM: tegra: clock: Add clock rate change notification
Alex Frid [Sun, 12 Jun 2011 06:23:50 +0000]
ARM: tegra: clock: Add clock rate change notification

Original-Change-Id: I97434334a4214180a365d9709a331405da135669
Reviewed-on: http://git-master/r/36202
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7bfea35bf7b2e083e594538e245e3b74e25d090a

5 years agonvhost: Make 3D workaround Tegra3 A01 only
Terje Bergstrom [Thu, 19 May 2011 06:35:16 +0000]
nvhost: Make 3D workaround Tegra3 A01 only

3D hardware workaround is needed for Tegra3 A01 only. With this patch, we
read run-time whether it should be enabled or not.

Workaround should be removed once A01's have been phased out.

Bug 786316

Original-Change-Id: Icd1b85b30a53c74d2e5c7a6df65a805d1fe5147c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/32136
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Re8e1ee401118339067a622ed7ae32f7f344c94b7

5 years agoARM: tegra: clock: Synchronize Tegra3 clocks scaling
Alex Frid [Sat, 14 May 2011 06:58:33 +0000]
ARM: tegra: clock: Synchronize Tegra3 clocks scaling

On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are
sourced from PLLC through integer dividers. Low resolution of these
dividers does not allow to set scaling frequency levels matching
intermediate voltage steps within core voltage range. Only changing
the source frequency can achieve it. However, re-locking common PLL
while engines are running requires synchronization of engines clock
control, and complex operations including switching to backup sources
during PLL stabilization time.

This commit introduces a new virtual clock "cbus" to support clocks
synchronization and PLLC re-locking procedures. The dvfs table for
cbus clock is constructed from frequency steps close to maximum rates
for each characterized core voltage level. Engine clocks exposed to
the drivers are no longer physical module clocks, but shared cbus
users. Setting the rate for such clock specifies the clock floor.
The final cbus rate is determined as maximum floor setting for all
enabled engines, and rounded up along the cbus dvfs ladder. Actual
engine clock rate is set equal to the cbus clock rate. Hence, engines
will be running close to maximum frequency for minimum voltage that
satisfies all floor requests.

Special case: Host1x. This clock will be always configured at 1/2 of
cbus clock rate, and its shared user floor request is ignored by cbus
target frequency calculations.

Added cbus dvfs tables and updated VDE engine dvfs data.

Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6
Reviewed-on: http://git-master/r/36199
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915

5 years agoarm: tegra: power: fix lp0 resume failure
Luke Huang [Mon, 6 Jun 2011 20:05:44 +0000]
arm: tegra: power: fix lp0 resume failure

Do not check PLLX lock bit on PLLX sanity check, since it might not be in the
lock state yet.

Original-Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3
Reviewed-on: http://git-master/r/35261
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R1ea05b0640b93de011109de3402d8810a64defcc

5 years agoARM: tegra: power: use buffered memory for suspend context
Jin Qian [Thu, 11 Aug 2011 22:57:43 +0000]
ARM: tegra: power: use buffered memory for suspend context

use buffered memory to bypass L2
add memory barrier after cpu suspend

Bug 862494

Change-Id: I0592ebd6608d2581700b9ae965de3e7d8aa2cabe
Reviewed-on: http://git-master/r/47172
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rfee82dddd83449e730ccfcd5f6359bbaa00582a7

5 years agoARM: tegra2: power: Don't disable CPU1 GIC interface in LP2
Scott Williams [Mon, 15 Aug 2011 16:08:06 +0000]
ARM: tegra2: power: Don't disable CPU1 GIC interface in LP2

Leave the GIC processor interface enabled for CPU1 during LP2.
Disabling it prevents CPU1 from waking up on IPIs.

Change-Id: I32ae01066f21f8b4fba1fd0da392bc691c29bf49
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R16db6ca494653a5d8c61cc7ac2b5cb2c3fa9f46f

5 years agoARM: tegra: power: Perform L2 cache sync when flushing L1
Scott Williams [Fri, 12 Aug 2011 17:21:35 +0000]
ARM: tegra: power: Perform L2 cache sync when flushing L1

Change-Id: I7b769bec8fc2dc0cd6db34e125f1cfd45aea8b12
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rcf33e9438333a90b3aa9bf29925a277d65317f84

5 years agoARM: tegra2: power: Fix reset race condition between the CPUs
Scott Williams [Thu, 11 Aug 2011 20:57:49 +0000]
ARM: tegra2: power: Fix reset race condition between the CPUs

During LP2 for CPU idle on Tegra2, there could be a race condition
between the CPUs. CPU1 cannot autonomously shut itself down (put
itself into reset). CPU1 must be reset by CPU0 but only when it
has no outstanding memory or I/O transactions going on (i.e., it
is in the WFI state). CPU1 indicates its readiness to be reset
by setting status in a PMC scratch register. If CPU1 wakes up
and CPU0 sees CPU1's ready to be reset status before CPU1 can
clear it CPU1 could be reset at inappropriate times resulting
in loss of cache coherency and ultimately a kernel panic.

Eliminate the race condition by ensuring that:

- CPU1's reset ready status is cleared as early as possible
  before CPU1 rejoins the coherent world.
- Use writel when updating the IRAM LP2 status flags to ensure
  the IRAM and coherent memory views of the flags are consistent.
- If there is not enough time remaining for CPU1 to be in LP2 for
  the minimum residency time, clear CPU1's reset status flag
  before entering WFI so that CPU0 will not wait for CPU1 to be
  ready to reset (since it won't be if there is insufficient time).

Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848

5 years agoARM: tegra: timer: Save TWD counter instead of load register
Scott Williams [Wed, 10 Aug 2011 21:18:37 +0000]
ARM: tegra: timer: Save TWD counter instead of load register

In tegra_twd_suspend(), save the remaining count rather than the
initial count of the timer.

Also catch invalid TWD configurations during suspend/restore
(e.g., enabled with a zero count).

BUG 862605

Change-Id: I05bf9e37f922a2b0a48cff23f1aa94ec8e8e039e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R6c7e5ae1220faee4564cd751fa6c94f7404ddc27

5 years agoARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2
Scott Williams [Wed, 10 Aug 2011 01:14:11 +0000]
ARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2

Don't try to flush the L1 D-cache for an aborted LP2 on the
secondary CPU if the L2 cache is enabled. The L1 cache will have
already been flushed and disabled by the suspend-side code.

Change-Id: If6fc7bd0f7d630e6cdcda6824411503f346c5405
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc50e525a320986432d2b125f82f846f94f605cc3

5 years agoARM: tegra: power: Map the CPU context page to tegra_pgd
Scott Williams [Wed, 10 Aug 2011 01:10:12 +0000]
ARM: tegra: power: Map the CPU context page to tegra_pgd

Add a mapping of the page used to save the CPU context to the
private pgd used during MMU shutdown.

Change-Id: I10ef282ff15ff5ee8469fcaa3637bcb0fb39ba4d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R837a2eb005ad93ef206153b120e972ee65383b65

5 years agoARM: tegra: power: Consolidate PM_SLEEP conditionals
Scott Williams [Wed, 10 Aug 2011 01:05:11 +0000]
ARM: tegra: power: Consolidate PM_SLEEP conditionals

Change-Id: If8f8868d929ec5bebe7c0083e03af504c7a6af11
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rf382a5bf2c7587ad496f2a88deaff75cb609f91c

5 years agoARM: tegra: power: Conditionalize diagnostic register save/restore
Scott Williams [Wed, 10 Aug 2011 01:01:49 +0000]
ARM: tegra: power: Conditionalize diagnostic register save/restore

Change-Id: I540d7272d585331da0241e7878dbb35557f0bb99
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R59fe634cc803ba2c9bb7916046aff5f92120f5c3

5 years agoARM: tegra: power: Fix build errors when DVFS is enabled
Scott Williams [Mon, 8 Aug 2011 20:41:53 +0000]
ARM: tegra: power: Fix build errors when DVFS is enabled

Change-Id: Icc37a1ac4fe1af3d08e579faf35ccb4ab1db1b1c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R786d091cccb765acb8d89acd59017ae993b78733

5 years agoARM: tegra: Fix mutex in atomic context when updating TWD freq
Scott Williams [Sat, 6 Aug 2011 01:16:48 +0000]
ARM: tegra: Fix mutex in atomic context when updating TWD freq

The CPU frequency change notifer runs in an atomic context but
obtaining the current CPU frequency requires taking a mutex because
updating the CPU frequency involves the regulator. Instead of
directly parenting the TWD clock on the CPU clock, make the TWD
a "detached child" of the CPU clock whose rate is updated whenever
the CPU frequency changes.

Change-Id: I49e15f85f269fb3ed0bcaee36ff739b4f064d6b8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7aa10f2576752390464586bc629c972802beb989

5 years agoARM: tegra: power: Rename variables for consistency
Scott Williams [Fri, 5 Aug 2011 01:41:41 +0000]
ARM: tegra: power: Rename variables for consistency

Rename Tegra3 CPU idle handler variables to be the same as their
Tegra2 counterparts for consistency.

Change-Id: I49a03182ff5a15d34847b3837f681ca842dcf643
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc71d7d71bebb197c983180429f24de7708d8dfea

5 years agoARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculation
Scott Williams [Fri, 5 Aug 2011 01:35:45 +0000]
ARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculation

CPU 0 must wake up before CPU 1 therefore CPU 0 must be awake by
the minimum of its or CPU 1's absolute wakeup time. However, the
the CPU idle request time is a duration not an absolute time.
Change the LP2 sleep time calculation to use an absolute "must
be away by" time.

Change-Id: Ia73dcbe071f81d0bd9fc6c5d860837e606575a8c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R138e6d4ae652932607f7dd411be3aa89ee53e34c

5 years agoARM: tegra: power: Save CPU context to non-cacheable stack
Scott Williams [Thu, 4 Aug 2011 20:32:10 +0000]
ARM: tegra: power: Save CPU context to non-cacheable stack

The standard cpu_suspend does not work if there is an exernal
L2 cache in the system individual CPUs are suspending without
shutting down the whole CPU complex. As a workaround for this
problem, we must save the CPU context to a non-cacheable region
of memory.

Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930

5 years agoARM: tegra: power: Add stack frame debug checks
Scott Williams [Thu, 4 Aug 2011 05:18:31 +0000]
ARM: tegra: power: Add stack frame debug checks

Tag the stack frame created by the CPU register context push
macro with a magic number and validate that magic number in
the register context pop macro to ensure that the stack
remains balanced and uncorrupted.

Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60

5 years agoARM: tegra: power: Define push/pop context register macros
Scott Williams [Thu, 4 Aug 2011 04:44:21 +0000]
ARM: tegra: power: Define push/pop context register macros

Define macros to ensure that the behavior of push/pop of the
context regsiter set is consistent across all callers.

Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4

5 years agoARM: tegra: power: Use uniform save/restore register set
Scott Williams [Thu, 4 Aug 2011 04:38:01 +0000]
ARM: tegra: power: Use uniform save/restore register set

Modify the register usage of tegra_cpu_save so that the same set
of registers is saved to and restored from the stack.

Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59

5 years agoARM: tegra: power: Use standard definitions for SCTLR
Scott Williams [Thu, 4 Aug 2011 03:36:21 +0000]
ARM: tegra: power: Use standard definitions for SCTLR

Change-Id: Ie2f619df4e5bff06960dcaa910a39d4cff78b879
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Ra75a8dba9e8f0fa57081a3fed9b3ef743b3c8796

5 years agoARM: tegra: power: Consolidate CPU context save and SMP exit
Scott Williams [Thu, 4 Aug 2011 02:07:51 +0000]
ARM: tegra: power: Consolidate CPU context save and SMP exit

Every call to tegra_cpu_save is always followed by a call to
tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save
by folding the CPU context save functionality of cpu_suspend and
the coherency exit functionality into a single function called
tegra_cpu_suspend.

Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8

5 years agoARM: tegra: power: Add SMP coherency exit macro
Scott Williams [Thu, 4 Aug 2011 00:33:37 +0000]
ARM: tegra: power: Add SMP coherency exit macro

Define the SMP coherency exit code as a macro to allow it to be
inlined in assembly code that needs to control its register usage.

Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a

5 years agoARM: tegra: power: Delete obsolete function
Scott Williams [Thu, 4 Aug 2011 00:08:54 +0000]
ARM: tegra: power: Delete obsolete function

Deleted tegra3_sleep_cpu which is never called by anything.

Change-Id: I59a737e92ed8bec222cec65252cc19592e171fd6
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1fabb1b9a728f1d4ff99643b4d31cfe7292c260d

5 years agoARM: tegra: Use common coherency exit function for Tegra2
Scott Williams [Wed, 3 Aug 2011 15:59:34 +0000]
ARM: tegra: Use common coherency exit function for Tegra2

Change-Id: Ibbc9c2a38fb654e24b1edb4ee7bbcaf285bf0f7d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R9ff092cf658b71d8f79ef3901bd5067d18548e69

5 years agoARM: tegra: power: Fix suspend pgd identity mapping
Scott Williams [Tue, 2 Aug 2011 20:33:01 +0000]
ARM: tegra: power: Fix suspend pgd identity mapping

The RAM identity mapping in the suspend pgd was based upon the
characteristics of the Tegra2 address map and would not work for
Tegra3. Change the mapping so that it's independent of the physical
address map characteristics.

Change-Id: Ib8f67c169f6b0988e88a4ef7616dfd48e66754ac
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R399b9624e8f25637538273642059e8d0719badf5

5 years agoARM: tegra: power: Allocate non-cacheable page for CPU context
Scott Williams [Tue, 2 Aug 2011 03:38:04 +0000]
ARM: tegra: power: Allocate non-cacheable page for CPU context

The standard cpu_suspend() mechanism doesn't work if there's an L2
cache controller like a PL310 in the system because there's no
effective way to flush the saved CPU context out to the L3 memory
system. Allocate a page of non-cacheable memory to hold the CPU
context. This save area will be utilized in a subsequent change.

Change-Id: I1e3bd60bd0bd19c1010905ef65ea0a8597ad6654
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R00d69f8cab6992ed729c1f6ef67fd38c999c3a5b

5 years agoARM: tegra: power: Put power functions under CONFIG_PM_SLEEP
Scott Williams [Tue, 2 Aug 2011 02:22:02 +0000]
ARM: tegra: power: Put power functions under CONFIG_PM_SLEEP

Place additional functions that are invoked only by code under
CONFIG_PM_SLEEP conditionals under CONFIG_PM_SLEEP conditionals
also.

Change-Id: I224ae07b9031038474b922422422a4feafcd94f1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R65b81ec60f59ae981fd668ad8354b14b8b4c83b9