5 years agoARM: tegra: bonaire: Add support for SMSC911X
Edgardo Handal [Tue, 19 Feb 2013 21:30:51 +0000]
ARM: tegra: bonaire: Add support for SMSC911X

Add support for using SMSC911X ethernet controller in bonaire

Change-Id: I2311a00ae80ee8fe507e12dd49ed5432a1d9a64a
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/202149
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra12: bonaire defconfig for l4t build
Bibek Basu [Tue, 19 Feb 2013 11:15:41 +0000]
arm: tegra12: bonaire defconfig for l4t build

This patch adds defconfig for bonaire and
bonaire_sim build for L4T

Bug 1211729

Change-Id: Ief358240f7389b89a39f031e95c4d8d5b5a3d12a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/202023
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stefan Becker <stefanb@nvidia.com>
Tested-by: Stefan Becker <stefanb@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: bonaire: add SPI support
Kunal Agrawal [Fri, 1 Mar 2013 04:53:42 +0000]
ARM: tegra: bonaire: add SPI support

added code to enable and initialize spi on
bonaire platform

Change-Id: I91bc591c8949c9c61512c60daa0794a95622d93c
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/205377
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: bonaire: Enable SDMMC3 controller
rrajk [Wed, 6 Mar 2013 08:31:43 +0000]
arm: tegra: bonaire: Enable SDMMC3 controller

Enabled SDMMC3 controller in bonaire.
Bug 1247029
Bug 1246725

Change-Id: Iaffea6cc6dd22dd865241ec518ec7ae534d0606c
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/206603
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agommc: host: tegra: Set internel Clk for t124 fpga
rrajk [Wed, 6 Mar 2013 08:34:57 +0000]
mmc: host: tegra: Set internel Clk for t124 fpga

Currently external clock loopback is not there on FPGA,
so use internal clock loopback.
Bug 1247029
Bug 1246725

Change-Id: Ibc53cb141c289e12526655b2995f97afc295e75b
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/206604
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: Update pinmux settings for SDMMC3
rrajk [Wed, 6 Mar 2013 08:28:54 +0000]
arm: tegra: Update pinmux settings for SDMMC3

Updated pinmux settings for SDMMC3 in bonaire.
Bug 1246725
Bug 1247029

Change-Id: I6c7f344caf7a572009e65dc099702bdda0549f4f
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/206602
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra12: Turn on LPAE for bonaire/bonaire_sim
Alex Van Brunt [Fri, 1 Mar 2013 00:06:51 +0000]
ARM: tegra12: Turn on LPAE for bonaire/bonaire_sim

This enables 64 bit physical addresses (LPAE) on bonaire and bonaire_sim.

Change-Id: Ida3ea9b2f3eabede7d855f57900cd6122baefc44
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/205316
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: Set dma_addr_t length with LPAE
Alex Van Brunt [Mon, 12 Nov 2012 23:57:24 +0000]
arm: tegra: Set dma_addr_t length with LPAE

On tegra platforms dma_addr_t and phys_addr_t should be the same.

Change-Id: I73a4fd1893f2a9711f0a9be23ed5c7eedc473453
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195685
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: mm: Use a page for the PGD with LPAE
Alex Van Brunt [Thu, 8 Nov 2012 23:57:36 +0000]
arm: mm: Use a page for the PGD with LPAE

Allocate a free page instead of useing kmalloc for the PGD. This is
needed to work with the pgd_list_{add|del}() functions that were added
to support the change_page_attr() function. Without it, the struct
page's "lru" list is corrupted by adding the same page to the list
twice because kmalloc would have already added it.

Change-Id: I2bb1a23df2f8af394f87756a167216fdc1f22a67
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: reduce panel size on simulator
Chao Xu [Wed, 6 Mar 2013 19:35:11 +0000]
ARM: tegra: reduce panel size on simulator

So the sanity regression runs faster.

Change-Id: Ide38de539433053e62ace12d3cc9be81096e3e21
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/206755
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>

5 years agoARM: tegra: bonaire: Update udc platform data
Petlozu Pravareshwar [Tue, 5 Mar 2013 19:14:10 +0000]
ARM: tegra: bonaire: Update udc platform data

Update the udc platform data to support usb device mode.

Change-Id: Ibe90ff3bcf53dda2fc9c721afe8b76639e8e36fc
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/206382
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agodrivers: video: tegra: Fix phys_add_t printing
Alex Van Brunt [Thu, 11 Oct 2012 18:29:52 +0000]
drivers: video: tegra: Fix phys_add_t printing

Use "%llx" to print variables with the type phys_addr_t.

Change-Id: I7e155dbf56b9118f16a92dcf5184acc9a56c048b
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195668

5 years agovideo: tegra: gk20a: Fixes for phys_addr_t
Alex Van Brunt [Thu, 11 Oct 2012 18:17:12 +0000]
video: tegra: gk20a: Fixes for phys_addr_t

Use "%llx" to convert phys_addr_t variables to strings and
remove the BUILD_BUT for phys_addr_t being bigger thatn 32 bits.

Change-Id: Ifcc1cfd62fb2971b4cd9c711cd13e8dbaa8adea9
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195667

5 years agoARM: mm: clean up membank size limit checks
Cyril Chemparathy [Fri, 20 Jul 2012 17:16:41 +0000]
ARM: mm: clean up membank size limit checks

This patch cleans up the highmem sanity check code by simplifying the range
checks with a pre-calculated size_limit.  This patch should otherwise have no
functional impact on behavior.

This patch also removes a redundant (bank->start < vmalloc_limit) check, since
this is already covered by the !highmem condition.

Change-Id: I6ee6ca1664aba3288af5c57280cf50d25407063a
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195676
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: mm: cleanup checks for membank overlap with vmalloc area
Cyril Chemparathy [Fri, 20 Jul 2012 16:24:45 +0000]
ARM: mm: cleanup checks for membank overlap with vmalloc area

On Keystone platforms, physical memory is entirely outside the 32-bit
addressible range.  Therefore, the (bank->start > ULONG_MAX) check below marks
the entire system memory as highmem, and this causes unpleasentness all over.

This patch eliminates the extra bank start check (against ULONG_MAX) by
checking bank->start against the physical address corresponding to vmalloc_min
instead.

In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.

Change-Id: I5dc3a7808f4a554b098b6333786af02647eab7fe
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195675
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: mm: use physical addresses in highmem sanity checks
Cyril Chemparathy [Fri, 20 Jul 2012 16:01:23 +0000]
ARM: mm: use physical addresses in highmem sanity checks

This patch modifies the highmem sanity checking code to use physical addresses
instead.  This change eliminates the wrap-around problems associated with the
original virtual address based checks, and this simplifies the code a bit.

The one constraint imposed here is that low physical memory must be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x < y must => pa(x) < pa(y).

Change-Id: I5ec769ff59ae69580167b02da23361693ed4dede
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195674
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: LPAE: use 64-bit accessors for TTBR registers
Cyril Chemparathy [Mon, 16 Jul 2012 21:20:17 +0000]
ARM: LPAE: use 64-bit accessors for TTBR registers

This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
the LPAE version of cpu_set_reserved_ttbr0() to use these instead.

In the process, we also fix these functions to correctly handle cases
where the physical address lies beyond the 4G limit of 32-bit addressing.

Change-Id: Ibf41d42fe59af020e1eb00d623cc5d5a483657e3
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195673
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: LPAE: use phys_addr_t in switch_mm()
Cyril Chemparathy [Mon, 16 Jul 2012 19:37:06 +0000]
ARM: LPAE: use phys_addr_t in switch_mm()

This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.

Change-Id: I596f50c4ff241b0769b43391de026b85c5774c6f
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195672
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: LPAE: use phys_addr_t for initrd location and size
Vitaly Andrianov [Fri, 22 Jun 2012 18:26:04 +0000]
ARM: LPAE: use phys_addr_t for initrd location and size

This patch fixes the initrd setup code to use phys_addr_t instead of assuming
32-bit addressing.  Without this we cannot boot on systems where initrd is
located above the 4G physical address limit.

Change-Id: Ib2967e18edb30695e5c40e918ecea37a1f074fdb
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195671
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: LPAE: use phys_addr_t in free_memmap()
Vitaly Andrianov [Thu, 21 Jun 2012 12:09:05 +0000]
ARM: LPAE: use phys_addr_t in free_memmap()

The free_memmap() was mistakenly using unsigned long type to represent
physical addresses.  This breaks on PAE systems where memory could be placed
above the 32-bit addressible limit.

This patch fixes this function to properly use phys_addr_t instead.

Change-Id: I4c62154017520d001bd97c1426b76d827c4842d0
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195670
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agoARM: LPAE: use phys_addr_t in alloc_init_pud()
Vitaly Andrianov [Tue, 10 Jul 2012 18:41:17 +0000]
ARM: LPAE: use phys_addr_t in alloc_init_pud()

This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
unsigned long when passing in the phys argument.

This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a (ARM:
pgtable: use phys_addr_t for physical addresses), which applied similar changes
elsewhere in the ARM memory management code.

Change-Id: I2ea4ad37cbec60cebbbe7513a4ef54e46ceed499
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195669
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>

5 years agovideo: tegra: host: Reassign T124 sync points
Terje Bergstrom [Fri, 1 Mar 2013 11:46:02 +0000]
video: tegra: host: Reassign T124 sync points

Reassign T124 sync points and remove overlaps. Also add a second
sync point for MSENC. Also moves all sync point definitions to the
same file.

Change-Id: I5f9fe9f671edc92f6b0fe35c521a1e896f5d3e48
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/205566
Reviewed-by: Amit Arora <amita@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agodrivers: video: nvmap: Fix ptr vs phys_addr types
Alex Van Brunt [Sat, 19 Jan 2013 00:57:26 +0000]
drivers: video: nvmap: Fix ptr vs phys_addr types

Use uintptr_t instead of phys_addr_t to store a pointer as an integer.

Change-Id: I164cc7b3a189d91a1926b74780d302af33cbf005
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195686
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra12: timer: Remove unused arch timer
Alex Van Brunt [Fri, 1 Mar 2013 00:53:18 +0000]
ARM: tegra12: timer: Remove unused arch timer

This code was needed before the merge from android-tegra-nv-3.7 fixed
arch_timer.

Now that it compiles, re-enable ARCH_TIMER for T12x

Change-Id: Ib026564652427e472e1644af34eb9f9bf4de2b08
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/205331
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: remove nvhost suspend hack after merge
Jin Qian [Fri, 1 Mar 2013 19:46:25 +0000]
drivers: video: tegra: remove nvhost suspend hack after merge

It's a revert of c3263479974bfb661316fdc48309eb4da72d5442.
The issue is fixed by previous change.

Bug 1244239

Change-Id: Ide5a624e5e3d2d471676ad8c6b390847466f3e63
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/205635
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: move gk20a init/deinit to probe/remove
Jin Qian [Thu, 28 Feb 2013 00:26:24 +0000]
drivers: video: tegra: move gk20a init/deinit to probe/remove

nvhost deinit gk20a before it's suspended in module idle after recent
merge from main. This is causing crash since suspend code requires
gk20a driver alive. Move init/deinit code to probe/remove to get around
this problem.

Bug 1244239

Change-Id: I699d41672c4c2c30f5f6266970ee322603035ad2
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/205247
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: Make AVP reservation section sized
Alex Van Brunt [Wed, 24 Oct 2012 23:34:16 +0000]
arm: tegra: Make AVP reservation section sized

With LPAE, sections are 2MB instead of 1MB. Use SECTION_SIZE to use
the correct size int eh LPAE and non-LPAE cases.

Change-Id: I78fb3b7f988aca0c176af7d20e90283fdb66f8ed
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/195680
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: pinmux settings for t12x SPI
Jin Qian [Thu, 28 Feb 2013 01:32:19 +0000]
ARM: tegra: pinmux settings for t12x SPI

Change-Id: Ibf14b66cc91ed78fc3615c0e17f90f858dffc10a
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/204893
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: config: Enable USB,SCSI,network config
Petlozu Pravareshwar [Fri, 1 Mar 2013 13:50:41 +0000]
ARM: tegra: config: Enable USB,SCSI,network config

Add SCSI, USB, Network config variables for the proper
functionality of usb host and device mode.

Change-Id: I51c3e6c4181e8fd9fb9ddfdf159ddbf3c30b37db
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/202911
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: phy: Add USB support on T12x_SOC
Petlozu Pravareshwar [Thu, 28 Feb 2013 07:08:51 +0000]
ARM: tegra: phy: Add USB support on T12x_SOC

Disable pllu_clk for 124 fpga.

Change-Id: If5ab0326971560d02ecf500596adb1d7a1a2a376
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/204637
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: bonaire: Add USB host support
Petlozu Pravareshwar [Wed, 27 Feb 2013 17:00:20 +0000]
ARM: tegra: bonaire: Add USB host support

Modifying board file sothat usb host works proper.

Change-Id: I4232c9b329728464bc145630d0cc42cf6b726018
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/202887
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoUSB: phy: update the Makefile
Petlozu Pravareshwar [Fri, 1 Mar 2013 06:49:58 +0000]
USB: phy: update the Makefile

Update Makefile for T12x_SOC.

Change-Id: I9d955f7681231edf88b4df43c3baab9faf71411b
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/205423
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: bonaire: Enable only SDMMC4
rrajk [Mon, 18 Feb 2013 06:56:04 +0000]
arm: tegra: bonaire: Enable only SDMMC4

Enabled only SDMMC4 controller for bonaire.
Bug 1218505

Change-Id: I04cef33d6900db4b57604161d5ec7f0a79e4b6a1
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/201626
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: config: enable mmc configs for bonaire
rrajk [Tue, 12 Feb 2013 15:47:04 +0000]
arm: tegra: config: enable mmc configs for bonaire

Bug 1218505

Change-Id: I50f7e0caf39382abe748a6e83884fdf3e1ab994f
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/200010
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agommc: host: tegra: Set number of pipe sates to zero
rrajk [Mon, 18 Feb 2013 09:14:33 +0000]
mmc: host: tegra: Set number of pipe sates to zero

Hack to set pipe stages to 0.

Bug 1218505

Change-Id: I7d1257c2afa2d82ac916bec94a155753e8e936b7
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/201704
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agotegra: bonaire: set SDMMC max clk support to 26MHz
rrajk [Mon, 18 Feb 2013 06:51:51 +0000]
tegra: bonaire: set SDMMC max clk support to 26MHz

As 26MHz supply is available to SDMMC controller,
this hack is necessary to handle ambiguity of clk setting
for SDMMC controller. Setting to 26MHZ is handled in our driver

Bug 1218505

Change-Id: I049feb7515c642e6e09c3066ebfb2ce3d1fa96a2
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/201623
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: Pinmux settings of eMMC for bonaire
rrajk [Mon, 18 Feb 2013 06:48:16 +0000]
arm: tegra: Pinmux settings of eMMC for bonaire

Enable pinmux settings for eMMC in bonaire.

Bug 1218505

Change-Id: I9fb1bd4ae9d8a29c5b8a634c0be8430668d7e300
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/201619
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: bonaire: enable 8bit support for eMMC
rrajk [Tue, 12 Feb 2013 16:12:04 +0000]
arm: tegra: bonaire: enable 8bit support for eMMC

Enabled 8bit support for eMMC in bonaire.
Bug 1218505

Change-Id: Id9ad7c25cc2dc3d95f94adf8861b0acc3adeef52
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/200016
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra12: clock: Add common EMC interface header
Alex Van Brunt [Tue, 26 Feb 2013 00:42:44 +0000]
ARM: tegra12: clock: Add common EMC interface header

Change-Id: Ie39ab61908c729e9c8ffd658f52ac6b5f7e7cb71
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203999
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra12: host: Make restore_push a common op
Alex Van Brunt [Sat, 23 Feb 2013 03:08:13 +0000]
video: tegra12: host: Make restore_push a common op

Add restore_push to vic03.

Change-Id: I5dc6f492c717549bd324fcb56e563ce1a9f86cc5
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203556
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoPartial revert: DNI: video: tegra: host: Init actmon with host1x on
Alex Van Brunt [Fri, 22 Feb 2013 21:07:31 +0000]
Partial revert: DNI: video: tegra: host: Init actmon with host1x on

Removing nvhost_module_suspend from nvhost_putchannel breaks gk20a
because it frees a data structure and then uses it.

For now, put it back in.

Change-Id: I7f542fbe86091db1c0078b6feea459c13b452396
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203475
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra12: nvmap: Fix redundant L2 flushes on t12x
Alex Van Brunt [Tue, 19 Feb 2013 23:28:45 +0000]
video: tegra12: nvmap: Fix redundant L2 flushes on t12x

Do the same for t12x as for t11x.

Change-Id: I86958ed6e58277b6f41eb1b4e61f74c1d2b9df79
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203357
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add common EMC interface header
Alex Van Brunt [Fri, 22 Feb 2013 17:15:44 +0000]
ARM: tegra12: clock: Add common EMC interface header

Change-Id: I42cdb350ba9c7380a1a3dbcce78951811cc6b9a2
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203356
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoi2c: tegra12: remove multiplexed bus option
Alex Van Brunt [Fri, 22 Feb 2013 17:28:20 +0000]
i2c: tegra12: remove multiplexed bus option

Remove the support for the pinmultiplexed based i2c bus driver.
Now i2c driver will support single bus per controller instance.
Bus number will be decided based on device id i.e. pdev->id.

Change-Id: Ia30bac1c0199270673d17b893e062bb4ab7aa968
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203355
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra12: host: Generalize hwctx parameters
Alex Van Brunt [Fri, 22 Feb 2013 18:29:31 +0000]
video: tegra12: host: Generalize hwctx parameters

Fixup t12x devices (vic03) to use nvhost_hwctx and
nvhost_hwctx_handler instead of the host1x versions.

Change-Id: Iee0c1707493922008f82f5db8cefed10fb5ed274
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203354
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra12: host: Remove 32 sync point limit
Alex Van Brunt [Fri, 22 Feb 2013 18:10:14 +0000]
video: tegra12: host: Remove 32 sync point limit

Remove the 32 sync point limit for t12x.

Bug 1050376
Bug 1034424

Change-Id: I4dba187dd59fb3d5dadd4a183327d3387572e7c1
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agotegra: video: add dc interlace mode support
Xue Dong [Wed, 13 Feb 2013 19:46:54 +0000]
tegra: video:  add dc interlace mode support

Bug 1172562

Signed-off-by: Xue Dong <xdong@nvidia.com>

Conflicts:

arch/arm/mach-tegra/include/mach/dc.h
drivers/video/tegra/dc/mode.c

Change-Id: I9e33ae73c60e0d98c5009a2a72c243d598bf084f
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/200502
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: Add base address for I2C6 controller
Sumit Sharma [Wed, 13 Feb 2013 05:31:08 +0000]
arm: tegra: Add base address for I2C6 controller

- Added base address for I2C6 controller for T12x
- Changed I2C5 controller size for adding I2C6 controller

Change-Id: Iec57fdee0ad131e503ab30a59b111458c60c444c
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200356
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: Enable I2C for board bonaire
Sumit Sharma [Thu, 14 Feb 2013 07:01:28 +0000]
arm: tegra: Enable I2C for board bonaire

Enabled I2C in bonaire defconfig

Change-Id: Ic8074068fe67ee6c5e5488cc3917c9edd267aaa5
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200361
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: Add I2C controllers for board bonaire
Sumit Sharma [Tue, 12 Feb 2013 09:20:08 +0000]
arm: tegra: Add I2C controllers for board bonaire

- Added I2C controller for T12x
- Changed bus count for I2C2 for adding I2C6

Change-Id: I69e536b27ada365610bb6d80aac06499ada44932
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200360
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: Use tegra14 i2c device for T124
Sumit Sharma [Tue, 12 Feb 2013 08:37:26 +0000]
arm: tegra: Use tegra14 i2c device for T124

Used tegra14_i2c_device for T12x
Based on http://git-master/r/#change,194544

Change-Id: Ie326fb68a2893c403db391826668753772ec5c1b
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200359
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: clock: Add clocks for T124 I2Cs
Sumit Sharma [Wed, 13 Feb 2013 05:43:43 +0000]
arm: tegra: clock: Add clocks for T124 I2Cs

Added I2C controller clocks for T12x

Change-Id: Ie668f7b0e8724e0b0f8f282cec7e2057d1ceaf06
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200357
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: Add irq for I2C6 controller
Sumit Sharma [Wed, 13 Feb 2013 05:29:47 +0000]
arm: tegra: Add irq for I2C6 controller

Added irq for I2C6 controller for T12x

Change-Id: I94216b6d679add46f3ca6eb9aea4323d34018d0c
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/200355
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: iomap: Add support for dma on T12x_SOC
Kunal Agrawal [Fri, 4 Jan 2013 07:06:10 +0000]
ARM: tegra: iomap: Add support for dma on T12x_SOC

Add support for dma on T12x_SOC

Bug 1205729

Change-Id: Iedc90f3615a98f7de1950bf9a6cff073bd44ff25
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/188584
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
(cherry picked from commit eab1167b596b2bf712663933807432215a65edb0)

Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Change-Id: I64f80ff314cb2042313e3d329be32ca4fbdbcd5c
Reviewed-on: http://git-master/r/200674
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra12: clock: Update clocks for cl 16971678
Chao Xu [Mon, 11 Feb 2013 19:37:33 +0000]
ARM: tegra12: clock: Update clocks for cl 16971678

Change-Id: Ibc8d69d57a63fa034749a132c7daf2d3423dd98f
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/199550

5 years agovideo: tegra: Update headers to cl 16971678
Chao Xu [Tue, 12 Feb 2013 18:10:51 +0000]
video: tegra: Update headers to cl 16971678

Change-Id: Ic958039601bb1a33373781e06c52bb6302c35ea3
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200059
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jin Qian <jqian@nvidia.com>

5 years agoarm: tegra: Update readl/writel calls
Alex Van Brunt [Thu, 31 Jan 2013 18:53:31 +0000]
arm: tegra: Update readl/writel calls

readl and writel now take void * instead of u32. Update the way they
are called to reflect this change.

Change-Id: I5b7ae6bf52003cdbb9f7ea1fd6cf365f8bc3356f
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/196098
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: dvfs: Add dvfs tables per bin
Bhanu Chetlapalli [Tue, 20 Nov 2012 21:15:24 +0000]
ARM: tegra12: dvfs: Add dvfs tables per bin

Picked from tegra11 & applied to tegra12
Original Commit: f951fca6b5ca2eeac53083d8728d83f01463744b

Changed core dvfs table differentiation ID from speedo_id to
process_id. Separated 3D/2D/EPP tables into 2 bins, and updated
dvfs limits according to the characterization input.

Bug 1161126

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Change-Id: I5ce262935eecf689149aaa773e225b9cd845996e
Reviewed-on: http://git-master/r/194796
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200199
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Increase EMC and GPU maximum rate limits
Bhanu Chetlapalli [Tue, 20 Nov 2012 21:06:32 +0000]
ARM: tegra12: dvfs: Increase EMC and GPU maximum rate limits

Picked from tegra11 & applied to tegra12
Original Commit: fdb8832d96220bce7b432d3fec3f5d7089adae05

- Increased PLLM and EMC clocks maximum rate limits to 1066MHz.
- Increased 3D/2D/EPP and cbus clocks maximum rate limits to 700MHz.

Bug 1161126

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Change-Id: I08e0b3b4c4b05dcc82c8898adc42832ac9358381
Reviewed-on: http://git-master/r/194795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200198
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: power: Add core EDP basic implementation
Bhanu Chetlapalli [Thu, 15 Nov 2012 06:16:18 +0000]
ARM: tegra12: power: Add core EDP basic implementation

Picked from tegra11 & applied to tegra12
Original Commit: a61a220e2d18242e425037e9f1c91e49ebb07ed0

Added mechanism to limit maximum GPU and memory frequency in order
to keep core rail current within power supply capabilities. The
actual limits yet to be characterized, and they will depend on

(a) Chip SKU
(b) Regulator current limit
(c) Slow (LP) CPU state (On/Off)
(d) Temperature range (trip-points TBD)
(e) User profile (balanced, favor GPU, favor EMC)
(f) Core module state (reserved)

Dependencies (a) and (b) are resolved statically when core EDP
is initialized for the particular chip. Core EDP limits will be
changed dynamically when run-time conditions (c), (d), (e), and
(f) are changed.

This commit implements only initialization of the core EDP limits
table and debugfs access to the table. Dynamic control is not
implemented. EDP table data is just a template.

Core EDP configuration option is unselected by default.

Bug 1165638

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I96a7f20a557834782a8c907c2ad67d5fce2d006b
Reviewed-on: http://git-master/r/194794
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200197
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: dvfs: Don't set common core edp default voltage
Bhanu Chetlapalli [Sun, 18 Nov 2012 06:46:16 +0000]
ARM: tegra: dvfs: Don't set common core edp default voltage

Picked from tegra11 & applied to tegra12
Original Commit: 6ed8068de3e30d50c4d695f9cb4bf093b864a24f

Removed 1.2V default core edp voltage setting from common code.
Let Tegra family specific dvfs layers to set different defaults:
1.2V for Tegra3, and 1.1V for Tegra11 (Tegra2 does not support
core edp limits at all).

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I329369b9ec34648d0dfac65add96ca2af83609f1
Reviewed-on: http://git-master/r/194793
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200196
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update system bus dvfs table
Bhanu Chetlapalli [Wed, 14 Nov 2012 05:51:47 +0000]
ARM: tegra12: dvfs: Update system bus dvfs table

Picked from tegra11 & applied to tegra12
Original Commit: 78e55efce27c4d1c3d81a94ff902b2f879e19174

Bug 1161126

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I73a101b0c41edd00681110f88ca44fe054cec4c0
Reviewed-on: http://git-master/r/194792
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200195
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: dvfs: Recompute EDP tables after dfll mode changes
Bhanu Chetlapalli [Tue, 6 Nov 2012 21:19:25 +0000]
ARM: tegra: dvfs: Recompute EDP tables after dfll mode changes

Picked from tegra11 & applied to tegra12
Original Commit: b15119fcc3a0258541ac2f40ad87da438d031f55

Also recompute on clock-late-init for EDP table with correct dfll mode

Bug 1167145

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ia18053123d4327b199ca10953c89d9246cc6d5c4
Reviewed-on: http://git-master/r/194791
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200194
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Force nominal voltage with no EMC DFS
Bhanu Chetlapalli [Wed, 14 Nov 2012 05:05:46 +0000]
ARM: tegra12: dvfs: Force nominal voltage with no EMC DFS

Picked from tegra11 & applied to tegra12
Original Commit: 76fe5cce57a49278e8698d65cf40948a40ca94b9

Made sure core voltage is pegged at nominal level when there is no
EMC DFS table provided.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I7ac00958e838e6f425b0f3350cabe7582d73fa44
Reviewed-on: http://git-master/r/194790
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200193
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/C3 settings
Bhanu Chetlapalli [Thu, 8 Nov 2012 05:20:20 +0000]
ARM: tegra12: clock: Update PLLC2/C3 settings

Picked from tegra11 & applied to tegra12
Original Commit: d7e375f273d1819d241db8fa437e9b1563136d38

Bug 1057353

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I21cc0b984f02ba3519c7315fe107177889c01729
Reviewed-on: http://git-master/r/194789
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200192
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add shared bus override users
Bhanu Chetlapalli [Tue, 6 Nov 2012 07:21:34 +0000]
ARM: tegra12: clock: Add shared bus override users

Picked from tegra11 & applied to tegra12
Original Commit: f079f62e33c16f703afed0c71f17e6977600a980

Added shared bus override users to allow testing of shared bus
mechanisms.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ib630d3d61a6aa7ee88b9b1231cfd2d6dad033c2a
Reviewed-on: http://git-master/r/194788
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200191
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Remove not used i2c fast clocks
Bhanu Chetlapalli [Tue, 6 Nov 2012 05:53:22 +0000]
ARM: tegra12: clock: Remove not used i2c fast clocks

Original commit: c3addcce7de841ae83a94723fc3ddd7d328a5a80

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I2ecbc084e57692f02761d984aeebd7a98136d8aa
Reviewed-on: http://git-master/r/194787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200190
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update emc to cpu rate ratio limits
Bhanu Chetlapalli [Wed, 7 Nov 2012 00:15:09 +0000]
ARM: tegra12: clock: Update emc to cpu rate ratio limits

Original commit: 4d0f63f0082d88a719dd66f3f795d1cf6857be71

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ie16d81d34e2d8825942ce87b8a0a049ddcecbd8e
Reviewed-on: http://git-master/r/194786
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200189
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update parameterized cluster switch
Bhanu Chetlapalli [Sun, 4 Nov 2012 03:15:06 +0000]
ARM: tegra12: clock: Update parameterized cluster switch

Picked from tegra11 & applied to tegra12
Original Commit: 7b1052716838a442a86a63a0dbbf9f9d1cb6c99e

Adjusted CPU rate during parametrized (enforced from sysfs) cluster
switch, so that target rate meets min/max constraints on both sides
of the switch. Ported commit c27f5a2e7380cb667f1f6a4ba61daf67c63ef2d4.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ia9c78ddd61a940d3530465d4bf7831b2f74e7dd9
Reviewed-on: http://git-master/r/194785
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200188
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: clocks: add frequency stats support for dual cbus
Bhanu Chetlapalli [Wed, 17 Oct 2012 03:09:17 +0000]
ARM: tegra: clocks: add frequency stats support for dual cbus

Picked from tegra11 & applied to tegra12
Original Commit: 3f3a475953c6d7b25873a300e61936d3410b11c1

Add frequency stats support for c2bus and c3bus

Bug 1026583

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I73dbfd8d6f140dc29fac52eae3ec13c7c1b7f662
Reviewed-on: http://git-master/r/194784
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200187
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoARM: tegra12: dvfs: Update miscellaneous dvfs tables
Bhanu Chetlapalli [Thu, 25 Oct 2012 07:07:38 +0000]
ARM: tegra12: dvfs: Update miscellaneous dvfs tables

Ignoring some tables in merge, to be rectified later

Picked from tegra11 & applied to tegra12
Original Commit: c9a4e799f260fa9e9b38c8eb86c911775b942f59

- Updated dvfs tables for SBUS (system clock), Host1x, and VI clocks
- Updated maximum limits for Host1x and MSELECT clocks
- Allowed only integer divisors for Host1x, VI, and MSELECT clocks

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 03a2546f2745dab8a8adda72777a062b7c113865)
Change-Id: Iab969f3753caabc9901bcef09b1fff4e8dd82db2
Reviewed-on: http://git-master/r/194783
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200186
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoARM: tegra12: clock: Do not allow 1:1.5 clock dividers ratio
Bhanu Chetlapalli [Thu, 25 Oct 2012 06:45:24 +0000]
ARM: tegra12: clock: Do not allow 1:1.5 clock dividers ratio

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 723f73ae73cacb4274b2b671a8454f5741dae712)
Change-Id: Ibb1a32b62cd250e498e4009ef276664cacc9aa1f
Reviewed-on: http://git-master/r/194782
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/200185
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agodrivers: video: tegra: fix gk20a pmu perfmon buffer alloc
Jin Qian [Tue, 29 Jan 2013 00:12:49 +0000]
drivers: video: tegra: fix gk20a pmu perfmon buffer alloc

sample_buffer was left uninitialized and allocator assumes it's
fixed address allocation.

Bug 1218938

Change-Id: I403d806bac59ef4b72078c1eb8d63ebce9651e41
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/200124
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: video: tegra: fix gk20a pmu race conditions
Jin Qian [Mon, 28 Jan 2013 19:00:24 +0000]
drivers: video: tegra: fix gk20a pmu race conditions

Bug 1220500

Change-Id: I512324e8e23c633ed0f364d064f2defe2ded280c
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/200123
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra12: Add DEBUG_LL_INCLUDE fro DCC
Alex Van Brunt [Mon, 11 Feb 2013 22:00:33 +0000]
arm: tegra12: Add DEBUG_LL_INCLUDE fro DCC

Add the new CONFIG_DEBUG_LL_INCLUDE option to enable DCC printing.

Bug 1233889

Change-Id: Id44c62f9cea3d8daf1d5e43e1a547871fdb38878
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/199710
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clocks: Enable VDE clocks for ASIM
Bhanu Chetlapalli [Fri, 21 Dec 2012 00:09:00 +0000]
ARM: tegra12: clocks: Enable VDE clocks for ASIM

Change-Id: I0a6431adae66a40661ca1e8358b5d3638c9ce888
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-on: http://git-master/r/200019
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoarm: tegra: Make the kernel easier to debug
Alex Van Brunt [Thu, 31 Jan 2013 17:50:55 +0000]
arm: tegra: Make the kernel easier to debug

Select READABLE_ASM when DEBUG_KERNEL is selected. This turns off
block reordering optimizations in GCC. The result is asm code that is
in the same order as the C code.

Change-Id: Ic65162e766960af06ed975effe853979ead932fc
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/196066
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra12: Fix misc compiler warnings
Alex Van Brunt [Thu, 31 Jan 2013 16:07:03 +0000]
arm: tegra12: Fix misc compiler warnings

Add a return statement to tegra_cpuidle_init_soc for the case that a
chip doesn't have a *_cpuidle_init_soc function.

Remove the declaration of arch_timer_register when struct arch_timer
is not defined.

Change-Id: I0986ae5b051cc30d0d2b78d04685b3685e4f8a5e
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/196038
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra12: mc: Update readl/writel calls
Alex Van Brunt [Thu, 31 Jan 2013 19:03:29 +0000]
arm: tegra12: mc: Update readl/writel calls

readl and writel now take void * instead of u32. Update the way they
are called to reflect this change.

Change-Id: Ib8fa088bd70001dedd55828298e5c4311a9b2a4e
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/196097
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra12: clocks: Update readl/writel calls
Alex Van Brunt [Thu, 31 Jan 2013 18:42:22 +0000]
arm: tegra12: clocks: Update readl/writel calls

readl and writel now take void * instead of u32. Update the way they
are called to reflect this change.

Change-Id: Id2b13a8e962fb53989009ffecbc0fad8e4da4bc4
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/196096
Reviewed-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: Clean up SoC dependent include
Kaz Fukuoka [Mon, 13 Aug 2012 20:35:25 +0000]
ARM: tegra: Clean up SoC dependent include

Change-Id: I88120746d5e6c7e0ef4a1962e40626aab69a1a86
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/123161
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/196595
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Reduce core voltage range
Bhanu Chetlapalli [Wed, 24 Oct 2012 21:15:25 +0000]
ARM: tegra12: dvfs: Reduce core voltage range

Picked from tegra11 & applied to tegra12
Original Commit: 9ba85b8a58171f7c6cc96029b3b08d41d27c269f

For initial testing of core voltage scaling s/w reduced core voltage
range from [0.9V ... 1.125V] to [1.0V ... 1.120V].

Bug 116126

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 1282fa23b54c2cfdedfeaa439a1cb5945d04b5ad)
Change-Id: I5e204162efe42a76c474e463af48eb4690d9cac6
Reviewed-on: http://git-master/r/193151
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Rename bus user comparison ops
Bhanu Chetlapalli [Sun, 28 Oct 2012 06:28:58 +0000]
ARM: tegra12: clock: Rename bus user comparison ops

Picked from tegra11 & applied to tegra12
Original Commit: 3ba695c206588e0d3aebf066b6236062a0fb23a0

Renamed bus user comparison operations from "cbus_user_is_xxx"
to "bus_user_is_xxx", as they can be applied to non cbus users
as well.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ibb0ea860d3dbf5383d43597e0683052cc11f3468
Reviewed-on: http://git-master/r/193150
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update DFLL range configuration
Bhanu Chetlapalli [Sat, 27 Oct 2012 02:01:57 +0000]
ARM: tegra12: dvfs: Update DFLL range configuration

Picked from tegra11 & applied to tegra12
Original Commit: 63e37d089bb55dbdd768ff711e1ed4cecac4615a

Replaced boolean DFLL usage configuration option with integer
TEGRA_USE_DFLL_RANGE option that specifies default range for
DFLL to be used as CPU clock source:
"0" - DFLL is not used,
"1" - DFLL is used as a source for all CPU rates
"2" - DFLL is used only for high rates above crossover with
PLL dvfs curve

Made sure that valid cvb tables for DFLL and PLL modes provide
crossover between DFLL and PLL dvfs voltage ranges.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I3e2848ee7473f338ac6dff31e84b117f9dc27756
Reviewed-on: http://git-master/r/193149
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12:clock:update UTMIPLL register program
Bhanu Chetlapalli [Wed, 31 Oct 2012 05:17:59 +0000]
ARM: tegra12:clock:update UTMIPLL register program

Picked from tegra11 & applied to tegra12
Original Commit: 0a3d8af649ade2aef589f84aee3bf971b5854290

Update the UTMIPLL register programming sequence
to let hardware control UTMIPLL.

Bug 1057339

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: If71896e55f60c8d3db5523a7dd880b413a71916e
Reviewed-on: http://git-master/r/193148
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Don't convert EMC shared user requests
Bhanu Chetlapalli [Tue, 30 Oct 2012 03:43:00 +0000]
ARM: tegra12: clock: Don't convert EMC shared user requests

Picked from tegra11 & applied to tegra12
Original Commit: b44de185c080d81f3e6f772dd618ca4db3e9adee

Removed conversion of EMC shared bus users bandwidth requests to EMC
bus width. Let the client drivers do it.

Bug 1167105

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I6f3bafb7675d630211e3a6cacc8d4cb630b85f7c
Reviewed-on: http://git-master/r/193147
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: dvfs: Update rail statistic
Bhanu Chetlapalli [Sat, 20 Oct 2012 06:04:29 +0000]
ARM: tegra: dvfs: Update rail statistic

Picked from tegra11 & applied to tegra12
Original Commit: 052bffe3f75579fe309d96d1ccc805110a2328e3

- Replaced fixed rail bins with per-rail-per-platform bins (by
default use backward compatible 12.5mV bin)
- On Tegra11 set bins for all rails on cvb alignment boundary (10mV)
- Increased maximum number of bins to 50
- Fixed rail voltage report in dfll mode: compensate 1mV adjustment
used in this mode to force voltage update

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I391e93b3b4d9aa97ea0b2e1ccde50fb08788969d
Reviewed-on: http://git-master/r/193146
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: clock: Rename shared bus operations.
Bhanu Chetlapalli [Tue, 30 Oct 2012 04:12:49 +0000]
ARM: tegra: clock: Rename shared bus operations.

Picked from tegra11 & applied to tegra12
Original Commit: 24f6ea855a1014a3ee65fe96ca1d616190a337d1

Renamed shared_bus operations that are actually applied to bus
user clock (rather than bus clock itself) to shared_bus_user
operations.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Change-Id: Ife2e3d52012329916917de32120fd0eb6207aebc
Reviewed-on: http://git-master/r/193145
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Combine DFLL usage controls
Bhanu Chetlapalli [Wed, 24 Oct 2012 02:50:05 +0000]
ARM: tegra12: clock: Combine DFLL usage controls

Picked from tegra11 & applied to tegra12
Original Commit: 40a825a9b37b359c2330cba272264bd024cbde4d

Replaced 2 boolean DFLL usage controls: use_dfll and use_pll_cpu_low
with one integer use_dfll parameter. Integrated this common control
into dfll.data structure as the following enumeration:

0 = DFLL_RANGE_NONE - DFLL is not used as CPU clock source

1 = DFLL_RANGE_ALL_RATES - DFLL is used as CPU clock source at all
rates

2 = DFLL_RANGE_HIGH_RATES - DFLL is used as CPU clock source at high
rates above use_dfll_rate_min, CPU source is automatically switched
from DFLL to PLL when use_dfll_rate_min threshold is crossed down,
and from PLL to DFLL when it is crossed upwards. In the latter case
do not clip target rate to pll mode maximum even though the switch
starts while CPU is on PLL.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 78733e5984ac08ed3667414dd3a770eb4f306a67)
Change-Id: I8c85bb32d44eaf3d8e0755909cf51b1d61fa8933
Reviewed-on: http://git-master/r/193144
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: clock: Keep CPU voltage above DFLL Vmin
Bhanu Chetlapalli [Tue, 23 Oct 2012 02:48:38 +0000]
ARM: tegra: clock: Keep CPU voltage above DFLL Vmin

Picked from tegra11 & applied to tegra12
Original Commit: 251098311d88f58043979ee7c9ce86d6a398f5c5

Updated DFLL On/Off procedures to keep CPU voltage above DFLL Vmin
during transition. This change is necessary now, as it is no longer
true that dvfs voltage in pll mode is above dfll mode voltage at all
rates.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 024210cfa6dd6173fe4edc4f0ed722a89ea370ce)
Change-Id: Ibaa198f990411499d09ed08f7499dc12159c658e
Reviewed-on: http://git-master/r/193143
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: clocks: Lower EMC min frequency to 12.75MHz
Bhanu Chetlapalli [Sun, 30 Sep 2012 21:34:34 +0000]
ARM: tegra: clocks: Lower EMC min frequency to 12.75MHz

Picked from tegra11 & applied to tegra12
Original Commit: af202ce47be32789db41645e625766ab24c72481

Lower EMC minimum frequency to 12.75MHz.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 01a4ca3c4d8ed2ac83bb51b86e2f4c8d970336ff)

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I762eae805cf44e6224f581cb510d7d7b89872586
Reviewed-on: http://git-master/r/193142
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update CPU DVFS tables
Bhanu Chetlapalli [Sat, 20 Oct 2012 02:38:01 +0000]
ARM: tegra12: dvfs: Update CPU DVFS tables

Picked from tegra11 & applied to tegra12
Original Commit: 205aedfd26ceca0305a739c35d188ba4b0a0fda7

Updated new cvb coefficients, dfll tuning parameters, maximum
voltage to 1.25V.

Bug 1161126

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 351020d6e0a8b90faf60cd96a9f2d66bb48025fb)
Change-Id: I757213e5e4a6ac71a5db4f66f8da903576189063
Reviewed-on: http://git-master/r/193141
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Fix cpufreq table construction
Bhanu Chetlapalli [Sat, 20 Oct 2012 07:53:23 +0000]
ARM: tegra12: clock: Fix cpufreq table construction

Picked from tegra11 & applied to tegra12
Original Commit: 309ce9f758516fcbc92fda9cd1c6fa02dcb03a12

Fixed cpufreq table construction in case of overlapping LP and G CPU
frequency ranges: made sure minimum G CPU rate is inserted into the
table once (was inserted before each LP CPU frequency that exceeds
G CPU minimum).

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 5caf5eaff268b6f55ef5361b508d84c5ef6b862f)
Change-Id: I9f78489fd2fd27f41a3a5b4679b079ad0f7f06d3
Reviewed-on: http://git-master/r/193140
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Use dfll below Fmax@Vmin
Bhanu Chetlapalli [Thu, 18 Oct 2012 04:39:54 +0000]
ARM: tegra12: dvfs: Use dfll below Fmax@Vmin

Picked from tegra11 & applied to tegra12
Original Commit: fd59b79ee5b384509346818c0c82530b283712f7

When CPU clock source switch from DFLL to PLL at low rate is enabled,
don't exit DFLL mode unconditionally for rates below Fmax@Vmin. If
required PLL voltage is above Vmin, stay on DFLL (and engage output
skipper to reach target rate).

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 1505458c08feabc60c2806c2f45ebdde62885b39)
Change-Id: I3083e6d2911884a379276f8ef3f146911b4371b0
Reviewed-on: http://git-master/r/193139
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra14: clocks:Handle CL-DVFS not selected on T148
Bhanu Chetlapalli [Thu, 25 Oct 2012 20:11:05 +0000]
ARM: tegra14: clocks:Handle CL-DVFS not selected on T148

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I5be67dde0700d7de274747ea18c351e5856d0e5f
Reviewed-on: http://git-master/r/193138
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoasoc: tegra: cs42l73: slave mode support
Bhanu Chetlapalli [Thu, 11 Oct 2012 06:52:23 +0000]
asoc: tegra: cs42l73: slave mode support

Picked from tegra11 & applied to tegra12
Original Commit: 088b16dac2b3409801ff37c6f5d0be08c9f3e5b7

I2S changed to slave mode
Add Schmidt trigger enable for DAP2
Add devid and conid for sync clock lookup
Configured DAP direction to INPUT
Audience configured for PORTA -> PORTC passthrough

Bug 1062554

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit f329532f3b76a276c2f1219ff6422510b5a8ed9d)
Change-Id: I8f57225919242c21a60e2f06aeae25853c43b3dd
Reviewed-on: http://git-master/r/193137
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: pluto: increase dsi max frequency
Bhanu Chetlapalli [Thu, 27 Sep 2012 22:20:03 +0000]
ARM: tegra: pluto: increase dsi max frequency

Picked from tegra11 & applied to tegra12
Original Commit: 0deb9ad25848e0079bad564ab3b9ecb00a7f05bd

Increase dsi maximum frequency to 500Mhz.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 5fa0c69175a1a4ebb81d5686d5b0c4e4b883726f)
Change-Id: Id63b98f2512bd26543660ba73fb0ef87b29be5c1
Reviewed-on: http://git-master/r/193136
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: power: enable dynamic VDD_CPU EDP capping
Bhanu Chetlapalli [Fri, 21 Sep 2012 08:02:42 +0000]
arm: tegra: power: enable dynamic VDD_CPU EDP capping

Picked from tegra11 & applied to tegra12
Original Commit: 526812684ac41bcf20eb452628498fc200e0964a

Using the model used to enforce max frequency for a given VDD_CPU EDP.
Enabled for dalmore and pluto.

Initialised edp_reg_override to 6A and increased default per-platform
edp-limit higher by 6A to allow users to override the limit up by upto
6A when needed for specific use-cases.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
(cherry picked from commit 9648d86f4a9a7b3b2557e98530e8265ea9f53467)
Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ie6deec42bd555f2395d72337747cacb18d794bcb
Reviewed-on: http://git-master/r/193135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Put UTMIPLL under h/w control
Bhanu Chetlapalli [Wed, 10 Oct 2012 05:25:08 +0000]
ARM: tegra12: clock: Put UTMIPLL under h/w control

Picked from tegra11 & applied to tegra12
Original Commit: 32fdc7f8d32e47ec0c9e893bbe47d65d54cfe2dc

Programming UTMIPLL register to let hardware to
control UTMIPLL.

Bug 1057339

(cherry picked from commit 6ff04c9acbb229e22410f7d70e4e127dc6768a34)

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: I646c56ba1dfdbeaf2e29984b1f39d68c0bb593b6
Reviewed-on: http://git-master/r/193134
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: fix curacao_sim build break
Bhanu Chetlapalli [Mon, 22 Oct 2012 17:47:59 +0000]
ARM: tegra12: clock: fix curacao_sim build break

Picked from tegra11 & applied to tegra12
Original Commit: 2597328141764ab70cd703a10303d246bd810715

Fixes unused warning-as-error problems with curacao_sim
build target.

Signed-off-by: Bhanu Chetlapalli <bchetlapalli@nvidia.com>
Change-Id: Ibcf040e66e67ceba641e7c81fc0d4cff5ab02abd
Reviewed-on: http://git-master/r/193133
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>