5 years agoarm: tegra: init tn8 and ardbeg as separate devices
Ahung Cheng [Mon, 29 Jul 2013 10:06:40 +0000]
arm: tegra: init tn8 and ardbeg as separate devices

Need to call DT_MACHINE_START for each platform so that
ro.hardware property is set according to platform name.
This also enforces one dts file per platform.

Bug 1328162

Change-Id: I368669af638ec2ee237fe090ad70c0d63375fef1
Signed-off-by: Ahung Cheng <ahcheng@nvidia.com>
Reviewed-on: http://git-master/r/255003
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agousb: xhci: tegra: save dfe value to ss port registers
Ajay Gupta [Wed, 24 Jul 2013 18:22:30 +0000]
usb: xhci: tegra: save dfe value to ss port registers

Bug 1333330

Change-Id: I8bd1f826ef6526e5116c09a2677ae67259bfff92
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253581
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agoARM: tegra: ardbeg: fix gpio expander number
Ajay Gupta [Wed, 24 Jul 2013 00:10:53 +0000]
ARM: tegra: ardbeg: fix gpio expander number

GPIO expander numbers are indexed as 0-7 and then 10-17 so
P11 maps to base + 9

Bug 1338745

Change-Id: Iddce1a4468257f31da27a48c4b94140e002cbf7a
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253580
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agousb: xhci: tegra: program SATA PAD PLL
Ajay Gupta [Mon, 22 Jul 2013 18:13:49 +0000]
usb: xhci: tegra: program SATA PAD PLL

Needed as per updated BCT from hw team

Bug 1338745

Change-Id: I9d2dd57ef5d91d02fa6226abd9bfc8bf7c7de145
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253579
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agoARM: tegra: decide UTMIP1/2 ownership based on odmdata[25]
Ajay Gupta [Fri, 19 Jul 2013 18:07:49 +0000]
ARM: tegra: decide UTMIP1/2 ownership based on odmdata[25]

XUSB should own UTMIP1/2 when odmdata[25] is set.

Bug 1338735

Change-Id: I19d26859e969d04d261f01c1e6d873fced853076
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253578
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agovideo: tegra: gk20a: turn on cya15 bit in l1c_dbg
Ashish Srivastava [Tue, 16 Jul 2013 08:41:39 +0000]
video: tegra: gk20a: turn on cya15 bit in l1c_dbg

Setting the CYA15 bit to 1 in the L1C_DBG register.
Note: we'll re-code this without the magic when the register
makes it into the hw_gr_gk20a.h file.

Change-Id: I7337bef1d86db3a584d6bec0563068a37a6d3723
Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com>
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/256377

5 years agoARM: tegra: bbc: call pm_wakeup_event() in IRQ if going to suspend
Hervé Fache [Fri, 7 Jun 2013 12:43:31 +0000]
ARM: tegra: bbc: call pm_wakeup_event() in IRQ if going to suspend

If an IRQ is fired as we are going to suspend then we want to abort
and make sure voltage and frequency remain high enough for BB to
operate.

The suspend function must not ack the IRQ as the handler shall be
fired and do it.

Bug 1294872

Change-Id: I20e3872b58814402e5ee5945bb6d91c2651eaacb
Signed-off-by: Hervé Fache <hfache@nvidia.com>
Reviewed-on: http://git-master/r/239765
(cherry picked from commit 022b42d27f9dcd3614cd44d297326c8778c66840)
Reviewed-on: http://git-master/r/256176
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: gk20a: use correct dma_len during gmmu map/unmap
Krishna Reddy [Tue, 30 Jul 2013 23:15:52 +0000]
video: tegra: host: gk20a: use correct dma_len during gmmu map/unmap

Bug 1339218

Change-Id: I90c8680b3b4bfb3306789b785069066b83a0793d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/255788
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: clocks: Remove always ON for SDMMC clk
Pavan Kunapuli [Tue, 30 Jul 2013 10:54:17 +0000]
ARM: tegra: clocks: Remove always ON for SDMMC clk

SDMMC clocks need not be enabled by default for T12x.

Bug 1328858

Change-Id: Id8283c83f0e520275125128e822e7960a288f9a9
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/255601
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agommc: sdhci: Enable host clock before reg access
Pavan Kunapuli [Tue, 30 Jul 2013 10:51:16 +0000]
mmc: sdhci: Enable host clock before reg access

Some SDMMC controllers require host clock to be enabled before accessing
the controller registers. Define SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK to
handle this behavior.

Ensure clock is enabled before register accesses in suspend/resume path.

Enabled SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK for Tegra SDMMC controllers.

Bug 1328858

Change-Id: I732d0597a715c96bc546beb4bba1beb86e51c302
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/255600
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agommc: core: set mmc signal voltage after clk is turned on
Kerwin Wan [Mon, 15 Jul 2013 22:29:57 +0000]
mmc: core: set mmc signal voltage after clk is turned on

The controller clk will be turned on then turned off when mmc does
power up setting. System will hang if signal voltage is set with clk is off.
After mmc does power on settings, the controller clk will be on so it's safe
to set signal voltage at that time.

Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/249393
(cherry picked from commit bcf30d2b52713acb87fef895635521ac3d3d2855)

Bug 1328858

Change-Id: I992ebd01794574e6236c4bf67480d343b3cfc24a
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/255599
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>

5 years agoasoc: tegra: fix NULL pointer dereference
Deepak Nibade [Tue, 30 Jul 2013 08:42:20 +0000]
asoc: tegra: fix NULL pointer dereference

- fix Coverity issues
- fix dereference of null pointer
  Coverity id : 23721
  Coverity id : 23735

Bug 1329327

Change-Id: I877959ab5446e09648a52fd18fd4a219c3f01e7e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/255453
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

5 years agoARM: dma-mapping: Fix crash w/o IOMMU enabled
Hiroshi Doyu [Tue, 30 Jul 2013 08:41:44 +0000]
ARM: dma-mapping: Fix crash w/o IOMMU enabled

Allow kernel to boot w/o TEGREA_IOMMU_SMMU

Bug 1285960

Change-Id: I8a8adac713ca0e76ca410a1f8cd4345488aae774
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/255451
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: ardbeg: configure overcurrent of GPU/Core rails for AMS
Laxman Dewangan [Wed, 31 Jul 2013 05:56:03 +0000]
ARM: tegra: ardbeg: configure overcurrent of GPU/Core rails for AMS

bug 1329929

Change-Id: I1974815d55255fab0c96f5f2343ddbde4b69c14a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/254940
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoregulator: as3722: add support for overcurrent configuration
Laxman Dewangan [Mon, 29 Jul 2013 09:07:48 +0000]
regulator: as3722: add support for overcurrent configuration

Add support for overcurrent configuration on as3722 PMIC.

bug 1329929

Change-Id: I777fa3a6616da027e2d742d22f99739c921293b6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/254939
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: clock: add DC2 to iso usage table
Jihoon Bang [Wed, 10 Jul 2013 17:22:13 +0000]
ARM: tegra: clock: add DC2 to iso usage table

Consider DC1 and DC2 as separate iso client.
If DC1 and DC2 are on at the same time, use lower
iso efficiency as DC is on with other client.

Bug 1320063

Change-Id: Id2060339b50899a4507df0e6dee62648a3a9bd2f
Reviewed-on: http://git-master/r/247282
(cherry picked from commit e2fba905182737c73446f5d989b22cb5d886963a)
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/247251
(cherry picked from commit f6111cb1ab843c60a6265610d686deb6475b8f36)
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/254364
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: ardbeg: Corrected dsi_csi power rail sources
Mallikarjun Kasoju [Mon, 22 Jul 2013 15:34:46 +0000]
ARM: tegra: ardbeg: Corrected dsi_csi power rail sources

Bug 1325539

Change-Id: Ia7576485ba1b1041bf88fe1926600b8cc49cadea
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/253962
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: Control PLLP_OUT5 in gk20a driver
Kaz Fukuoka [Thu, 11 Jul 2013 18:33:23 +0000]
video: tegra: Control PLLP_OUT5 in gk20a driver

- In drivers/video/tegra/host/gk20a/gk20a.c,
PLLP_OUT5 is controlled as "pwr" clock.
(This part is already done by earlier changes.)

- Also in kernel/arch/arm/mach-tegra/common.c,
"pll_p_out5" is enabled in lower frequency.
This is necessary for gk20a.c driver to initialize registers,
before the "pwr" clock is enabled in gk20a.c

bug 1323688

Change-Id: Icb1c10562af3da5f60fe92a4a2b563d131df0c19
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/247978
(cherry picked from commit 50741c7f2011a4bf388836dff594266dce839960)
Reviewed-on: http://git-master/r/253661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo:tegra: fix cyclestats bugs
Kirill Artamonov [Wed, 10 Jul 2013 04:46:15 +0000]
video:tegra: fix cyclestats bugs

Free memory buffers allocated for cyclestats when channel is freed.
Fix format of callback buffers to match format used in userspace.
Fix names of callback operations.

bug 1154464
bug 1324403

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I0540275d180236b1bcc67013f542f359398ff907
Reviewed-on: http://git-master/r/252674
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>

5 years agoarm: configs: t124: add profiling configs
Donghan Ryu [Tue, 30 Jul 2013 11:35:53 +0000]
arm: configs: t124: add profiling configs

Enable PROFILING and OPROFILE

Bug 1325300

Change-Id: I35a8d791c5a1bfc9e52cd23d5d5c0d97398881be
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/255576
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: mc: Reduce code for debugfs node
Alex Waterman [Mon, 29 Jul 2013 20:49:30 +0000]
ARM: tegra: mc: Reduce code for debugfs node

Use the convenience macro for simple debugfs nodes instead of the long
complete definition for debugfs nodes.

Change-Id: I17ce8d53871a6dad88c24710cd9cf09259bed2bc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/255215
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agomedia: video: tegra: imx091: Auto detect support
Frank Chen [Thu, 20 Jun 2013 00:39:16 +0000]
media: video: tegra: imx091: Auto detect support

Read imx091 sensor ID during probe time. Sensor
ID will be used for sensor auto detection later.

Bug 1306878

Change-Id: I32da93266b6aa0c0ec2bffc7a5156c21083cb069
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/243657
(cherry picked from commit 854ff318b7ec483b81960b753440cf2cb7dc18ee)
Reviewed-on: http://git-master/r/254467
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: soctherm: fix handling cl-dvfs voltage range
Diwakar Tundlam [Sat, 27 Jul 2013 01:03:35 +0000]
ARM: tegra14: soctherm: fix handling cl-dvfs voltage range

Fixed check which was inverted. Also added check for possibility of
cpu-temp being lower than pll-temp, which causes unnaturally large
offset getting programmed resulting in spurious (huge) temperatures,
which will lead to sperious shutdowns.

Bug 1332999
Bug 1329597
Bug 832603

Change-Id: I3b720ae73e1816922f51c1431bcbca1760aa31d0
Reviewed-on: http://git-master/r/254639
(cherry picked from commit 290a2507b4247919776af8ffa76573dc37eb4e30)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/255205
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agodrivers: misc: therm_est: Fixed factory reset issue
Hyungwoo Yang [Wed, 10 Jul 2013 02:14:04 +0000]
drivers: misc: therm_est: Fixed factory reset issue

Thermal Estimator tries to access device no more usable during factory reset.

Bug 1320678

Change-Id: Ic56f550c029ad5b9d9a117ad79ccf5bd03292f86
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/246962
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit e06ae462d514f61f28d5fd7f82d927bbeb0c8607)
Reviewed-on: http://git-master/r/255172
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: thermal: change names of zone devices
Hyungwoo Yang [Mon, 13 May 2013 22:47:46 +0000]
ARM: tegra: thermal: change names of zone devices

Changed names of zone devices to be measuring device independent.

nct_ext -> Tdiode
nct_int -> Tboard

Bug 1261182

Change-Id: I11fda2288857142332c4c37c5505c23a95656480
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/247413
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit b178dcefa3c72d1927c390e3de4d8cd9d5aa8fee)
Reviewed-on: http://git-master/r/255159
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agomisc: nct1008: change names of zone devices
Hyungwoo Yang [Wed, 10 Jul 2013 21:19:36 +0000]
misc: nct1008: change names of zone devices

Changed names of zone devices this driver creates.
New names are based on where the device probe.

nct_ext -> Tdiode
nct_int -> Tboard

Bug 1261182

Change-Id: I147ae07992b3e0efa32671a47bb8c395faa24ff7
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/247344
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 74213e3e26148eb63c9f311a74206ba253e65ee6)
Reviewed-on: http://git-master/r/255157
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: dsi: Interleave dsi controllers ganged init
Animesh Kishore [Fri, 26 Jul 2013 14:21:51 +0000]
video: tegra: dsi: Interleave dsi controllers ganged init

With panels operating in ganged mode, initialization of both
DSI controllers happens one after the other sequentially.
Due to this some of panels are showing abnormal behaviour.

Enabling interleaved initialization of both dsi controllers.

Change-Id: I9de1f51fea4f7e930cad09e6258eb64b0514d4d7
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/254359
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra14: soctherm: handle cl-dvfs voltage range notification
Diwakar Tundlam [Tue, 2 Jul 2013 21:18:15 +0000]
ARM: tegra14: soctherm: handle cl-dvfs voltage range notification

Adjust soctherm cpu zone configuration when CL-DVFS is crossing
boundary between high/low voltage ranges.

Bug 832603

Change-Id: Ic1bfbd5506dee496dc2c7308ab550ac5c7770429
Reviewed-on: http://git-master/r/246327
(cherry picked from commit 59daa04571e595b7b6d6a089091b9735f26708f3)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253753
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: soctherm: fix heavy throttling on GPU zone
Diwakar Tundlam [Thu, 23 May 2013 21:57:46 +0000]
arm: tegra: soctherm: fix heavy throttling on GPU zone

Fixed initialization of GPU throttling config in board files

Bug 1169070

Change-Id: I43cc7edaa4adf5a3527ff16332b7755682fc5d74
Reviewed-on: http://git-master/r/239453
(cherry picked from commit 80605ae69b8f1f5a9a5b20e3a74384a18ab75f41)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253752
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: EDP: Allow enforcing max-freq caps based on tables
Diwakar Tundlam [Mon, 3 Jun 2013 21:40:06 +0000]
arm: tegra: EDP: Allow enforcing max-freq caps based on tables

In addition solving for max-freq using leakage/dynamic formula, some
platforms require capping based on EDP tables published in the spec.
Adding support for this.

Added T114 fixed-capping table entries.

Bug 1281159

Change-Id: Ia159281db0ca72e74002b526b3b9e6f54b271646
Reviewed-on: http://git-master/r/239512
(cherry picked from commit d2ad4ba3de666f3fd299a8b95b1685e2f6da0d21)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253751

5 years agoarm: tegra: soctherm: show temperature log in debug output
Diwakar Tundlam [Fri, 21 Jun 2013 20:02:31 +0000]
arm: tegra: soctherm: show temperature log in debug output

Added new debugfs node to show temperature log with one-line summary
of temperatures of various TSOSCs with time-stamp.

The TSOSCs temperatures order is CPU0, CPU1, CPU2, CPU3, GPU, PLLx.

Also temporarily resume soctherm if it was suspended for the duration
of the debugfs call. Useful for logging purposes.

Bug 1165644

Change-Id: I695b7f8ab15fe9f5dcd2bc38b26c87a1938b3efb
Reviewed-on: http://git-master/r/241145
(cherry picked from commit b538aa0a38894dad2fe83a9decbe3c4702471438)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253750
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: tegra: update edp parameters init for t11x
Diwakar Tundlam [Mon, 10 Jun 2013 23:09:43 +0000]
arm: tegra: update edp parameters init for t11x

Updated leakage and dynamic parameters to compute EDP table fro T114
based on latest characterization data.

Bug 1304350

Change-Id: I503e7942c0f5c8bd401df086037694cba0e52bf6
Reviewed-on: http://git-master/r/241601
(cherry picked from commit f46bdb0f8a0b89e21cf1929a6eae354180141019)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253749
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: Tegra: Floor the calculated CPU leakage current
Diwakar Tundlam [Wed, 6 Mar 2013 21:08:08 +0000]
ARM: Tegra: Floor the calculated CPU leakage current

Also handle leakage calculation failure as an error in EDP-init

Bug 1251570

Change-Id: Ia5f0495f3019c54d1c56701f289618b82a100e05
Reviewed-on: http://git-master/r/239861
(cherry picked from commit 5ed581841d235cb2d0154002f457da668012d32e)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253748

5 years agoarm: tegra: EDP: Config to enable fixed EDP freq caps
Diwakar Tundlam [Wed, 5 Jun 2013 22:12:51 +0000]
arm: tegra: EDP: Config to enable fixed EDP freq caps

Added the config option for T11x. Default is disabled.

Bug 1281159

Change-Id: I7477e121f23304ca4234390906101e1829cb2803
Reviewed-on: http://git-master/r/239513
(cherry picked from commit e1975755f51bb86fcdd947c8550c4c235e3a1913)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253747
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: refactor edp parameters init
Diwakar Tundlam [Sat, 8 Jun 2013 00:33:03 +0000]
arm: tegra: refactor edp parameters init

Move common numeric values to be macro-based to avoid duplicates

Bug 1304350

Change-Id: I470e135715a7226225b09213748783fc9dff70ae
Reviewed-on: http://git-master/r/239511
(cherry picked from commit 90326769802790cf2bac4ebdc8c6f307b0d1d1f5)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253746

5 years agoedp: tegra: table show support for T40DC
Diwakar Tundlam [Tue, 18 Jun 2013 00:38:42 +0000]
edp: tegra: table show support for T40DC

Bug 1300607

Change-Id: Iafaab450fd88a41b6384256ad2c6aaf2ebb9f360
Reviewed-on: http://git-master/r/239500
(cherry picked from commit fb715d4a3cb28547c274c648ecd43c87b33a1ec2)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253745
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: tegra: edp: table show support for T40DC
Diwakar Tundlam [Wed, 12 Jun 2013 23:52:31 +0000]
arm: tegra: edp: table show support for T40DC

Bug 1300607

Change-Id: I19a5381e3e68632f2f06deb7400a33419f320590
Reviewed-on: http://git-master/r/239497
(cherry picked from commit 4f484e2e0fdbdd5d1eeabdc4d39fa888dfd400d0)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253744

5 years agoarm: tegra: soctherm: Only error on improper FUSE_BASE
Diwakar Tundlam [Fri, 7 Jun 2013 23:22:17 +0000]
arm: tegra: soctherm: Only error on improper FUSE_BASE

FUSE_CALIB values can be zero and should not trigger init error.

Bug 1284859

Change-Id: I0a9b0dcaaf166adb2dba604e0ca5e430cfcecb1e
Reviewed-on: http://git-master/r/239457
(cherry picked from commit fc2ba2a5d235b67109eeae32aee9edf445c55dda)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253743
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Anand Bhatia <anandb@nvidia.com>

5 years agomisc: nct1008: specify polling delay in plat struct
Diwakar Tundlam [Mon, 15 Jul 2013 23:25:43 +0000]
misc: nct1008: specify polling delay in plat struct

Bug 1315460

Change-Id: I6fa760a01103f34d9f2bc9551025cbaadadf4eb2
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/250907
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoThermal: sys node to read and write polling_delay
Diwakar Tundlam [Mon, 15 Jul 2013 23:26:05 +0000]
Thermal: sys node to read and write polling_delay

Bug 1315460

Change-Id: I7dca29c63d5238522b1cd9df680dc7c019674066
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/250905
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>

5 years agoARM: tegra: pcie: fix Coverity issue
Deepak Nibade [Mon, 13 May 2013 10:34:17 +0000]
ARM: tegra: pcie: fix Coverity issue

fix Coverity issue of reading from pointer after free
Coverity id : 23084

Bug 1046331
Bug 1329327

Change-Id: I17916ad2c0cfee828c50fe148927513a262a7c43
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/227923
(cherry picked from commit ebba5239ddcea9f9d4c94a4eaf68a9ac2468206c)
Reviewed-on: http://git-master/r/255377
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agovideo: tegra: gk20a: Fix GPCPLL VCO max
Kaz Fukuoka [Sat, 27 Jul 2013 00:35:57 +0000]
video: tegra: gk20a: Fix GPCPLL VCO max

- Fix VCO max (old=1700MHz, new=2000MHz).
- Because of this bug, 984MHz caused error.

Change-Id: Iebb1c1cb2da212244ef051ee758bc3965e3ab3c9
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/254617
(cherry picked from commit 22ba27f9545ef78e82384972c50a2720c54d77c0)
Reviewed-on: http://git-master/r/255256
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: config: tegra12: Enable BCM43341 wifi driver
Nagarjuna Kristam [Mon, 29 Jul 2013 11:02:20 +0000]
arm: config: tegra12: Enable BCM43341 wifi driver

Bug 1310572

Change-Id: Ic099cec1b2ff810a5fa6fcdbd8e0789d41b823cd
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/254222
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: config: tegra12: Actually enable SMMU
Robert Morell [Mon, 29 Jul 2013 21:22:17 +0000]
arm: config: tegra12: Actually enable SMMU

Commit ca1c4ca6fc enabled CONFIG_PLATFORM_ENABLE_IOMMU, but not
CONFIG_TEGRA_IOMMU_SMMU.

Signed-off-by: Robert Morell <rmorell@nvidia.com>
Change-Id: Ib9b6db7fa7fb1917095afe743a8ac928f1d6fdc2
Reviewed-on: http://git-master/r/255273
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoiommu: tegra: fix incorrect iova used during tlb/ptc flush
Krishna Reddy [Mon, 29 Jul 2013 21:56:24 +0000]
iommu: tegra: fix incorrect iova used during tlb/ptc flush

Change-Id: I13ed5d9c426e1b421283e0261fe397f79034e808
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/255236
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoARM: tegra: thermal: Use exact_freq only if thermal_throttling is on
Diwakar Tundlam [Mon, 29 Jul 2013 20:10:54 +0000]
ARM: tegra: thermal: Use exact_freq only if thermal_throttling is on

EXACT_FREQ was forced ON in absence of THERMAL_THROTTLE prerequisite.
This breaks some kernel configurations such as MODS, which disable CPU
frequency scaling so TEGRA_THERMAL_THROTTLE is disabled. This is fixed.

Bug 1338672
Bug 1174096
Bug 1200111

Change-Id: I9571aa1295cd99a3ece75cbb823019e6352149b1
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/255200
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>

5 years agoARM: tegra: Fix throttle_count malfunction
Hyungwoo Yang [Wed, 3 Jul 2013 01:49:45 +0000]
ARM: tegra: Fix throttle_count malfunction

Bug 1288550

Change-Id: I4baba118331d579d1522a63b26ffeef3027cd28e
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/244600
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 659b49aff7238b1d5c859940c4fa2f753d809912)
Reviewed-on: http://git-master/r/255175
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: laguna: Fix voltage range for ldo6 rail
Johnny Qiu [Wed, 10 Jul 2013 00:55:27 +0000]
ARM: tegra: laguna: Fix voltage range for ldo6 rail

ldo6 power rail min voltage should be 1.8V

Bug 1323354

Reviewed-on: http://git-master/r/246936
(cherry picked from commit 77ae8456c00701f150aad727ae90ff7709b367c8)
Change-Id: I44a30e7f81feb2aafd0d37915aebf1b5d92ce0d4
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/254851
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Shanker S <shs@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra14: bb: use mem_req_soon for emc dvfs
Vinayak Pane [Tue, 16 Jul 2013 00:33:29 +0000]
arm: tegra14: bb: use mem_req_soon for emc dvfs

Use mem_req_soon signal instead of mem_req signal to
remove EMC clock request. This prevent EMC drops for
short BB hibernate periods.

Bug 1323192

Change-Id: I6dc2e6a4069e5fcbfad0481860b8a9a691e3c0ab
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/249419
(cherry picked from commit a23b66a54bc335e426cebf2441ec8382b5b50e06)
Reviewed-on: http://git-master/r/254496
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoarm: tegra14: bbc: update core suspend about EMC rate
Vinayak Pane [Thu, 6 Jun 2013 23:07:11 +0000]
arm: tegra14: bbc: update core suspend about EMC rate

Inform LP1BB entry part about the current BBC emc floor and
the corresponding voltage required. These EMC parameters can
be used by LP1 entry low power routine to set optimal values
before entering in LP1BB hw state. The EMC parameter should
also be used by lp1bb exit routine to set the required EMC
frequency and voltage to minimize suspend-resume latency.

Bug 1270116
Bug 1301005

Change-Id: I1a979ae92fd4d579cd5ecc293f5c40203b440e4d
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/238239
(cherry picked from commit 6b083a4101c7d30dd14b391b2381ed91b938306f)
Reviewed-on: http://git-master/r/254495
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra14: bbc: prepare for lp1bb state
Vinayak Pane [Fri, 24 May 2013 23:54:16 +0000]
arm: tegra14: bbc: prepare for lp1bb state

There is window when BBC driver may not be aware of upcoming
paging event. During LP1BB suspend the EMC rate is used whatever
the system was using before suspend. That EMC rate may not be well
suited for BBC to operate in LP1BB state. Changing the emc clock
rate to set at the maximum floor for BBC. The LP1BB entry part
should reduce it down to the actual frequency floor.

Also for RPC request during LP1BB this new minimum floor gives a
safeguard against the resume time to raise EMC frequency.

Bug 1294872

Change-Id: I3b98cfac174f9dac12307923a1ef54c2c9430bad
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/238238
(cherry picked from commit 36a3bffaf90209f1a6b607a2a3bf581e9731ae49)
Reviewed-on: http://git-master/r/254494
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoarm: tegra14: bb: abort suspend when IPC is pending
Vinayak Pane [Wed, 12 Jun 2013 00:06:19 +0000]
arm: tegra14: bb: abort suspend when IPC is pending

If BBC has asserted IPC interrupt then abort the system
suspend. This is to reduce the wakeup latency for BBC
requests.
Also, add function to check for pending BB IPC interrupt.

Bug 1304608

Change-Id: Ie3766ab82c9e7f359cc9866dcf7ee163ab1aabc6
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/237796
(cherry picked from commit 7d65d264cae1810faa3e8193125a0da61da8dfce)
Reviewed-on: http://git-master/r/254492
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agovideo: tegra: host: fix gk20a rail gate/ungate sequence
Mayuresh Kulkarni [Fri, 12 Jul 2013 16:53:55 +0000]
video: tegra: host: fix gk20a rail gate/ungate sequence

bug 1324512

Change-Id: I6d95c5ae454be6e5a3c377a23fc0283d576aa016
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/253397
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: host: Use dma_map_sg()
Terje Bergstrom [Thu, 25 Jul 2013 05:08:14 +0000]
video: tegra: host: Use dma_map_sg()

Use dma_map_sg_attrs() for mapping in nvhost_memmgr.c. Also remove
touching sg fields. This causes dma_address to be set to only the first
chunk, so gk20a memory management code was adjusted to deal with that.

Also sets maximum dma chunk size to biggest possible number.

Bug 1325300

Change-Id: Icf76e01d6cc5464d98e5907cdefc40cc7ae59d14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/253308
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: host: Reimplement nvmap_pin in nvhost
Terje Bergstrom [Thu, 4 Apr 2013 12:31:50 +0000]
video: tegra: host: Reimplement nvmap_pin in nvhost

Reimplement mapping buffer to device memory in nvhost. This allows
separating memory areas of devices from each other.

Adds also dma parameters for each host1x device.

Bug 1259839
Bug 1174439

Change-Id: I0029756d84c455faacbbe27791e0e8f1190352ee
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/251931
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agodrivers: tegra: gk20a: Add debugfs node for load
Prashant Malani [Tue, 9 Jul 2013 00:30:54 +0000]
drivers: tegra: gk20a: Add debugfs node for load

Add a debugfs node to provide load measurements
for gk20a.
This uses counters in the PMU to measure the busy
and total cycles, and calculates load using this.

Bug 1320968

Change-Id: Id66d9002b49ec787d8dc957d19826a3433415bd0
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/250476
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: move cpu-based timers out of timer.c
Peng Du [Tue, 16 Jul 2013 03:40:52 +0000]
ARM: tegra: move cpu-based timers out of timer.c

This change cleans up timer.c by pulling out cpu-based timers
(ie. arch & twd) into their own files. timer.c now hosts code
only for the Tegra SOC timers and common init code.

Also relocated deep power down (DPD) code from timer.c to pm.c
so that it can be shared by other chip family.

Change-Id: I247e514270e5a81a5eb1bde6d7f75692cbede1f0
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/250353
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>

5 years agoarch: config: tegra enable support to debug clocks in mods config
Vivek Aseeja [Mon, 29 Jul 2013 18:04:56 +0000]
arch: config: tegra enable support to debug clocks in mods config

enable CONFIG_TEGRA_CLOCK_DEBUG_MODS support in mods defconfig

Change-Id: I781c090056075bb31732b033c96ecbe6d0ab13b9
Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-on: http://git-master/r/255152
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/3 lock timeout message
Kaz Fukuoka [Fri, 26 Jul 2013 00:27:16 +0000]
ARM: tegra12: clock: Update PLLC2/3 lock timeout message

Since PLLC2/3 lock bits may fluctuate after the lock with no adverse
functional effect, report timeout as debug (not error) print. At the
same time expand information in the message for detailed debugging.

bug 1325603
Ported from http://git-master/r/223688 (change for Tegra14)

Change-Id: I9147692e3773a56cd59c797301c7c66f911e396b
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/253878
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: Change resistor value based on reworked/nonreowrked
Rohit Vijayaraghavan [Thu, 25 Jul 2013 22:45:11 +0000]
ARM: tegra12: Change resistor value based on reworked/nonreowrked

Identify whether a reworked board or not. Then set the respective
resistors accordingly and proceed.

Bug 1325536

Signed-off-by: Rohit Vijayaraghavan <rohitv@nvidia.com>
Change-Id: I243c2e78db01b0f78c49f3053d1e89c260f4e57b
Reviewed-on: http://git-master/r/253772
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>

5 years agotlk_driver: use dma_alloc_coherent for uncached mem
Chris Johnson [Tue, 23 Jul 2013 18:20:34 +0000]
tlk_driver: use dma_alloc_coherent for uncached mem

Instead of relying on change page attribute calls, instead use DMA
routines to get uncached mem. This will go away in the near future
when we can map these buffers directly in the kernel.

Change-Id: I6a375f2b1b09f987deae8a61e0907209b90c870e
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/252523
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aaron Gamble <jgamble@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>

5 years agosecurity: tlk_driver: return failure for IOCTL_FILE_NEW_REQ during suspend
Varun Wadekar [Tue, 2 Jul 2013 07:26:15 +0000]
security: tlk_driver: return failure for IOCTL_FILE_NEW_REQ during suspend

The user space daemon will retry 3 times whenever it receives errors for new
requests.

Bug 1314244

Change-Id: I57f1740d7b24d2f3f3f97e7e83a5434f54d05bdb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/244187
(cherry picked from commit 639efa238a01be8fd9debf4c8511c9eac942fc46)
Reviewed-on: http://git-master/r/249874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>

5 years agosecurity: tlk_driver: use local stack for context save/restore
Varun Wadekar [Tue, 25 Jun 2013 05:42:35 +0000]
security: tlk_driver: use local stack for context save/restore

With secure storage there is a situation when we getback from the SMC call,
but find that the stack is completely corrupted due to SVC handling in the
kernel. To avoid such scenarios, use a local stack to save/restore our context.

Bug 1291402

Change-Id: If7d4c336aa0cc664b7c7f7134becb68d03e22ece
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/241681
(cherry picked from commit 4fb8a5f59ce565cb684d9aaa816a465d7c3a5d04)
Reviewed-on: http://git-master/r/249872
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>

5 years agotlk: New API changes for tlk
James Zhao [Fri, 7 Jun 2013 22:51:20 +0000]
tlk: New API changes for tlk

- add new parameter passing support for variable number of parameter
- some clean up of naming conventions

Bug 1310292

Change-Id: Ie9669456682fe2b85eb79a3d9cb4cbac9eba8d54
Signed-off-by: James Zhao <jamesz@nvidia.com>
Reviewed-on: http://git-master/r/239104
(cherry picked from commit da4ee985be76b4f02284510d2eb7e851fb50bc0b)
Reviewed-on: http://git-master/r/249870
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>

5 years agosecurity: nv_tee_driver: handle "daemon not present" scenario
Varun Wadekar [Wed, 12 Jun 2013 05:53:54 +0000]
security: nv_tee_driver: handle "daemon not present" scenario

During each request from the daemon, set a bit in a global variable
indicating that the daemon is alive and kicking. For each request from
secure world, check this bit to see if the daemon is present, and send
error if not present.

Bug 1291402

Change-Id: Ie8c59a465451b1781b4f379c0b6f661b05a417da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/237850
(cherry picked from commit 205baa9bb3f4d2ba150253284ac7af9733938a01)
Reviewed-on: http://git-master/r/249869
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aaron Gamble <jgamble@nvidia.com>

5 years agosecurity: nv_tee_driver: make wait_for_completion calls freezable
Varun Wadekar [Tue, 11 Jun 2013 10:03:20 +0000]
security: nv_tee_driver: make wait_for_completion calls freezable

Bug 1305672

Change-Id: I21efcac292bfc2001087614437a4fee68fe5db69
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/237571
(cherry picked from commit 3d8d572a2aabe7d6943cd39ce42d82394c87ff5a)
Reviewed-on: http://git-master/r/249868
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aaron Gamble <jgamble@nvidia.com>
Reviewed-by: James Zhao <jamesz@nvidia.com>
Tested-by: James Zhao <jamesz@nvidia.com>

5 years agovideo: tegra: gk20a: add sysfs nodes.
Kevin Huang [Thu, 25 Jul 2013 18:19:01 +0000]
video: tegra: gk20a: add sysfs nodes.

Create gk20a sysfs nodes to toggle status of elcg, blcg and slcg.

Bug 1327269

Change-Id: I6c206e8ff7f8620ca960b9d7c617857cf42c36db
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/253574
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: config: tegra[3/11]: Turn off PCI VGA arbitration
Preetham Chandru R [Tue, 23 Jul 2013 11:34:57 +0000]
arm: config: tegra[3/11]: Turn off PCI VGA arbitration

Not used in tegra. With it, the driver continously
spews on console.

Bug 930042

Change-Id: If86b57b4349d23e5757ca5c8431eed0f3e431bce
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/252388
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomfd: as3722: cache only regulator register
Laxman Dewangan [Mon, 29 Jul 2013 12:22:14 +0000]
mfd: as3722: cache only regulator register

Caching the regulator register rather than saying all registers
are non-volatile.

Change-Id: I5fd9673f38da47c40aa0f03594dcec97e8d063b1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/255040
Reviewed-by: Automatic_Commit_Validation_User

5 years agoasoc: tegra: fix Coverity issues of NULL dereference
Deepak Nibade [Mon, 29 Jul 2013 10:00:16 +0000]
asoc: tegra: fix Coverity issues of NULL dereference

- fix dereference after null check
  Coverity id : 23554
  Coverity id : 23555
- fix dereference of null return value
  Coverity id : 23338
- fix dereference before null check
  Coverity id : 23683
  Coverity id : 23684

Bug 1329327

Change-Id: I65542ff9da32810676c5b28fed463cf43c7807df
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/254991
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

5 years agoARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2
Bharat Nihalani [Tue, 23 Jul 2013 12:40:27 +0000]
ARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2

This change is done for all boards.

Change-Id: I4db494717a62fd9df366088a04245f007d4cf5b2
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/252410
(cherry picked from commit 78a94c5b80e390d63e4e240be62cb0bff1fc4cfa)
Reviewed-on: http://git-master/r/254248
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: enable vic power-gating
Mayuresh Kulkarni [Wed, 24 Jul 2013 11:35:19 +0000]
video: tegra: host: enable vic power-gating

bug 1324512

Change-Id: Ibb9ff1f0b60e84752eef55cd0a1899822e65c6fb
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/253401
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: gk20a: enable ELCG with higher idle time.
Kevin Huang [Tue, 23 Jul 2013 21:39:52 +0000]
video: tegra: gk20a: enable ELCG with higher idle time.

Bug 1327269

Change-Id: I65d5e80462625cf96a9cfc05e50209f22866a2ee
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/252593
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>

5 years agoTegra12: ARM: Clocks: Update gpu clocks and voltage
Krishna Sitaraman [Fri, 19 Jul 2013 19:23:45 +0000]
Tegra12: ARM: Clocks:  Update gpu clocks and voltage

Increase gpu clock to 350Mhz and set vdd_gpu to 0.9V.

Change-Id: Id6adb4fa8790beab5971f7ec9467de130d625b9f
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/251437
(cherry picked from commit 3d16e8b0611e328ac50eebf50981a71c45b78248)
Reviewed-on: http://git-master/r/254240
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: disable one shot mode for sharp 25x16
Mitch Luban [Mon, 22 Jul 2013 22:27:47 +0000]
arm: tegra: disable one shot mode for sharp 25x16

Bug 1334200

Change-Id: I08d85831dc8255e04f67393b50432ce8790ac59d
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/254472
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: dsi: Fix pad disable during suspend
Animesh Kishore [Fri, 26 Jul 2013 07:45:20 +0000]
video: tegra: dsi: Fix pad disable during suspend

Replace direct register writes with correct api.

Change-Id: I0b5365083bfad410cdfba5624e683a6cc3c1210f
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/254071
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agomedia: video: tegra: ov2710: remove unused code
Deepak Nibade [Fri, 26 Jul 2013 06:37:21 +0000]
media: video: tegra: ov2710: remove unused code

- fix Coverity issue
  Coverity id : 23456

Bug 1329327

Change-Id: I7ad994db88726151b1f29139b6924d04472bbffa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/254037
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm: tegra: ardbeg: Disable always on and boot on for avdd_dsi_csi
Animesh Kishore [Fri, 19 Jul 2013 10:56:51 +0000]
arm: tegra: ardbeg: Disable always on and boot on for avdd_dsi_csi

Bug 1325539

Change-Id: I0544443417e5e9f6639753d051bcf7f2b61fd89b
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/251317
(cherry picked from commit 82b947a4768514534ae173799152a5f2014e8412)
Reviewed-on: http://git-master/r/253961
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: ardbeg: Add os idle aggressiveness for sharp 25x16
Animesh Kishore [Fri, 19 Jul 2013 10:59:04 +0000]
arm: tegra: ardbeg: Add os idle aggressiveness for sharp 25x16

Bug 1325539

Change-Id: I4defe4689253f7c16f6e59ab37e678cda1002489
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/251318
(cherry picked from commit 996a4bace62b01e3af3ac5c429673abd2301e3ce)
Reviewed-on: http://git-master/r/253960
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: dsi: Implement ganged mode os idle
Animesh Kishore [Fri, 19 Jul 2013 11:00:11 +0000]
video: tegra: dsi: Implement ganged mode os idle

- Add code for OS idle power save in ganged mode
- Turn off various pad and controller HW logic in os idle

Bug 1325539

Change-Id: I38104bd57aabd0b670c6dd8b84df43062e5cdd93
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/251319
(cherry picked from commit e557919293e17879438eaab2cb6c289ee2f1a17b)
Reviewed-on: http://git-master/r/253959
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: dc: Add clockgating to eDP and LVDS
Chao Xu [Thu, 25 Jul 2013 23:45:54 +0000]
video: tegra: dc: Add clockgating to eDP and LVDS

Change-Id: I4ed2c655b67cdde7d7fdec1fc61adc58c2684307
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/253845
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: clock: Add CONFIG_TEGRA_CLOCK_DEBUG_MODS
Kaz Fukuoka [Mon, 22 Jul 2013 23:25:44 +0000]
ARM: tegra: clock: Add CONFIG_TEGRA_CLOCK_DEBUG_MODS

Add a function for clock debug and verification.
- Add CONFIG_TEGRA_CLOCK_DEBUG_MODS
- Add tegra_clk_set_max()

Change-Id: I4cc66c7ec83f08afc4275de4bb5dcdd64c7c8f25
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/253726
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra: clock: Update max dvfs rate
Alex Frid [Fri, 19 Jul 2013 20:48:01 +0000]
ARM: tegra: clock: Update max dvfs rate

When changing clock maximum rate via debugfs interface, update top
dvfs entry accordingly.

Change-Id: I6b7d05ad86ab3a08840cf6ac309a5f4cffa5fc78
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253725
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: Tegra: Re-register warning on temperature_overheat change
Diwakar Tundlam [Wed, 17 Jul 2013 22:05:48 +0000]
ARM: Tegra: Re-register warning on temperature_overheat change

Modified overheat warning message to be clearer. Use a non-modifiable
thermal trip point to handle the warning. This is bound to a cooling
device that is automatically registered.

Bug 1321177

Change-Id: I976d1bf6116b7ece3b67a7cb4efba142ef57d07d
Reviewed-on: http://git-master/r/251511
(cherry picked from commit 18ff4844f0242b5ca83ed0690bde752f67afb2c4)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253713
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: gk20a: Add gk20a_clk_set/get_cap
Kaz Fukuoka [Wed, 17 Jul 2013 22:59:27 +0000]
video: tegra: gk20a: Add gk20a_clk_set/get_cap

Change-Id: I5fd7d9bf167e4c46c3d66bfa26ecfb3e200703bb
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/253694
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Fix SOR0 clock divider
Kaz Fukuoka [Wed, 17 Jul 2013 00:01:01 +0000]
ARM: tegra12: clock: Fix SOR0 clock divider

Change-Id: Ib7e3a3859877449b27f0ab51e6cb74966f231f07
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/249982
(cherry picked from commit 14492a2b718da28f02e80c6f4f5694bffeb540ab)
Reviewed-on: http://git-master/r/253662
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoconfig: tegra12: Enable SMMU
Mursalin Akon [Thu, 25 Jul 2013 17:54:22 +0000]
config: tegra12: Enable SMMU

Change-Id: I191faf2b797880a069f8e4075398832a378c7d95
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/253556
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: host: enable force context restore for vic
Mayuresh Kulkarni [Tue, 23 Jul 2013 10:49:06 +0000]
video: tegra: host: enable force context restore for vic

bug 1324512

Change-Id: I401325529ed330519a07efc972e20e216e57d350
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/253400
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: add a flag to force restore gather
Mayuresh Kulkarni [Tue, 23 Jul 2013 10:41:32 +0000]
video: tegra: host: add a flag to force restore gather

- add a flag which when set will force the restore gather
to each submit
- this is needed for some clients like VIC who lose the
information in this gather buffer on power-gating

bug 1324512

Change-Id: I22e8403a4d214d0f57e4dd555ce201580e5a5078
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/253399
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: host: change vic03 init strategy
Mayuresh Kulkarni [Wed, 24 Jul 2013 10:53:36 +0000]
video: tegra: host: change vic03 init strategy

- always call vic03_boot from nvhost_vic03_init.
- this is to ensure that we load a new instance of firmware in it.
- if suppose, before call to nvhost_vic03_deinit, it gets power-gated then
runtime pm call-back will restore it
- if user space closes the channel before it is power-gated,
it gets ready for next channel open
- add a flag to indicate that vic is booted and do not attempt
to reboot it
- fix misc issues (related to pin/unpin and cleanup)

Change-Id: I2d40aec16f21cf3c556988373de7e374663f4d0b
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/253398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: config: Enable SMMU
Terje Bergstrom [Thu, 25 Jul 2013 08:38:34 +0000]
ARM: config: Enable SMMU

Change-Id: Iee255c91de963540fd86c67bbf0a16ee93dce12d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/253309
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: nvmap: use dmabuf fd to share handles
Krishna Reddy [Wed, 3 Jul 2013 23:55:18 +0000]
video: tegra: nvmap: use dmabuf fd to share handles

fix incorrect error handling in nvmap_share_dmabuf.
remove unnecessary dependency on DMA_SHARED_BUFFER.
cleanup nvmap dmabuf implementation.

Change-Id: If427fb8c29116b797e7e998e1c68ff0081acc559
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/244907
(cherry picked from commit ebda92705d3f7925e9edfbda7b715f33d2d93fcf)
Reviewed-on: http://git-master/r/251670
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: add Tj throttling table with PID governor
Diwakar Tundlam [Fri, 19 Jul 2013 01:01:19 +0000]
arm: tegra: add Tj throttling table with PID governor

Using previous values used in T114. Set Tj throttling to 83C.
Also fixed vdd rail init for NCT on devices with AMS PMU.

Bug 1315460

Change-Id: Ib3e32eb0be6ba267e179b9154e6f038396440e16
Reviewed-on: http://git-master/r/251513
(cherry picked from commit de27d03213145a65fd40fc21a3508ef3ab625f90)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/251106
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agomedia: video: tegra: imx132: edp support
Charlie Huang [Wed, 5 Jun 2013 19:34:46 +0000]
media: video: tegra: imx132: edp support

support edp client on imx132.

bug 1299149

Change-Id: Iafa7bd1e749b73311a98e15ebba788d83951523a
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/239822
(cherry picked from commit ace7e87d0db411479266492caf303f9057d29579)
Reviewed-on: http://git-master/r/250886
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wei Chen (Camera) <wechen@nvidia.com>
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra14: clock: Fix encoder module EMC clock mode
Mahesh Lagadapati [Fri, 21 Jun 2013 18:53:52 +0000]
ARM: tegra14: clock: Fix encoder module EMC clock mode

Encoder module EMC clock mode is not set as shared bandwidth client.
Hence changing its mode to make it shared bandwidth client.

Bug 1298224

Change-Id: I7d4566e7e795b9c346fff009b28335baae7c72fa
Signed-off-by: Mahesh Lagadapati <mlagadapati@nvidia.com>
Reviewed-on: http://git-master/r/241994
(cherry picked from commit eb8740c9172b7bb1788daa29d87156659579a653)

Signed-off-by: Mahesh Lagadapati <mlagadapati@nvidia.com>
Change-Id: I8bdb756caefb95248c869d514fe835e476733027
Reviewed-on: http://git-master/r/248473
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: nvmap: Remove 32-bit param query
Terje Bergstrom [Tue, 23 Jul 2013 12:05:08 +0000]
video: tegra: nvmap: Remove 32-bit param query

Remove nvmap_handle_get_param_u32() now that it's not used anymore.

Bug 1174439

Change-Id: Ie91545ad6e9533ad1fe798514d282419f94d8a98
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/253304
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: host: Use 64-bit safe param query
Terje Bergstrom [Tue, 23 Jul 2013 12:04:26 +0000]
video: tegra: host: Use 64-bit safe param query

Use the 64-bit safe nvmap_handle_get_param().

Bug 1174439

Change-Id: I76bf7b17d5239f0c20053d163ae00bd82838955e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/253303
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: nvmap: Introduce 64-bit safe param query
Terje Bergstrom [Tue, 23 Jul 2013 12:03:29 +0000]
video: tegra: nvmap: Introduce 64-bit safe param query

Introduce a 64-bit safe variant of nvmap_handle_get_param_u32().

Bug 1174439

Change-Id: Ia88d8dea830a2fcb9f8d1e51c8912c2a856c60d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/253302
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: remove MCLK gate from vi driver
David Schalig [Thu, 25 Jul 2013 03:55:14 +0000]
video: tegra: remove MCLK gate from vi driver

Sensor clock gate is now controlled by 'mclk'/'mclk2' virtual
clocks, which enable/disable MCLK and its gate together.
mclk/mclk2 handles are managed by the camera sensor drivers.

Bug 1298672
Bug 1306878

Change-Id: I2c6c42c3fd8c34e1d9de9d2a85cf1f309b11c084
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/253177
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Add virtual mclk for camera
David Schalig [Thu, 25 Jul 2013 03:21:24 +0000]
ARM: tegra: Add virtual mclk for camera

Add virtual clocks 'mclk' and 'mclk2' to control sensor mclk and
and its clock gate at the same time. This enables drivers to control
MCLK with only one clk handle instead of two.

mclk: controls vi_sensor + csus gate (on T20, T30, T114, T148, T124)
mclk2: controls vi_sensor2 + vim2_clk gate (on T148, T124 only)

Also remove obsolete source files.

Bug 1298672

Change-Id: I0ff210f22d2e6f023de852a169045bb2f66942e0
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/253173
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>