6 years agoarm: tegra: usb_phy: add support for t114 usb_phy
Suresh Mangipudi [Mon, 4 Jun 2012 14:22:46 +0000]
arm: tegra: usb_phy: add support for t114 usb_phy

Supoorted added for t114 usb_phy driver.

Change-Id: Ib3ab79a86f1092a3073dc80e3d426105391518e7
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/106211
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: Rcf6d31ebbfef94f24d5b754d5525b9b8c4fca27b

6 years agoARM: tegra: clock: Initialize wake.sclk to 250 MHz
Alex Van Brunt [Thu, 31 May 2012 21:39:17 +0000]
ARM: tegra: clock: Initialize wake.sclk to 250 MHz

The JTAG probe must drive TCLK at less than 1/6th of sclk for JTAG
to function. The JTAG probe is not able to go slower than 4 kHz in
the real world. By setting sclk to 250 MHz in design time, it runs
faster than the required 24 kHz in the real world.

Bug 983408

Change-Id: Ifd3b4d454dbe2e96222290059580947ce93ade41
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/104233
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra412dd39d9dfc83062a2b931f56efbb6c904d003

6 years agoARM: tegra11: Update cache flush/invalidate for power gating
Bo Yan [Sat, 19 May 2012 02:38:05 +0000]
ARM: tegra11: Update cache flush/invalidate for power gating

The field ENABLE_EXT in CSR register controls what power partition
to be gated. If it's CPU-partition power gating only, there is no
need to flush or invalidate L2 cache before/after power gating.
With this change, L2 cache is flushed/invalidated only when the
non-CPU partition is to be power gated or when rail gating is
selected.

Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R3108cb94a1efc64574ff58067e239bd8539e6059

6 years agoARM: tegra: Disable CPU interface in power gating
Bo Yan [Tue, 29 May 2012 23:18:37 +0000]
ARM: tegra: Disable CPU interface in power gating

CPU interface needs to be disabled to avoid race condition. Simply
disabling legacy pass-through is not enough.

Change-Id: I4202d870036b137bdfd3b1d32a5781e2ef65ead9
Reviewed-on: http://git-master/r/105235
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rfccde91150c20d801e9e016039b2e64c8a2fabaf

6 years agoARM: tegra11: Select partitions for power gating
Bo Yan [Sat, 19 May 2012 02:47:34 +0000]
ARM: tegra11: Select partitions for power gating

Select power gating partitions based on flag. With this change,
Rail-gating is used as the default power gating option for CPU0
on cluster 0, non-CPU gating is the default power gating option
for CPU0 on cluster 1.

Also fixed  power gating flags by using control macros instead of
CSR field macros.

Change-Id: I971a34cc01f0216314f4bdbafc9aa070ca0dd708
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103477
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

Rebase-Id: R90ff171fb99007996ac159955095bed568960000

6 years agoARM: tegra: t114: new sub driver changes
Krishna Yarlagadda [Mon, 28 May 2012 17:58:49 +0000]
ARM: tegra: t114: new sub driver changes

modify board file to support new usb design

Change-Id: I496a665d3ccd5a46e55a88385bc9c94c4239d318
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/104989
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R1538617630f28732b0c0b16af1e1286556b56351

6 years agoARM: tegra11: clock: Remove host1x from cbus
Alex Frid [Thu, 24 May 2012 04:18:13 +0000]
ARM: tegra11: clock: Remove host1x from cbus

According to tegra11 clock policy moved host1x clock from cbus with
scaled PLLC source to fixed PLLP clock source. This allows completely
shut-off PLLC in use-cases when all graphics clocks are disabled, and
host1x is used only by display.

Change-Id: I100b9f4a9978deea1401a004eb855c5fc5ce8dcd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104320
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rd7cac155f5056912709b323a0a0d3ade86d74d48

6 years agoARM: tegar11: clock: Support cbus users auto-migration
Alex Frid [Tue, 22 May 2012 01:26:11 +0000]
ARM: tegar11: clock: Support cbus users auto-migration

Automatically move graphics clocks between 2 buses (with PLLC2 and
PLLC3 as respective clock sources), so that at any moment the user
requesting the highest rate among all enabled cbus modules has the
slowest dvfs table on the bus it is attached to.

Configuration option for auto-migration is disabled by default.

Bug 965702

Change-Id: I837ed6de163303bc4998bdcf4c7c4a4706b1ee6c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104297
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rf647e1d746b95b316beaff8aa04f6267a74e04f3

6 years agoARM: tegra11: Fake clk-m rate as 13M in Quickturn
Bo Yan [Wed, 23 May 2012 01:10:22 +0000]
ARM: tegra11: Fake clk-m rate as 13M in Quickturn

In Quickturn environment, the detected clock rate can be 115200
or 230400. In this case, we need to fake clock rate as 13M.

Change-Id: I926bc932a002c17c463a62bebce2554194c716cd
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/104029
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rde09a61ede880cad10a3038dde9a01892c1aa430

6 years agoARM: tegra: curacao: Enable SDMMC3
Pradeep Kumar [Thu, 24 May 2012 10:53:39 +0000]
ARM: tegra: curacao: Enable SDMMC3

Enable SDMMC3 for SD 3.0 Card testing.

Bug 953433
Bug 837138

Change-Id: I38ba198c7b2e9eb1e1fd5b303b4ec371e7b2df68
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/97505
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R1d7d45b9865c28fb0939bc42f77a58b8c2dbc266

6 years agoARM: tegra: Add descriptions of the new cbus configuration options.
Alex Frid [Wed, 23 May 2012 21:51:34 +0000]
ARM: tegra: Add descriptions of the new cbus configuration options.

Change-Id: Ib61e05553755b2cab09a74f02f1f99a0a206b62a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104255
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Racffa0ede0359a3ec356296d23229653e56496d1

6 years agoARM: tegra11: clock: Add support for dual cbus
Alex Frid [Wed, 16 May 2012 03:11:02 +0000]
ARM: tegra11: clock: Add support for dual cbus

Added support for 2 buses with graphics modules sourced from PLLC2,
and PLLC3. Default bus population: 3D and 2D modules are on PLLC2,
and all others (EPP, MSENC, VDE, TSEC, SE, Host1x) are on PLLC3.

Configuration option for dual cbus is not selected, yet. Hence,
current build configuration still run all graphics modules on PLLC.

Change-Id: I2ecbf098cb6d0f305e27c3583637b8c6e1719e46
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/103715
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R536402230130c95c5dd671ecbf9987d4899d83e7

6 years agoARM: tegra11: clock: Add shared user set parent operation
Alex Frid [Thu, 17 May 2012 03:05:14 +0000]
ARM: tegra11: clock: Add shared user set parent operation

Expanded shared user operations with set parent support. Since shared
bus and its children/users have reversed rate relations - user rates
determine bus rate - switching user from one parent/bus to another may
change rates of both parents. Therefore, we need a cross-bus lock on
top of individual user and bus locks. For now limit bus switch support
to cansleep users with cross-bus mutex only.

None of current shared users can utilize this expansion.

Change-Id: Ie01a9cf6d49cece3b498809ff3467fc43714ec34
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/103714
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb90d79a3930be5814544181dd5ab089cf7bafc82

6 years agoARM: tegra: Clean up flow controller CSR macros
Bo Yan [Sat, 19 May 2012 02:55:18 +0000]
ARM: tegra: Clean up flow controller CSR macros

Group flow controller macros for CSR register in one place in sleep.h
Also strip "CPU" out of macro names because the corresponding COP CSR
register has only one field INTR_FLAG which is at bit 15, same as CPU
CSR, so there is no confusion here.

Change-Id: Ib3dea0bd3e9051d1e7b9048abc4afde5ddc8bab5
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103478
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>

Rebase-Id: R63c198f17e573818b8d44482c46cb61516bf1267

6 years agoARM: tegra: Fix argument name for GIC function
Bo Yan [Mon, 21 May 2012 23:43:15 +0000]
ARM: tegra: Fix argument name for GIC function

The argument "pass_through" of function tegra_gic_cpu_disable is
confusing. If it's true, it actually means "to disable" pass-through.
Change it to "disable_pass_through" to reflect what it really is.

Change-Id: I4a08b8965641af913ebb626c81cdac3382a995a0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103729
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rd2af746d5742fb03fd094eaf4678bf078add0ba3

6 years agoARM: tegra: Define accessor for gic version
Bo Yan [Mon, 21 May 2012 23:24:12 +0000]
ARM: tegra: Define accessor for gic version

Accessor function is defined to return GIC version in system. Since
the returned value is u32, read out the GIC version number directly
from GIC ICPIDR2 register instead of forcing it to 2 as implied in
CortexA15 implementation or 1 in CortexA9.

Change-Id: Ib7a948656faf9552aef1bb3effa28f827c17d0f1
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103728
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R7bb73e0a0c8da81a747730b7d584eaf99bf16631

6 years agoARM: tegra: Add control for power gating mode
Bo Yan [Wed, 16 May 2012 19:46:48 +0000]
ARM: tegra: Add control for power gating mode

Add a module parameter to control what power gating mode to use
for LP2. There are 4 options: non-cpu power gating, rail gating,
CPU only power gating, or emulation mode.

Change-Id: I1529b28f7b478df980aa4e8ac2557b6ffdfe8e73
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/102880
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

Rebase-Id: Rce6345b9c876ebead0699b3d1f87270ab41779b1

6 years agoARM: tegra: power: Flush L1 to hot unplug CPU
Bo Yan [Wed, 16 May 2012 19:59:22 +0000]
ARM: tegra: power: Flush L1 to hot unplug CPU

This will ensure only L1 is flushed when hot unplugging non-boot
CPUs for CortexA15

Change-Id: Id78f801e5501d34dd43618179440adcf47666739
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/102881
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R37219dc63b66ffaee6bc866e403d1da509464142

6 years agoARM: tegra11: clock: Adjust cbus dvfs table dynamically
Alex Frid [Thu, 10 May 2012 05:36:31 +0000]
ARM: tegra11: clock: Adjust cbus dvfs table dynamically

Dynamically adjusted cumulative cbus dvfs table instead of using
static table that specifies worst case voltage requirements for
all cbus clients. Table adjustment takes into account only clients
enabled when cbus rate is updated, and ignores disabled clients.
Adjustment algorithm selects the dvfs table of the slowest enabled
client as new cumulative cbus dvfs table.

Changing dvfs table in flight makes cbus clock unique from voltage
control prospective: voltage requirements may change even when rate
is not changing; moreover voltage may go down while rate is going up
and vice versa. Hence, separated cbus update from common shared bus
rate control.

Bug 965692

Change-Id: I662fd08ab0481200221c7786edfa5249df567d54
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102716
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R7af46bab4520754b0802a6128a2db2f71930f0cd

6 years agoARM: tegra: curacao_sim: Enable NVAVP
Jeff Smith [Wed, 9 May 2012 16:19:50 +0000]
ARM: tegra: curacao_sim: Enable NVAVP

Disable mediaserver

Change-Id: Idb3556b55294db5a266cb9e1ff471dba69443c48
Reviewed-on: http://git-master/r/102113
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rffcfecb34165e108638ec4b525bdf2dd9abac61e

6 years agoARM: defconfig: curacao: update the defconfig to that of android
Preetham Chandru [Tue, 15 May 2012 11:57:51 +0000]
ARM: defconfig: curacao: update the defconfig to that of android

update the defconfig to that of tegra_curacao_android_defconfig. The configs
enabled are
1. MAX77663 MFD and Regulator
2. GPIO Regulator
3. NVAVP
4. I2C
5. USB_TEGRA
6. Ethernet
7. NETFILTER_XT_MATCH_OWNER
8. SMP

Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Tested-by: Chetan Hooli <chooli@nvidia.co>
Bug 944760
Change-Id: I0be287b4f41eee242b5df9885d5cf4a6c1c718ae
Reviewed-on: http://git-master/r/102587
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R2ba4df702e5429b37da2c543069535b15a01f647

6 years agomfd: max77663: register driver only if device is present
Pradeep Kumar [Thu, 17 May 2012 04:25:31 +0000]
mfd: max77663: register driver only if device is present

Performing a dummy read to chip_id register return error
from probe of this dummy read fails.

Bug 984138

Change-Id: Ib1ec804765ab00b6e2ea7e42c30e96722343c55e
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/103013
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R9a1e86a417e95cfbc2adb914459b1b4713b376bd

6 years agoARM: tegra: implement L1 cache flush function
Bo Yan [Tue, 15 May 2012 22:27:39 +0000]
ARM: tegra: implement L1 cache flush function

The function flush_cache_all flushes all caches within level of
coherency. For CortexA9, this is ok since only L1 is defined. For
CortexA15, it will flush both L1 and L2, this behavior is not
desired when there is no need to touch L2. So a new function is
defined to just flush L1 cache.

Change-Id: Id5a651770b70496d0dde6e90b226a19df90a57d0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/102682
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R06daabe836a97de0f4cace26235bf06ffbd49501

6 years agoARM: tegra11: clock: Don't backup detached cbus clocks
Alex Frid [Thu, 10 May 2012 03:29:05 +0000]
ARM: tegra11: clock: Don't backup detached cbus clocks

Check if cbus clock is attached to cbus parent pll before switching
it to backup source - no need to backup detached clocks. At this point
cbus clients are on different pll (used by boot-loader) only in early
initialization. Similarly skip detached clients during explicit dvfs
update (when dynamic ramp is enabled).

Change-Id: Ia7bfbe67b678f020538e10307a27fd72cf4026bf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R7993d622d09dd14e9d8500f12197fd32c224978e

6 years agoARM: tegra11: dvfs: Remove core dvfs table in simulation
Alex Frid [Tue, 15 May 2012 00:09:35 +0000]
ARM: tegra11: dvfs: Remove core dvfs table in simulation

Simulation setup over-clocks graphics (cbus) modules, and Tegra11
boot would fail if preliminary dvfs tables are enforced. Remove
tables for now to unblock simulation.

Change-Id: I398490b4aa0597c3f87483c03c8102bf36c65424
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102373
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>

Rebase-Id: Rb5605c2e115f1796b4bfc83b654eb5ca546c7dc5

6 years agoARM: defconfig: curacao: Enable CONFIG_USB_TEGRA
Rakesh Bodla [Fri, 11 May 2012 07:48:16 +0000]
ARM: defconfig: curacao: Enable CONFIG_USB_TEGRA

Enable tegra udc driver.

Bug 983006

Change-Id: If761a2eeb9dec01bd47ab0ca728eb43ac9ebb926
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/101924
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R048b2ea5f655b821d68b13834628fcd97fd99ccb

6 years agoARM: tegar11: clock: update the udc driver name
Rakesh Bodla [Fri, 11 May 2012 07:45:42 +0000]
ARM: tegar11: clock: update the udc driver name

Update the clocks structure to use new udc driver
name.

Bug 983006

Change-Id: I95c64b214aa845e4cbf509bca0416d80e6273aac
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/101923
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb6b365b5445e56ef9be22c65cbbdfa8ffe7fac3d

6 years agoARM: tegra11: clock: Remove non-supported emc bridge
Alex Frid [Wed, 9 May 2012 05:27:40 +0000]
ARM: tegra11: clock: Remove non-supported emc bridge

Change-Id: Ieb463e6138286b1c61ef71959b94f93f1cf4452e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101813
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3acd5e8e9e846f585d86ebd8ebf4e7b9d1c1bff4

6 years agousb: gadget: tegra: add support for FPGA
Rakesh Bodla [Fri, 11 May 2012 07:43:37 +0000]
usb: gadget: tegra: add support for FPGA

On FPGA VBUS is detected through VBUS A Session instead
of VBUS status. Updated this where ever it is necessary.
Also added the clearance of ASUS bit to prevent
auto suspend present in H/W.

Bug 983006

Change-Id: I91e4554e39703c861dc5055c24812b5d34615949
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/101514
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: Rd88ba8970196ad1c8d60f75614df474a53128556

6 years agoARM: tegra11: clock: Don't apply common limit to cbus users
Alex Frid [Sat, 5 May 2012 01:36:05 +0000]
ARM: tegra11: clock: Don't apply common limit to cbus users

The cbus dvfs table is currently constructed to guarantee safe
operations of the slowest client at any rate, and cbus maximum
rate at nominal voltage is applied as common limit to all cbus
shared users.

The latter provision is changed now: each shared user has its
own limit set equal to the maximum rate of the the respective
graphics module. Thus, individual users rate requests are no
longer throttled by the slowest one. Still final bus rate is
subject to worst case dvfs table, so this commit just allow for
unthrottled user request recording with no actual change in
final rates/voltages.

Change-Id: I89c463d2c52f4028ebaf433c69ac99b6131281e5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101863
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R37819131d668c8b056a489c19467900a97576063

6 years agoARM: tegra11: clock: Remove non-existed 3D2 clock
Alex Frid [Thu, 10 May 2012 00:24:01 +0000]
ARM: tegra11: clock: Remove non-existed 3D2 clock

Change-Id: I768b86ce93c5a2875a6f2b1406f7e02094aa55b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101812
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9e9aadb2e23ab91318e922a4d4d7008447f68d71

6 years agoARM: tegra11: clock: Don't round shared user request
Alex Frid [Thu, 3 May 2012 02:49:15 +0000]
ARM: tegra11: clock: Don't round shared user request

Keep raw individual shared user requests before aggregation - just
clip them to shared bus range. Apply bus rounding only after the
requests are aggregated.

Change-Id: I53889670e89363f47d3722825ecd5d6dd3d9fda7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101811
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Reffb58910b98e1c621ed6d0859005599f60c166a

6 years agoARM: tegra11: curacao: Set suspend mode to LP1
Bo Yan [Thu, 10 May 2012 02:14:06 +0000]
ARM: tegra11: curacao: Set suspend mode to LP1

System will disable LP2 if suspend mode is TEGRA_SUSPEND_NONE when
initializing suspend. Set it to TEGRA_SUSPEND_LP1 to unblock LP2.

Change-Id: I191d981280b7bc47378e24ecbd60f8bf586845cb
Reviewed-on: http://git-master/r/101645
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R22018e95ae812edfe8d31b4c3c6271b29bd13006

6 years agoARM: tegra: enable LP2 enable/disable function
Bo Yan [Wed, 9 May 2012 23:53:53 +0000]
ARM: tegra: enable LP2 enable/disable function

This removes the temporary hack putting there previously, thus
enabling us to control whether to enable or disable LP2 in idle.

Change-Id: Idaef7e0bca8b490ef1320adb40c6b01f263d4a80
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101641
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R74dcf2683007913e44dd67f4f2a2ac0e574349e7

6 years agoARM: tegra11: Update resume sequence
Bo Yan [Wed, 9 May 2012 17:39:49 +0000]
ARM: tegra11: Update resume sequence

New fields in flow controller CSR are cleared.
L2 cache is invalidated instead of L1
Redundant conditional compilation flag is removed.
Set up the correct L2 data RAM latency
Invalidate TLB for both L1 and L2

Change-Id: Id7cad3cc60a93a735c26158cf271a6b3f947d9ca
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101570
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R4fb21039d032853e795990920d6d1b8183c59c68

6 years agoARM: tegra11: CPU rail power up sequence
Bo Yan [Mon, 7 May 2012 21:24:20 +0000]
ARM: tegra11: CPU rail power up sequence

It is necessary to disable RAM repair bypass when CPU rail is
powered up.  This needs to be done even in case of HW controlled
CPU rail power-on.

This change also enables cluster switch to use "power_gate" flag
defined in sysfs to control the power gating mode. For LP0 entry
case, rail-gating is set to default.

Set default power gating mode for cluster switch to rail gating.
For chips that doesn't support symmetric power gating, "0" is
the default value which will trigger rail-gating.

Change-Id: Ia7ccb023118bbfba4fa53dc263bdfda59e29f089
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R50b64bfc236a664028edc822219af0d30d1af043

6 years agoARM: tegra11: Update wake interrupt
Bo Yan [Mon, 7 May 2012 20:58:03 +0000]
ARM: tegra11: Update wake interrupt

The register fields have changed in Tegra11. Update wake interrupt
to reflect new definitions.

Change-Id: Ia6931dde19ed7cee30bb247355cc6cb47336b841
Reviewed-on: http://git-master/r/101044
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R25c1c9a375f9aa28ae3829c256bd902233e4f5ad

6 years agoARM: tegra: disable powergating on simulation
Jeff Smith [Thu, 3 May 2012 00:26:56 +0000]
ARM: tegra: disable powergating on simulation

Change-Id: Ibcf0536bfb882dea1db7f7b61c68e3bbd562a291
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/101277
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Ra772f9a1905ee5cb1548a26eddc5ec6e99dbf80d

6 years agoARM: tegra11: curacao: No flip on probe for sim
Jeff Smith [Thu, 3 May 2012 23:05:59 +0000]
ARM: tegra11: curacao: No flip on probe for sim

Change-Id: I8910b19b053f4b69c289a70d69478707d8a9eb30
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/101278
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit <kchilds@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R590538fa5c76cdef4d53ae6714fbe003273b820b

6 years agoARM: tegra11: dvfs: Add core dvfs tables
Alex Frid [Sun, 29 Apr 2012 03:40:45 +0000]
ARM: tegra11: dvfs: Add core dvfs tables

Added preliminary dvfs tables for graphics (cbus) clocks.
Adjusted clocks maximum limits and cbus divider accordingly.

Change-Id: I0b0438a3ae7c91793fd69c9ea9d28634ea91751c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101085
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R02200e9dbb45fb6d77fe5bf3a32e0eaeecd1643a

6 years agoARM: tegra11: clock: Add PLLC2/PLLC3 to cbus clocks muxes
Alex Frid [Fri, 4 May 2012 03:45:03 +0000]
ARM: tegra11: clock: Add PLLC2/PLLC3 to cbus clocks muxes

Change-Id: Idd0bf4695bd4e773dbc3706af8c91292eb2f10a8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101084
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R6821cf66b08a7e9648c40192d669e5b131af3552

6 years agoARM: tegra11: clock: Skip cbus backup if dynamic ramp
Alex Frid [Fri, 4 May 2012 00:43:00 +0000]
ARM: tegra11: clock: Skip cbus backup if dynamic ramp

Skipped switch to cbus backup PLL if main PLL allows dynamic
ramp to the new target rate. Updated voltage requirements for
cbus clients explicitly after dynamic ramp is completed.

Change-Id: I0222c46b5a916d2c9cbad37b8b55e4271f06bd0a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101083
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9953861d62ddf045721df570a10d6fad07eb4e54

6 years agoARM: tegra11: clock: Update cbus backup divider dynamically
Alex Frid [Thu, 3 May 2012 23:18:14 +0000]
ARM: tegra11: clock: Update cbus backup divider dynamically

On Tegra11 graphics clocks range is very wide (almost 1:10). Using
fixed backup divider for all rates may create big rate dips during
buss rate change. To mitigate this effect, calculated cbus backup
divider dynamically for each target rate.

Change-Id: Ifb63f6431e2f360c5a408c22492b03ceb705f374
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101082
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R16b6209e1b6a31df6b980e65662abe37757c9291

6 years agoARM: tegra11: clock: Set minimum rate for dynamic ramp PLLs
Alex Frid [Tue, 1 May 2012 01:38:16 +0000]
ARM: tegra11: clock: Set minimum rate for dynamic ramp PLLs

Fill in minimum possible rate for PLLX, PLLC, PLLC2/C3
(for these PLLs minimum rate is high enough to affect real
client requests).

Signed-off-by: Alex Frid <afrid@nvidia.com>

Change-Id: I55a4ec3aa79290df9782ad274e72f111f23ccd9c
Reviewed-on: http://git-master/r/101081
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R0411c26134934e6d1092c6fe496d2e21b5d77331

6 years agoARM: tegra11: clock: Don't ignore host1x shared user
Alex Frid [Sat, 28 Apr 2012 05:24:43 +0000]
ARM: tegra11: clock: Don't ignore host1x shared user

So far, rate request for host1x shared user was ignored by graphics
bus (cbus) implementation, and host1x rate followed bus rate set by
other users with 1:2 ratio.

This policy has changed: host1x rate request is included into cbus
target rate calculation. Still the ratio between host1x rate and bus
rate is kept 1:2, and shared bus operations are adjusted accordingly.

Change-Id: Ia22695e8a760c91c288899507928af26fc42f310
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101080
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rf9ae12102ec1b4cca818723f3452213a532cc461

6 years agoARM: tegra11: clock: Update cbus operations
Alex Frid [Fri, 27 Apr 2012 19:21:12 +0000]
ARM: tegra11: clock: Update cbus operations

- Added support for non-identity ratio between cbus parent (PLLC) rate
and bus rate (the default ratio is kept 1:1)

- Added support for SHARED_AUTO users that just follow the bus, and by
itself do not require bus rate above the minimum (set Host1x as auto
user, for now)

- Set and propagate cbus designation flag PERIPH_ON_CBUS

- Updated cbus minimum rate calculation to skip placeholders (if
any) in DVFS tables

Change-Id: Idf752bb4b87726f5dca7955b155bc9aa73470cb6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101079
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R03edd4f05eaca22d9c51ae212593402ca3744c7c

6 years agoARM: tegra: curacao: power: Add PMU MAX77663 support
Pradeep Kumar [Tue, 24 Apr 2012 11:00:09 +0000]
ARM: tegra: curacao: power: Add PMU MAX77663 support

Register PMU MAX77663 and fill initial power rails as unused.

Bug 968626

Change-Id: I13db57222fc6a9a6f0084715a6394b68360960e7
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/98431
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit <kchilds@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R6b8ecb8ccd98cb64acc59918247df46ef925289a

6 years agoARM: defconfig: curacao: Enable CONFIG_USB_TEGRA
Bo Yan [Tue, 8 May 2012 16:41:09 +0000]
ARM: defconfig: curacao: Enable CONFIG_USB_TEGRA

Change-Id: I828db9bbd2bb4654961cfae3266a2db96987eb13
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101287
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra0d8475c5cf673b6c6ed7403c1c2aad8c901f0ca

6 years agoARM: tegra11: Fix wake-up condition
Bo Yan [Tue, 1 May 2012 17:21:40 +0000]
ARM: tegra11: Fix wake-up condition

For immediate wake, always use WAITEVENT as the wake-up condition

bug 952631

Change-Id: Ie1fe9790c6559d3be41b30ad7c0792721140cf2e
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/99816
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: R4eada70f2664deb5275fca53e1792b55e99483c0

6 years agoARM: tegar11: clock: Handle DFLL during LP2 state
Alex Frid [Thu, 26 Apr 2012 22:45:35 +0000]
ARM: tegar11: clock: Handle DFLL during LP2 state

Expanded CPU clock control to handle DFLL when fast CPU0
enters/exits LP2 state:
- switch DFLL to open loop on LP2 entry
- restore closed loop DFLL operations on LP2 exit

Bug 871124

Change-Id: Icf88caac29f04dd5fdce6215c3f2459147b99c96
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99753
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb800390fdd1a443037ee960d91a31262c5b10e9d

6 years agoARM: tegar11: clock: Handle DFLL during CPU mode switch
Alex Frid [Wed, 25 Apr 2012 05:21:33 +0000]
ARM: tegar11: clock: Handle DFLL during CPU mode switch

Expanded CPU clock control to handle DFLL when switching between
fast G-CPU and slow LP-CPU modes:
- keep DFLL in open loop during the switch
- disable DFLL after the switch from G to LP mode
- restore closed loop DFLL operations after the switch from LP to G
mode.

Bug 871124

Change-Id: Ieba1345fc8aa332fea577f0c23389b78e79b85d2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R0f61df7b100db7556bf32800e6e2cec6719aff33

6 years agoARM: tegra11: clock: Add MUX flag to CPU super-clocks
Alex Frid [Thu, 26 Apr 2012 04:22:50 +0000]
ARM: tegra11: clock: Add MUX flag to CPU super-clocks

Added MUX flag to both G and LP CPU super-clock descriptors to make
sure that input clock sources are temporarily enabled when changing
disabled super clock parent (set_parent API enforce clock enable on
clocks with MUX attribute).

Change-Id: Ia02b7170eed66af5c573dca4d8065356e510ef0b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99751
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R79cbe64da951425a28cb1fff90958e5f52fb2309

6 years agoARM: tegra11: Use wfi for power gating
Bo Yan [Mon, 30 Apr 2012 18:48:51 +0000]
ARM: tegra11: Use wfi for power gating

Change-Id: I2331b92848c86f09866850d19d5b8a63d9190bca
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/99691
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: R8f778d45d9e34a35f176551aff6d05102b84a983

6 years agoARM: tegra: clock: Don't lock clock tree for emulation
Alex Frid [Fri, 27 Apr 2012 06:01:59 +0000]
ARM: tegra: clock: Don't lock clock tree for emulation

Don't lock clock tree for emulation platforms - the locking loop
would take forever with crawling CPU in emulation.

Change-Id: If68c765c323af5c9f0d500959d136eef3766d786
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99532
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb00cbdf24429a4eaa59f58c9fffd1b28064f0d14

6 years agoARM: tegra: curacao: Add ganged mode support
Animesh Kishore [Mon, 30 Apr 2012 08:25:46 +0000]
ARM: tegra: curacao: Add ganged mode support

Adding changes required to support ganged mode.

Bug 944115

Change-Id: Icdc6d1bb51709305b2ed94d31c24c841f9fbc308
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/99400
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re78811bf06465239789f13f082ff10eafc400e0a

6 years agoARM: tegra: dvfs: Pull in dvfs on non-silicon platforms
Alex Frid [Fri, 27 Apr 2012 04:20:24 +0000]
ARM: tegra: dvfs: Pull in dvfs on non-silicon platforms

Compile production dvfs code for all types of tegra platforms.
On non-silicon platforms it is still dormant as long as voltage
regulators are not connected. Since changes in dvfs files layout
introduced by commit 56a1f60aae90be8e1a9bfc455477c3bd3a9fffb3
are no longer needed, reverted them to facilitate future merge
with main tegra branch.

Change-Id: Idb7307e0d87b3dbbba8af6fbb46583b90532e4e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99313
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R712284105ca8053a69f7732302e19c63160d92c1

6 years agoARM: tegra: curacao: Enable MAX77663 MFD and Regulator
Pradeep Kumar [Tue, 24 Apr 2012 08:11:49 +0000]
ARM: tegra: curacao: Enable MAX77663 MFD and Regulator

Bug 968626

Change-Id: I3853dc3c6514eda4eba89242f95c4a631bad3d3b
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/98430
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rff9e92bfea4f72c91e17e14cfdac94a1a8f93e1a

6 years agoarm: tegra: Enable tegra odm fuse
Ashwini Ghuge [Thu, 5 Apr 2012 05:03:29 +0000]
arm: tegra: Enable tegra odm fuse

Change-Id: I1afdcb5820f18e58d8713b2d12b625183d20fb66
Reviewed-on: http://git-master/r/94654
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R86d0bf28448721dfe1cc3d3a8404511cb33a3708

6 years agoARM: tegra: curacao: Enable NVAVP
Shashank Garg [Thu, 26 Apr 2012 07:31:05 +0000]
ARM: tegra: curacao: Enable NVAVP

Disable mediaserver

Change-Id: Ie5b655532f05f43fb2aa2663421cb1dcfa1ee167
Signed-off-by: Shashank Garg <sgarg@nvidia.com>
Reviewed-on: http://git-master/r/99020
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R26b7571cc4512150c61d16da1735447d9f15bade

6 years agoarm: tegra: curacao: Register NVAVP with nvhost
Shashank Garg [Thu, 26 Apr 2012 07:27:45 +0000]
arm: tegra: curacao: Register NVAVP with nvhost

Change-Id: Icb3917f1f42132aeed4d617beb6578598641c3e7
Signed-off-by: Shashank Garg <sgarg@nvidia.com>
Reviewed-on: http://git-master/r/99019
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

Rebase-Id: R2c89952d67b58354bcdc4477a3ba3e45c1f3ae9d

6 years agoARM: tegra11: clock: Add NVAVP driver clocks
Alex Frid [Wed, 25 Apr 2012 20:21:00 +0000]
ARM: tegra11: clock: Add NVAVP driver clocks

Change-Id: I3eedf6b085c7a44e3a0f9e6b93c249bdc3490ade
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/98897
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R8880ae0f4e1443c04ba3ed1d2bfad5dd3226521e

6 years agoARM: tegra11: Disable d-cache before power gating
Bo Yan [Wed, 25 Apr 2012 01:18:24 +0000]
ARM: tegra11: Disable d-cache before power gating

For Cortex A15, the power down sequence requires D cache be
disabled before flushing cache and power gating the CPU.

bug 971396

Change-Id: I15c169c82780022877a0a49aa6403a9e5fd9d83f
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/98581
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R9af0f0af47ebb7260215b314cb958098a029183c

6 years agoARM: tegar11: clock: Add DFLL source to CPU clock control
Alex Frid [Thu, 19 Apr 2012 06:17:26 +0000]
ARM: tegar11: clock: Add DFLL source to CPU clock control

Added mechanism to switch fast G-CPU clock source from PLL to DFLL
and vice versa (slow LP CPU does not have DFLL source). New sysfs
node /sys/module/tegra11_clocks/use_dfll controls this option
(disabled by default, for now).

Bug 871124

Change-Id: I9c5e50c1c9e606ae031e5305aac95f1704710b9b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/98580
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb5f306841ad0bff2f25fa1585f9c40ae32ffc19f

6 years agoARM: tegra11: dvfs: Update CL-DVFS rate calculations
Alex Frid [Tue, 24 Apr 2012 03:22:34 +0000]
ARM: tegra11: dvfs: Update CL-DVFS rate calculations

Updated CL-DVFS rate calculations to avoid 64-bit arithmetic and make
sure that the rate stays the same after get_rate=>set_rate call chain.
Set minimum CL-DVFS rate to exact multiple of reference rate units, so
that minimum rate won't be crossed as a result of set rate round down
operation.

Bug 871124

Change-Id: Iafd73b94e7d68694a93f411d919e687ec165b451
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/98579
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9b14c0823f28762cd5ba3f6c9f38a4610b2d8156

6 years agoARM: tegra: Fake TSC frequency for emulation
Bo Yan [Sat, 21 Apr 2012 02:32:11 +0000]
ARM: tegra: Fake TSC frequency for emulation

The TSC clock rate in emulation is around 100K+,
fake its frequency so software can work in emulation.

Change-Id: Ib33e863f8ce2508affbd7c22083fc49739c1bb48
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/98079
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Bond <rbond@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>

Rebase-Id: R9355e093921aa4f02af1789cd79004e3510567df

6 years agoARM: tegra: curacao: power: Add vddio_sdmmc gpio regulator
Pradeep Kumar [Thu, 19 Apr 2012 08:07:56 +0000]
ARM: tegra: curacao: power: Add vddio_sdmmc gpio regulator

-Enable pinmux for GPIO_PV1.
-Enable vddio_sdmmc  gpio regulator for sdmmc3 on GPIO_PV1.

Bug 953433
Bug 837138

Change-Id: I8f61328926fe0f6b781571ce46d0b3c7ff97fe82
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/97565
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R9f9e9ce09c010ff8914018b72e41b50c41a2b63b

6 years agotegra: usb: host: set STREAM_DISABLE bit to 1
vjagadish [Tue, 20 Mar 2012 10:45:14 +0000]
tegra: usb: host: set STREAM_DISABLE bit to 1

Software WAR for FPGA system, setting this bit
will disable standard double buffering scheme.

Bug 950522

Change-Id: I1702e4480af07838ad8c4a62deaafb2fc4dfdefc
Signed-off-by: vjagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/91195
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R49c45ad355e2c6c7ce114241ecf5fe590f992f4c

6 years agoARM: tegra11: clock: Update CPU clock entries
Alex Frid [Thu, 19 Apr 2012 00:19:08 +0000]
ARM: tegra11: clock: Update CPU clock entries

- Increased CPU rate limits to 1.8GHz
- Added and populated DFLL source entries in cpu clock descriptors
- Added auto_control attribute to rail descriptor

Change-Id: I820e3ddeec5d49b4319c2edb31b083bab1fed35b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/98107
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rfeac97340431d840eef98dbe571f8914bf821f11

6 years agoARM: tegra11: clock: Add shared sclk users
Alex Frid [Sat, 21 Apr 2012 05:59:43 +0000]
ARM: tegra11: clock: Add shared sclk users

Added shared system clock users (SPI, wake, floor) to match tegra30
nomenclature.

Signed-off-by: Alex Frid <afrid@nvidia.com>

Change-Id: I523bfb9e74746441007b4f0ae3e6d60e2049c9bd
Reviewed-on: http://git-master/r/98083
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9dde55547cd922524caf3bca1e2a0885141fc52a

6 years agoARM: tegra: curacao: turn on gpio regulator feature
Pradeep Kumar [Thu, 19 Apr 2012 04:19:53 +0000]
ARM: tegra: curacao: turn on gpio regulator feature

Bug 953433
Bug 837138

Change-Id: Ib0089aad4a9aa2b5256a33b75bb3aa0f0a3da5cc
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/97564
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R92d3eff46553108bc981120839ec65c8dc11337a

6 years agoARM: tegra11: dvfs: Enable CL-DVFS initialization
Alex Frid [Sun, 15 Apr 2012 03:48:25 +0000]
ARM: tegra11: dvfs: Enable CL-DVFS initialization

Bug 871124

Change-Id: I53e308bdcb66b788ae93551c5a6dfe953e990ce9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/97498
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb995e4e10d7d6fbfba14d47f70555585ac7a87db

6 years agoARM: tegra11: clock: Skip redundant set backup rate
Alex Frid [Sun, 15 Apr 2012 05:10:56 +0000]
ARM: tegra11: clock: Skip redundant set backup rate

Skip redundant set CPU backup rate call if backup source is already
at target rate.

Change-Id: I80238ca7754d8c7d89157fbcdafbca3e46760b52
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/97119
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7707cb009550da5b68e73f13ec78e352be6823b8

6 years agoARM: tegra11: clock: Enable PLLD2 clock for PG
Krupal Divvela [Tue, 17 Apr 2012 11:14:16 +0000]
ARM: tegra11: clock: Enable PLLD2 clock for PG

Enable PLLD2 clock also along with CSI clock.
This is meant for CSI pattern generator.

Bug 946957

Change-Id: I73634c15f128fd65f36da9d31f2a49e6acb3cad8
Signed-off-by: Krupal Divvela <kdivvela@nvidia.com>
Reviewed-on: http://git-master/r/97005
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7075a0fc9917442f419c8fbcb9b066f313d7addd

6 years agoARM: tegra: curacao: Add Curacao board defconfig
Preetham Chandru [Mon, 16 Apr 2012 13:25:21 +0000]
ARM: tegra: curacao: Add Curacao board defconfig

Bug 944760
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Tested-by: Chetan Hooli <chooli@nvidia.com>
Change-Id: I0b44ebc37f2607c2ce9a5580d16352f50edf2b04
Reviewed-on: http://git-master/r/96750
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chetan Hooli <chooli@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb943477aa03e282d2915cd1d99c0537ec5b3acfb

6 years agoARM: tegra: curacao: Initialize i2c slave platform data
Chaitanya Bandi [Mon, 16 Apr 2012 08:40:10 +0000]
ARM: tegra: curacao: Initialize i2c slave platform data

Initialized i2c slave platform data on bus no. 1.

Bug 837139

Change-Id: Id7d1280760fc2c9c9656d8f205cb69137d2be250
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/96682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R44961f93190963dc7785461d257131bc0557ce6e

6 years agoarch: arm: tegra: Add i2c slave devices
Chaitanya Bandi [Fri, 3 Feb 2012 10:51:00 +0000]
arch: arm: tegra: Add i2c slave devices

Added i2c slave devices for i2c controllers.

Bug 837139

Change-Id: I407d846d0fc2409acfe7de005be1d0da9921b491
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/96681
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R60c4966390426033ec101b9313b89f541c7f19c2

6 years agoARM: tegra: Rename spi drivers
Amit Kamath [Mon, 20 Feb 2012 05:05:18 +0000]
ARM: tegra: Rename spi drivers

Correcting naming as per standards followed by linux community
BUG 815557

Change-Id: Iefa97ecdb8e54c7e595aeb61b89daa5014eeef5a
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/84738
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R35d486a4f93185964bcf89e98b72b94de8810f26

6 years agoarm: config: tegra: curacao: Enable I2C Slave
Chaitanya Bandi [Tue, 14 Feb 2012 06:46:51 +0000]
arm: config: tegra: curacao: Enable I2C Slave

Enabling I2C Slave functionality

Change-Id: I9de278892567460c374f1636244c416f753f436c
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/83700
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R685c607d688f94d6310591f644f570d98d19a554

6 years agoARM: tegra11: clock: Update CPU clock control
Alex Frid [Tue, 10 Apr 2012 21:52:22 +0000]
ARM: tegra11: clock: Update CPU clock control

Update CPU clock control to take advantage of dynamic ramp support
available on Tegra11 PLLX, and mitigate di/dt spikes caused by CPU
frequency jumps. New implementation eliminates switch to backup clock
source for all transitions between high rates above PLLX VCO minimum
(700MHz). VCO minimum is also set as intermediate rate for transitions
that require switch to backup source (backup rate 200MHz). As a result
maximum rate jump in the entire CPU frequency range is limited to
(VCO minimum - backup rate) -- 500MHz.

Change-Id: I820ba075c4fcf6a50a0af797de379ad7b1ab5325
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/95745
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Rdd567b1e23cb97efacf37c64c2320d36489ae97c

6 years agoARM: tegra11: curacao: Change CL-DVFS parameters
Alex Frid [Sun, 15 Apr 2012 03:36:03 +0000]
ARM: tegra11: curacao: Change CL-DVFS parameters

Bug 871124

Change-Id: I49e3abcc4bda6891c42b8cec12e2cb8375b05af9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/96629
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R88480c56f1f004583023bb46aa3191b7ed42bd2e

6 years agoARM: tegra11: dvfs: Update CL-DVFS configuration
Alex Frid [Sun, 15 Apr 2012 03:29:59 +0000]
ARM: tegra11: dvfs: Update CL-DVFS configuration

- Changed type of gain control parameter to "signed"
- Added gain scale parameter
- Fixed I2C high speed divider calculation

Bug 871124

Change-Id: I9dbda5364b1889462341e5c33e2e423ab8140667
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/96628
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R09f9a8975dc494fc8e09133e90ce679b68fb8e82

6 years agoARM: tegra11: dvfs: Move CL-DVFS debugfs entries
Alex Frid [Sun, 15 Apr 2012 02:05:24 +0000]
ARM: tegra11: dvfs: Move CL-DVFS debugfs entries

Moved CL-DVFS debugfs entries under dfll_cpu clock directory.

Bug 871124

Change-Id: I5e531383be2ab5f862a2795a0775eb6a60269b8b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/96627
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rffbc982d35e1aaa465a084e242f2196939e97891

6 years agoARM: tegra: Expand APB aperture to 2MB
Alex Frid [Sun, 15 Apr 2012 01:01:24 +0000]
ARM: tegra: Expand APB aperture to 2MB

Change-Id: I5d740a61084e19a7879c5bb0d796f293d068caff
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/96626
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R37a8b423b536d72b147505fbfdc20b222edb3040

6 years agoARM: tegra11: clock: Change CPU, SCLK low rate sources
Alex Frid [Sat, 7 Apr 2012 04:55:04 +0000]
ARM: tegra11: clock: Change CPU, SCLK low rate sources

So far CPU low rates were sourced from undivided PLLP_OUT0 output via
CPU complex 7.1 divider. Control register for this divider is shared
with super-clock skipper, which in turn is controlled by thermal h/w
on Tegra11. In addition some CPU clock sources (PLLX, DFLL) may bypass
7.1 divider, and other sources may not. To avoid concurrency issues
and simplify CPU clock control, s/w would keep default 1:1 settings
for CPU complex 7.1 divider, and never use it for rate scaling.

Instead, secondary PLLP_OUT4 divider is now used as CPU clock low rate
source. Respectively low rate source for SCLK has been changed from
PLLP_OUT4 to PLLP_OUT2.

Change-Id: Ic8c313b2295d0359542e963e239441f6d53700f9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/95240
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R5ec5f106b82027d0a053ede714841d20a60dcb6b

6 years agoARM: tegra11: clock: Clip VCO min on dynamic ramp PLLs
Alex Frid [Thu, 12 Apr 2012 18:37:01 +0000]
ARM: tegra11: clock: Clip VCO min on dynamic ramp PLLs

Clipped VCO minimum on dynamic ramp PLLs to exact multiple of input
rate to avoid crossover when rounding PLLs feedback divider settings.
Updated VCO minimum levels for PLLX, PLLC, PLLC2, PLLC3 according to
the respective specifications.

Signed-off-by: Alex Frid <afrid@nvidia.com>

Change-Id: If0abebced04c71e53a01458907b22c224e600f8f
Reviewed-on: http://git-master/r/96290
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R60c08f330f262f8afca2bb71fb9553e9ac67878b

6 years agoARM: tegra: curacao: Initialize i2c platform data
Alok Chauhan [Mon, 13 Feb 2012 04:51:00 +0000]
ARM: tegra: curacao: Initialize i2c platform data

Bug 837139

Change-Id: I8baf14041d8f1443163147cb17a07b2e5682b092
Signed-off-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-on: http://git-master/r/83338
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Ra9a0d052d0faa97af518db47b94a55135cb9437a

6 years agoARM: tegra: clock: Use tegra11 devid instead of tegra
Alok Chauhan [Thu, 2 Feb 2012 08:47:04 +0000]
ARM: tegra: clock: Use tegra11 devid instead of tegra

Updated devid of i2c to tegra11-i2c.* and conid as i2c-div.

Bug 837139

Change-Id: I1ea7ecd16a9ae0cff48b6494508d9ce53751554a
Signed-off-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-on: http://git-master/r/78929
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R17e50e698166586274b699282f97afb0ec989845

6 years agoARM: tegra: curacao: turn on features for Android
Bo Yan [Wed, 11 Apr 2012 18:08:32 +0000]
ARM: tegra: curacao: turn on features for Android

The enabled features are not a complete set required for booting
android since not all emulation platform can support them. So it
is necessary to manually turn on some other features to boot
Android

Change-Id: Ia6abd80bc79f22d8e53d67847f3d29561b5df090
Reviewed-on: http://git-master/r/95912
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R0276b9d265e6d9ddc425f86a196dfe69a1e6ab4b

6 years agoARM: tegra11: dvfs: Re-factor CL-DVFS support
Alex Frid [Sun, 8 Apr 2012 02:36:49 +0000]
ARM: tegra11: dvfs: Re-factor CL-DVFS support

Since CL-DVFS module is now represented in Tegra11 clock framework
as dynamic frequency lock loop (DFLL) clock source, and all CL_DVFS
operations are protected by DFLL clock lock, moved the CL-DVFS object
instance from tegra_cl_dvfs.c file to tegra11_clocks.c file, and
updated all respective APIs accordingly. As a result tegra_cl_dvfs.c
contains only chip independent APIs that can be shared between clock
frameworks for different tegra architectures that support CL-DVFS.

Change-Id: I8ae2d6fb8ef58ab1a41cca778742ba1ab0af78a1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/95513
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rdc4320a73563cc3a8a3e9bffad4e2c6663da68af

6 years agoARM: tegra: curacao: Enable OV14810 camera sensor
Krupal Divvela [Wed, 11 Apr 2012 08:45:16 +0000]
ARM: tegra: curacao: Enable OV14810 camera sensor

Bug 946945

Change-Id: I9cf33202b100ee0a95ccd332a8ffc53b2ffdf2d3
Signed-off-by: Krupal Divvela <kdivvela@nvidia.com>
Reviewed-on: http://git-master/r/94210
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R6e030e09b69c5a8a2ea9286657b3f2416f218d78

6 years agoARM: tegra: Switch off inlining get_core_count
Amit Kamath [Tue, 10 Apr 2012 09:58:26 +0000]
ARM: tegra: Switch off inlining get_core_count

bug 949932

get_core_count function was optimized for only case of T20. Since the
available_cpus function has got conditional compilation. This resulted
in execution of mrc instruction to cop which is meant for A15 arm core.

Change-Id: Ia9c0f284362adaf61fa18fe05370954666a283bc
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/95569
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R212658bcf5a45e44ffec2a182ab9074a01d0af74

6 years agoARM: tegra11: clock: Auto-detect PLLP rate in clock init
Alex Frid [Thu, 5 Apr 2012 06:11:05 +0000]
ARM: tegra11: clock: Auto-detect PLLP rate in clock init

Tegra11 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz/FPGA, 408MHz/SILICON, or
204MHz/SILICON (option no yet supported). This commit implements
auto-detection of PLLP rate during clock tree initialization.

(ported from commit 1512190bb0bb1b087e40c977731e3ac851ceffff)

Change-Id: I92105722fe3fc2b937ebc1d6cbc20149692db4f6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94997
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra1eea48075924942eb5eed9e2d278204d584646b

6 years agoARM: tegra11: clock: Update CPU rate change permissions
Alex Frid [Thu, 5 Apr 2012 03:05:49 +0000]
ARM: tegra11: clock: Update CPU rate change permissions

- Compile in CPU rate change function on FPGA platform
- Allow cpu rate change on FPGA and SIMULATION platforms even if
cpu regulator is not connected.
- Do not allow rate change on SILICON if cpu regulator is
not connected.

Change-Id: Id81547cc3c114a0c1571adc36425e5e988d06407
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94643
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb99a1c8cda823e1cc1ea29e49e8dc747977543d4

6 years agoARM: tegra: curacao: Enable USB support
Rakesh Bodla [Tue, 7 Feb 2012 11:12:49 +0000]
ARM: tegra: curacao: Enable USB support

Bug 837132

Change-Id: Ied0627e3cf838568eb7f908451e9129f9bff3138
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/79781
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R5e45b92afab26ecf7965e0f64d60f476023133da

6 years agoARM: tegra11: dvfs: Re-arrange CL-DVFS debugfs entries
Alex Frid [Wed, 4 Apr 2012 05:57:59 +0000]
ARM: tegra11: dvfs: Re-arrange CL-DVFS debugfs entries

CL-DVFS debugfs entries are defines as follows:

/d/tegra_cl_dvfs/dfll_lock - controls switching between CL-DVFS
open (dfll_lock = 0) and closed (dfll_lock = 1) loop modes

/d/tegra_cl_dvfs/monitor - provides read-only access to CL-DVFS
monitoring register

/d/tegra_cl_dvfs/register - provides direct Cl-DVFS registers access:
cat /d/tegra_cl_dvfs/register - dump CL_DVFS registers;
echo [0xYY] = 0xZZZZ > /d/tegra_cl_dvfs/register - write ZZZZ value
to register at YY offset.

Change-Id: Id354afa0a6530165ae6ecb9589c2500e739d0a5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94604
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R79c196f4512534d7e0c70c71d468f3b7e93cd822

6 years agoARM: tegra11: dvfs: Update CL_DVFS error logging
Alex Frid [Wed, 4 Apr 2012 00:27:31 +0000]
ARM: tegra11: dvfs: Update CL_DVFS error logging

Change-Id: I5ba3e6fb0b3ff5c008d792a10bc9ad381e1893ee
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94603
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R55fa60ba839f75c5ce5e75bec0f37fd79b7bdf0b

6 years agoARM: tegra11: clock: Add DFLL clock source
Alex Frid [Tue, 3 Apr 2012 05:38:22 +0000]
ARM: tegra11: clock: Add DFLL clock source

Added dynamic frequency lock loop (DFLL) clock to Tegra11 clock tree.
Define DFLL enable, disable, set rate operations are wrappers around
the respective CL-DVFS APIs.

Removed debugfs nodes (as they duplicate DFLL clock debugfs now):
/d/tegra_cl_dvfs/cl_dvfs_enable
/d/tegra_cl_dvfs/cl_dvfs_request

Change-Id: Ibb9f2265c11cdc3231d6bc4a8dcf001fe0295929
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94602
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R6d00deedc32fa41af7e349b95ed41293f83df95e

6 years agoARM: tegra11: dvfs: Fix CL-DVFS LUT alignment
Alex Frid [Wed, 4 Apr 2012 18:57:53 +0000]
ARM: tegra11: dvfs: Fix CL-DVFS LUT alignment

CL-DVFS output look-up table alignment is 32-bit word, not byte as
it was implemented.

Change-Id: I54dae12bc0a7062fd9264014c7d089532864221d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94601
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Ra13c6773d992ac0d7f42df3cb391c0bdc3e29a98

6 years agoarm: tegra: curacao: Use DCb as default display
Bo Yan [Fri, 9 Mar 2012 02:53:36 +0000]
arm: tegra: curacao: Use DCb as default display

Change-Id: Iac0bf761502a62dd1513024bfe2c2254c9f765e6
Reviewed-on: http://git-master/r/88976
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R7e33cbe4cb9630de29de3df28c5586fdb6b632fc

6 years agoarm: tegra: config: Select ARM_SMP_TWD
Prashant Gaikwad [Wed, 4 Apr 2012 12:29:50 +0000]
arm: tegra: config: Select ARM_SMP_TWD

Change-Id: Iacde8fab53fc2ff413262e0126acc16abc76844a
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/94514
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R3efe90ed0de49bfa82ab5cfafdc803eea3ddeed7